ls1043aqds.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Copyright 2019-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/ppa.h>
  17. #include <asm/arch/fdt.h>
  18. #include <asm/arch/mmu.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/soc.h>
  21. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22. #include <ahci.h>
  23. #include <hwconfig.h>
  24. #include <mmc.h>
  25. #include <scsi.h>
  26. #include <fm_eth.h>
  27. #include <fsl_esdhc.h>
  28. #include <fsl_ifc.h>
  29. #include <spl.h>
  30. #include "../common/i2c_mux.h"
  31. #include "../common/qixis.h"
  32. #include "ls1043aqds_qixis.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. enum {
  35. MUX_TYPE_GPIO,
  36. };
  37. /* LS1043AQDS serdes mux */
  38. #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
  39. #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
  40. #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
  41. #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
  42. #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
  43. #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
  44. #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
  45. #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
  46. #define CFG_UART_MUX_MASK 0x6
  47. #define CFG_UART_MUX_SHIFT 1
  48. #define CFG_LPUART_EN 0x1
  49. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  50. void i2c_early_init_f(void);
  51. #endif
  52. #ifdef CONFIG_TFABOOT
  53. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  54. {
  55. "nor0",
  56. CONFIG_SYS_NOR0_CSPR,
  57. CONFIG_SYS_NOR0_CSPR_EXT,
  58. CONFIG_SYS_NOR_AMASK,
  59. CONFIG_SYS_NOR_CSOR,
  60. {
  61. CONFIG_SYS_NOR_FTIM0,
  62. CONFIG_SYS_NOR_FTIM1,
  63. CONFIG_SYS_NOR_FTIM2,
  64. CONFIG_SYS_NOR_FTIM3
  65. },
  66. },
  67. {
  68. "nor1",
  69. CONFIG_SYS_NOR1_CSPR,
  70. CONFIG_SYS_NOR1_CSPR_EXT,
  71. CONFIG_SYS_NOR_AMASK,
  72. CONFIG_SYS_NOR_CSOR,
  73. {
  74. CONFIG_SYS_NOR_FTIM0,
  75. CONFIG_SYS_NOR_FTIM1,
  76. CONFIG_SYS_NOR_FTIM2,
  77. CONFIG_SYS_NOR_FTIM3
  78. },
  79. },
  80. {
  81. "nand",
  82. CONFIG_SYS_NAND_CSPR,
  83. CONFIG_SYS_NAND_CSPR_EXT,
  84. CONFIG_SYS_NAND_AMASK,
  85. CONFIG_SYS_NAND_CSOR,
  86. {
  87. CONFIG_SYS_NAND_FTIM0,
  88. CONFIG_SYS_NAND_FTIM1,
  89. CONFIG_SYS_NAND_FTIM2,
  90. CONFIG_SYS_NAND_FTIM3
  91. },
  92. },
  93. {
  94. "fpga",
  95. CONFIG_SYS_FPGA_CSPR,
  96. CONFIG_SYS_FPGA_CSPR_EXT,
  97. CONFIG_SYS_FPGA_AMASK,
  98. CONFIG_SYS_FPGA_CSOR,
  99. {
  100. CONFIG_SYS_FPGA_FTIM0,
  101. CONFIG_SYS_FPGA_FTIM1,
  102. CONFIG_SYS_FPGA_FTIM2,
  103. CONFIG_SYS_FPGA_FTIM3
  104. },
  105. }
  106. };
  107. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  108. {
  109. "nand",
  110. CONFIG_SYS_NAND_CSPR,
  111. CONFIG_SYS_NAND_CSPR_EXT,
  112. CONFIG_SYS_NAND_AMASK,
  113. CONFIG_SYS_NAND_CSOR,
  114. {
  115. CONFIG_SYS_NAND_FTIM0,
  116. CONFIG_SYS_NAND_FTIM1,
  117. CONFIG_SYS_NAND_FTIM2,
  118. CONFIG_SYS_NAND_FTIM3
  119. },
  120. },
  121. {
  122. "nor0",
  123. CONFIG_SYS_NOR0_CSPR,
  124. CONFIG_SYS_NOR0_CSPR_EXT,
  125. CONFIG_SYS_NOR_AMASK,
  126. CONFIG_SYS_NOR_CSOR,
  127. {
  128. CONFIG_SYS_NOR_FTIM0,
  129. CONFIG_SYS_NOR_FTIM1,
  130. CONFIG_SYS_NOR_FTIM2,
  131. CONFIG_SYS_NOR_FTIM3
  132. },
  133. },
  134. {
  135. "nor1",
  136. CONFIG_SYS_NOR1_CSPR,
  137. CONFIG_SYS_NOR1_CSPR_EXT,
  138. CONFIG_SYS_NOR_AMASK,
  139. CONFIG_SYS_NOR_CSOR,
  140. {
  141. CONFIG_SYS_NOR_FTIM0,
  142. CONFIG_SYS_NOR_FTIM1,
  143. CONFIG_SYS_NOR_FTIM2,
  144. CONFIG_SYS_NOR_FTIM3
  145. },
  146. },
  147. {
  148. "fpga",
  149. CONFIG_SYS_FPGA_CSPR,
  150. CONFIG_SYS_FPGA_CSPR_EXT,
  151. CONFIG_SYS_FPGA_AMASK,
  152. CONFIG_SYS_FPGA_CSOR,
  153. {
  154. CONFIG_SYS_FPGA_FTIM0,
  155. CONFIG_SYS_FPGA_FTIM1,
  156. CONFIG_SYS_FPGA_FTIM2,
  157. CONFIG_SYS_FPGA_FTIM3
  158. },
  159. }
  160. };
  161. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  162. {
  163. enum boot_src src = get_boot_src();
  164. if (src == BOOT_SOURCE_IFC_NAND)
  165. regs_info->regs = ifc_cfg_nand_boot;
  166. else
  167. regs_info->regs = ifc_cfg_nor_boot;
  168. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  169. }
  170. #endif
  171. int checkboard(void)
  172. {
  173. #ifdef CONFIG_TFABOOT
  174. enum boot_src src = get_boot_src();
  175. #endif
  176. char buf[64];
  177. #ifndef CONFIG_SD_BOOT
  178. u8 sw;
  179. #endif
  180. puts("Board: LS1043AQDS, boot from ");
  181. #ifdef CONFIG_TFABOOT
  182. if (src == BOOT_SOURCE_SD_MMC)
  183. puts("SD\n");
  184. else {
  185. #endif
  186. #ifdef CONFIG_SD_BOOT
  187. puts("SD\n");
  188. #else
  189. sw = QIXIS_READ(brdcfg[0]);
  190. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  191. if (sw < 0x8)
  192. printf("vBank: %d\n", sw);
  193. else if (sw == 0x8)
  194. puts("PromJet\n");
  195. else if (sw == 0x9)
  196. puts("NAND\n");
  197. else if (sw == 0xF)
  198. printf("QSPI\n");
  199. else
  200. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  201. #endif
  202. #ifdef CONFIG_TFABOOT
  203. }
  204. #endif
  205. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  206. QIXIS_READ(id), QIXIS_READ(arch));
  207. printf("FPGA: v%d (%s), build %d\n",
  208. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  209. (int)qixis_read_minor());
  210. return 0;
  211. }
  212. bool if_board_diff_clk(void)
  213. {
  214. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  215. return diff_conf & 0x40;
  216. }
  217. unsigned long get_board_sys_clk(void)
  218. {
  219. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  220. switch (sysclk_conf & 0x0f) {
  221. case QIXIS_SYSCLK_64:
  222. return 64000000;
  223. case QIXIS_SYSCLK_83:
  224. return 83333333;
  225. case QIXIS_SYSCLK_100:
  226. return 100000000;
  227. case QIXIS_SYSCLK_125:
  228. return 125000000;
  229. case QIXIS_SYSCLK_133:
  230. return 133333333;
  231. case QIXIS_SYSCLK_150:
  232. return 150000000;
  233. case QIXIS_SYSCLK_160:
  234. return 160000000;
  235. case QIXIS_SYSCLK_166:
  236. return 166666666;
  237. }
  238. return 66666666;
  239. }
  240. unsigned long get_board_ddr_clk(void)
  241. {
  242. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  243. if (if_board_diff_clk())
  244. return get_board_sys_clk();
  245. switch ((ddrclk_conf & 0x30) >> 4) {
  246. case QIXIS_DDRCLK_100:
  247. return 100000000;
  248. case QIXIS_DDRCLK_125:
  249. return 125000000;
  250. case QIXIS_DDRCLK_133:
  251. return 133333333;
  252. }
  253. return 66666666;
  254. }
  255. int dram_init(void)
  256. {
  257. /*
  258. * When resuming from deep sleep, the I2C channel may not be
  259. * in the default channel. So, switch to the default channel
  260. * before accessing DDR SPD.
  261. *
  262. * PCA9547 mount on I2C1 bus
  263. */
  264. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  265. fsl_initdram();
  266. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  267. defined(CONFIG_SPL_BUILD)
  268. /* This will break-before-make MMU for DDR */
  269. update_early_mmu_table();
  270. #endif
  271. return 0;
  272. }
  273. int i2c_multiplexer_select_vid_channel(u8 channel)
  274. {
  275. return select_i2c_ch_pca9547(channel, 0);
  276. }
  277. void board_retimer_init(void)
  278. {
  279. u8 reg;
  280. int bus_num = 0;
  281. /* Retimer is connected to I2C1_CH7_CH5 */
  282. select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
  283. reg = I2C_MUX_CH5;
  284. #if CONFIG_IS_ENABLED(DM_I2C)
  285. struct udevice *dev;
  286. int ret;
  287. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
  288. 1, &dev);
  289. if (ret) {
  290. printf("%s: Cannot find udev for a bus %d\n", __func__,
  291. bus_num);
  292. return;
  293. }
  294. dm_i2c_write(dev, 0, &reg, 1);
  295. /* Access to Control/Shared register */
  296. ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
  297. 1, &dev);
  298. if (ret) {
  299. printf("%s: Cannot find udev for a bus %d\n", __func__,
  300. bus_num);
  301. return;
  302. }
  303. reg = 0x0;
  304. dm_i2c_write(dev, 0xff, &reg, 1);
  305. /* Read device revision and ID */
  306. dm_i2c_read(dev, 1, &reg, 1);
  307. debug("Retimer version id = 0x%x\n", reg);
  308. /* Enable Broadcast. All writes target all channel register sets */
  309. reg = 0x0c;
  310. dm_i2c_write(dev, 0xff, &reg, 1);
  311. /* Reset Channel Registers */
  312. dm_i2c_read(dev, 0, &reg, 1);
  313. reg |= 0x4;
  314. dm_i2c_write(dev, 0, &reg, 1);
  315. /* Enable override divider select and Enable Override Output Mux */
  316. dm_i2c_read(dev, 9, &reg, 1);
  317. reg |= 0x24;
  318. dm_i2c_write(dev, 9, &reg, 1);
  319. /* Select VCO Divider to full rate (000) */
  320. dm_i2c_read(dev, 0x18, &reg, 1);
  321. reg &= 0x8f;
  322. dm_i2c_write(dev, 0x18, &reg, 1);
  323. /* Selects active PFD MUX Input as Re-timed Data (001) */
  324. dm_i2c_read(dev, 0x1e, &reg, 1);
  325. reg &= 0x3f;
  326. reg |= 0x20;
  327. dm_i2c_write(dev, 0x1e, &reg, 1);
  328. /* Set data rate as 10.3125 Gbps */
  329. reg = 0x0;
  330. dm_i2c_write(dev, 0x60, &reg, 1);
  331. reg = 0xb2;
  332. dm_i2c_write(dev, 0x61, &reg, 1);
  333. reg = 0x90;
  334. dm_i2c_write(dev, 0x62, &reg, 1);
  335. reg = 0xb3;
  336. dm_i2c_write(dev, 0x63, &reg, 1);
  337. reg = 0xcd;
  338. dm_i2c_write(dev, 0x64, &reg, 1);
  339. #else
  340. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  341. /* Access to Control/Shared register */
  342. reg = 0x0;
  343. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  344. /* Read device revision and ID */
  345. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  346. debug("Retimer version id = 0x%x\n", reg);
  347. /* Enable Broadcast. All writes target all channel register sets */
  348. reg = 0x0c;
  349. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  350. /* Reset Channel Registers */
  351. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  352. reg |= 0x4;
  353. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  354. /* Enable override divider select and Enable Override Output Mux */
  355. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  356. reg |= 0x24;
  357. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  358. /* Select VCO Divider to full rate (000) */
  359. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  360. reg &= 0x8f;
  361. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  362. /* Selects active PFD MUX Input as Re-timed Data (001) */
  363. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  364. reg &= 0x3f;
  365. reg |= 0x20;
  366. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  367. /* Set data rate as 10.3125 Gbps */
  368. reg = 0x0;
  369. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  370. reg = 0xb2;
  371. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  372. reg = 0x90;
  373. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  374. reg = 0xb3;
  375. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  376. reg = 0xcd;
  377. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  378. #endif
  379. /* Return the default channel */
  380. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
  381. }
  382. int board_early_init_f(void)
  383. {
  384. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  385. #ifdef CONFIG_HAS_FSL_XHCI_USB
  386. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  387. u32 usb_pwrfault;
  388. #endif
  389. #ifdef CONFIG_LPUART
  390. u8 uart;
  391. #endif
  392. /*
  393. * Enable secure system counter for timer
  394. */
  395. out_le32(cntcr, 0x1);
  396. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  397. i2c_early_init_f();
  398. #endif
  399. fsl_lsch2_early_init_f();
  400. #ifdef CONFIG_HAS_FSL_XHCI_USB
  401. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  402. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  403. usb_pwrfault =
  404. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
  405. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
  406. (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
  407. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  408. #endif
  409. #ifdef CONFIG_LPUART
  410. /* We use lpuart0 as system console */
  411. uart = QIXIS_READ(brdcfg[14]);
  412. uart &= ~CFG_UART_MUX_MASK;
  413. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  414. QIXIS_WRITE(brdcfg[14], uart);
  415. #endif
  416. return 0;
  417. }
  418. #ifdef CONFIG_FSL_DEEP_SLEEP
  419. /* determine if it is a warm boot */
  420. bool is_warm_boot(void)
  421. {
  422. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  423. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  424. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  425. return 1;
  426. return 0;
  427. }
  428. #endif
  429. int config_board_mux(int ctrl_type)
  430. {
  431. u8 reg14;
  432. reg14 = QIXIS_READ(brdcfg[14]);
  433. switch (ctrl_type) {
  434. case MUX_TYPE_GPIO:
  435. reg14 = (reg14 & (~0x30)) | 0x20;
  436. break;
  437. default:
  438. puts("Unsupported mux interface type\n");
  439. return -1;
  440. }
  441. QIXIS_WRITE(brdcfg[14], reg14);
  442. return 0;
  443. }
  444. int config_serdes_mux(void)
  445. {
  446. return 0;
  447. }
  448. #ifdef CONFIG_MISC_INIT_R
  449. int misc_init_r(void)
  450. {
  451. if (hwconfig("gpio"))
  452. config_board_mux(MUX_TYPE_GPIO);
  453. return 0;
  454. }
  455. #endif
  456. int board_init(void)
  457. {
  458. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  459. erratum_a010315();
  460. #endif
  461. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  462. board_retimer_init();
  463. #ifdef CONFIG_SYS_FSL_SERDES
  464. config_serdes_mux();
  465. #endif
  466. #ifdef CONFIG_FSL_LS_PPA
  467. ppa_init();
  468. #endif
  469. return 0;
  470. }
  471. #ifdef CONFIG_OF_BOARD_SETUP
  472. int ft_board_setup(void *blob, struct bd_info *bd)
  473. {
  474. u64 base[CONFIG_NR_DRAM_BANKS];
  475. u64 size[CONFIG_NR_DRAM_BANKS];
  476. u8 reg;
  477. /* fixup DT for the two DDR banks */
  478. base[0] = gd->bd->bi_dram[0].start;
  479. size[0] = gd->bd->bi_dram[0].size;
  480. base[1] = gd->bd->bi_dram[1].start;
  481. size[1] = gd->bd->bi_dram[1].size;
  482. fdt_fixup_memory_banks(blob, base, size, 2);
  483. ft_cpu_setup(blob, bd);
  484. #ifdef CONFIG_SYS_DPAA_FMAN
  485. #ifndef CONFIG_DM_ETH
  486. fdt_fixup_fman_ethernet(blob);
  487. #endif
  488. fdt_fixup_board_enet(blob);
  489. #endif
  490. fdt_fixup_icid(blob);
  491. reg = QIXIS_READ(brdcfg[0]);
  492. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  493. /* Disable IFC if QSPI is enabled */
  494. if (reg == 0xF)
  495. do_fixup_by_compat(blob, "fsl,ifc",
  496. "status", "disabled", 8 + 1, 1);
  497. return 0;
  498. }
  499. #endif
  500. u8 flash_read8(void *addr)
  501. {
  502. return __raw_readb(addr + 1);
  503. }
  504. void flash_write16(u16 val, void *addr)
  505. {
  506. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  507. __raw_writew(shftval, addr);
  508. }
  509. u16 flash_read16(void *addr)
  510. {
  511. u16 val = __raw_readw(addr);
  512. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  513. }
  514. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  515. void *env_sf_get_env_addr(void)
  516. {
  517. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  518. }
  519. #endif