m547x_8x.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef mcf547x_8x_h
  9. #define mcf547x_8x_h
  10. /*********************************************************************
  11. * XLB Arbiter (XLB)
  12. *********************************************************************/
  13. /* Bit definitions and macros for XARB_CFG */
  14. #define XARB_CFG_AT (0x00000002)
  15. #define XARB_CFG_DT (0x00000004)
  16. #define XARB_CFG_BA (0x00000008)
  17. #define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
  18. #define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
  19. #define XARB_CFG_PLDIS (0x80000000)
  20. /* Bit definitions and macros for XARB_SR */
  21. #define XARB_SR_AT (0x00000001)
  22. #define XARB_SR_DT (0x00000002)
  23. #define XARB_SR_BA (0x00000004)
  24. #define XARB_SR_TTM (0x00000008)
  25. #define XARB_SR_ECW (0x00000010)
  26. #define XARB_SR_TTR (0x00000020)
  27. #define XARB_SR_TTA (0x00000040)
  28. #define XARB_SR_MM (0x00000080)
  29. #define XARB_SR_SEA (0x00000100)
  30. /* Bit definitions and macros for XARB_IMR */
  31. #define XARB_IMR_ATE (0x00000001)
  32. #define XARB_IMR_DTE (0x00000002)
  33. #define XARB_IMR_BAE (0x00000004)
  34. #define XARB_IMR_TTME (0x00000008)
  35. #define XARB_IMR_ECWE (0x00000010)
  36. #define XARB_IMR_TTRE (0x00000020)
  37. #define XARB_IMR_TTAE (0x00000040)
  38. #define XARB_IMR_MME (0x00000080)
  39. #define XARB_IMR_SEAE (0x00000100)
  40. /* Bit definitions and macros for XARB_SIGCAP */
  41. #define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
  42. #define XARB_SIGCAP_TBST (0x00000020)
  43. #define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
  44. /* Bit definitions and macros for XARB_PRIEN */
  45. #define XARB_PRIEN_M0 (0x00000001)
  46. #define XARB_PRIEN_M2 (0x00000004)
  47. #define XARB_PRIEN_M3 (0x00000008)
  48. /* Bit definitions and macros for XARB_PRI */
  49. #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
  50. #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
  51. #define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
  52. /*********************************************************************
  53. * General Purpose I/O (GPIO)
  54. *********************************************************************/
  55. /* Bit definitions and macros for GPIO_PAR_FBCTL */
  56. #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
  57. #define GPIO_PAR_FBCTL_TA (0x0004)
  58. #define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
  59. #define GPIO_PAR_FBCTL_OE (0x0040)
  60. #define GPIO_PAR_FBCTL_BWE0 (0x0100)
  61. #define GPIO_PAR_FBCTL_BWE1 (0x0400)
  62. #define GPIO_PAR_FBCTL_BWE2 (0x1000)
  63. #define GPIO_PAR_FBCTL_BWE3 (0x4000)
  64. #define GPIO_PAR_FBCTL_TS_GPIO (0)
  65. #define GPIO_PAR_FBCTL_TS_TBST (2)
  66. #define GPIO_PAR_FBCTL_TS_TS (3)
  67. #define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
  68. #define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
  69. #define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
  70. /* Bit definitions and macros for GPIO_PAR_FBCS */
  71. #define GPIO_PAR_FBCS_CS1 (0x02)
  72. #define GPIO_PAR_FBCS_CS2 (0x04)
  73. #define GPIO_PAR_FBCS_CS3 (0x08)
  74. #define GPIO_PAR_FBCS_CS4 (0x10)
  75. #define GPIO_PAR_FBCS_CS5 (0x20)
  76. /* Bit definitions and macros for GPIO_PAR_DMA */
  77. #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
  78. #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
  79. #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
  80. #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
  81. #define GPIO_PAR_DMA_DACKx_GPIO (0)
  82. #define GPIO_PAR_DMA_DACKx_TOUT (2)
  83. #define GPIO_PAR_DMA_DACKx_DACK (3)
  84. #define GPIO_PAR_DMA_DREQx_GPIO (0)
  85. #define GPIO_PAR_DMA_DREQx_TIN (2)
  86. #define GPIO_PAR_DMA_DREQx_DREQ (3)
  87. /* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
  88. #define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
  89. #define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
  90. #define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
  91. #define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
  92. #define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
  93. #define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
  94. #define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
  95. #define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
  96. #define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
  97. #define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
  98. #define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
  99. #define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
  100. #define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
  101. #define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
  102. #define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
  103. #define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
  104. #define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
  105. #define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
  106. /* Bit definitions and macros for GPIO_PAR_PCIBG */
  107. #define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
  108. #define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
  109. #define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
  110. #define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
  111. #define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
  112. /* Bit definitions and macros for GPIO_PAR_PCIBR */
  113. #define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
  114. #define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
  115. #define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
  116. #define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
  117. #define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
  118. /* Bit definitions and macros for GPIO_PAR_PSC3 */
  119. #define GPIO_PAR_PSC3_TXD3 (0x04)
  120. #define GPIO_PAR_PSC3_RXD3 (0x08)
  121. #define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
  122. #define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
  123. #define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
  124. #define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
  125. #define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
  126. #define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
  127. #define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
  128. #define GPIO_PAR_PSC3_RTS3_RTS (0x30)
  129. #define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
  130. /* Bit definitions and macros for GPIO_PAR_PSC2 */
  131. #define GPIO_PAR_PSC2_TXD2 (0x04)
  132. #define GPIO_PAR_PSC2_RXD2 (0x08)
  133. #define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
  134. #define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
  135. #define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
  136. #define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
  137. #define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
  138. #define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
  139. #define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
  140. #define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
  141. #define GPIO_PAR_PSC2_RTS2_RTS (0x30)
  142. /* Bit definitions and macros for GPIO_PAR_PSC1 */
  143. #define GPIO_PAR_PSC1_TXD1 (0x04)
  144. #define GPIO_PAR_PSC1_RXD1 (0x08)
  145. #define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
  146. #define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
  147. #define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
  148. #define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
  149. #define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
  150. #define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
  151. #define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
  152. #define GPIO_PAR_PSC1_RTS1_RTS (0x30)
  153. /* Bit definitions and macros for GPIO_PAR_PSC0 */
  154. #define GPIO_PAR_PSC0_TXD0 (0x04)
  155. #define GPIO_PAR_PSC0_RXD0 (0x08)
  156. #define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
  157. #define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
  158. #define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
  159. #define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
  160. #define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
  161. #define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
  162. #define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
  163. #define GPIO_PAR_PSC0_RTS0_RTS (0x30)
  164. /* Bit definitions and macros for GPIO_PAR_DSPI */
  165. #define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
  166. #define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
  167. #define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
  168. #define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
  169. #define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
  170. #define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
  171. #define GPIO_PAR_DSPI_CS5 (0x1000)
  172. #define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
  173. #define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
  174. #define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
  175. #define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
  176. #define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
  177. #define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
  178. #define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
  179. #define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
  180. #define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
  181. #define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
  182. #define GPIO_PAR_DSPI_CS0_RTS (0x0080)
  183. #define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
  184. #define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
  185. #define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
  186. #define GPIO_PAR_DSPI_SCK_CTS (0x0020)
  187. #define GPIO_PAR_DSPI_SCK_SCK (0x0030)
  188. #define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
  189. #define GPIO_PAR_DSPI_SIN_RXD (0x0008)
  190. #define GPIO_PAR_DSPI_SIN_SIN (0x000C)
  191. #define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
  192. #define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
  193. #define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
  194. /* Bit definitions and macros for GPIO_PAR_TIMER */
  195. #define GPIO_PAR_TIMER_TOUT2 (0x01)
  196. #define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
  197. #define GPIO_PAR_TIMER_TOUT3 (0x08)
  198. #define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
  199. #define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
  200. #define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
  201. #define GPIO_PAR_TIMER_TIN3_TIN (0x30)
  202. #define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
  203. #define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
  204. #define GPIO_PAR_TIMER_TIN2_TIN (0x06)
  205. /*********************************************************************
  206. * Slice Timer (SLT)
  207. *********************************************************************/
  208. #define SLT_CR_RUN (0x04000000)
  209. #define SLT_CR_IEN (0x02000000)
  210. #define SLT_CR_TEN (0x01000000)
  211. #define SLT_SR_BE (0x02000000)
  212. #define SLT_SR_ST (0x01000000)
  213. /*********************************************************************
  214. * Interrupt Controller (INTC)
  215. *********************************************************************/
  216. #define INT0_LO_RSVD0 (0)
  217. #define INT0_LO_EPORT1 (1)
  218. #define INT0_LO_EPORT2 (2)
  219. #define INT0_LO_EPORT3 (3)
  220. #define INT0_LO_EPORT4 (4)
  221. #define INT0_LO_EPORT5 (5)
  222. #define INT0_LO_EPORT6 (6)
  223. #define INT0_LO_EPORT7 (7)
  224. #define INT0_LO_EP0ISR (15)
  225. #define INT0_LO_EP1ISR (16)
  226. #define INT0_LO_EP2ISR (17)
  227. #define INT0_LO_EP3ISR (18)
  228. #define INT0_LO_EP4ISR (19)
  229. #define INT0_LO_EP5ISR (20)
  230. #define INT0_LO_EP6ISR (21)
  231. #define INT0_LO_USBISR (22)
  232. #define INT0_LO_USBAISR (23)
  233. #define INT0_LO_USB (24)
  234. #define INT1_LO_DSPI_RFOF_TFUF (25)
  235. #define INT1_LO_DSPI_RFOF (26)
  236. #define INT1_LO_DSPI_RFDF (27)
  237. #define INT1_LO_DSPI_TFUF (28)
  238. #define INT1_LO_DSPI_TCF (29)
  239. #define INT1_LO_DSPI_TFFF (30)
  240. #define INT1_LO_DSPI_EOQF (31)
  241. #define INT0_HI_UART3 (32)
  242. #define INT0_HI_UART2 (33)
  243. #define INT0_HI_UART1 (34)
  244. #define INT0_HI_UART0 (35)
  245. #define INT0_HI_COMMTIM_TC (36)
  246. #define INT0_HI_SEC (37)
  247. #define INT0_HI_FEC1 (38)
  248. #define INT0_HI_FEC0 (39)
  249. #define INT0_HI_I2C (40)
  250. #define INT0_HI_PCIARB (41)
  251. #define INT0_HI_CBPCI (42)
  252. #define INT0_HI_XLBPCI (43)
  253. #define INT0_HI_XLBARB (47)
  254. #define INT0_HI_DMA (48)
  255. #define INT0_HI_CAN0_ERROR (49)
  256. #define INT0_HI_CAN0_BUSOFF (50)
  257. #define INT0_HI_CAN0_MBOR (51)
  258. #define INT0_HI_SLT1 (53)
  259. #define INT0_HI_SLT0 (54)
  260. #define INT0_HI_CAN1_ERROR (55)
  261. #define INT0_HI_CAN1_BUSOFF (56)
  262. #define INT0_HI_CAN1_MBOR (57)
  263. #define INT0_HI_GPT3 (59)
  264. #define INT0_HI_GPT2 (60)
  265. #define INT0_HI_GPT1 (61)
  266. #define INT0_HI_GPT0 (62)
  267. /*********************************************************************
  268. * General Purpose Timers (GPTMR)
  269. *********************************************************************/
  270. /* Enable and Mode Select */
  271. #define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
  272. #define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
  273. #define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
  274. #define GPT_CTRL_CE 0x10 /* Counter Enable */
  275. #define GPT_CTRL_STPCNT 0x04 /* Stop continous */
  276. #define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
  277. #define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
  278. #define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
  279. #define GPT_TMS_ICT 0x01 /* Input Capture Enable */
  280. #define GPT_TMS_OCT 0x02 /* Output Capture Enable */
  281. #define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
  282. #define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
  283. #define GPT_PWM_WIDTH(x) (x & 0xffff)
  284. /* Status */
  285. #define GPT_STA_CAPTURE(x) (x & 0xffff)
  286. #define GPT_OVFPIN_OVF(x) (x & 0x70)
  287. #define GPT_OVFPIN_PIN 0x01
  288. #define GPT_INT_TEXP 0x08
  289. #define GPT_INT_PWMP 0x04
  290. #define GPT_INT_COMP 0x02
  291. #define GPT_INT_CAPT 0x01
  292. /*********************************************************************
  293. * PCI
  294. *********************************************************************/
  295. /* Bit definitions and macros for SCR */
  296. #define PCI_SCR_PE (0x80000000) /* Parity Error detected */
  297. #define PCI_SCR_SE (0x40000000) /* System error signalled */
  298. #define PCI_SCR_MA (0x20000000) /* Master aboart received */
  299. #define PCI_SCR_TR (0x10000000) /* Target abort received */
  300. #define PCI_SCR_TS (0x08000000) /* Target abort signalled */
  301. #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
  302. #define PCI_SCR_DP (0x01000000) /* Master data parity err */
  303. #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
  304. #define PCI_SCR_R (0x00400000) /* Reserved */
  305. #define PCI_SCR_66M (0x00200000) /* 66Mhz */
  306. #define PCI_SCR_C (0x00100000) /* Capabilities list */
  307. #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
  308. #define PCI_SCR_S (0x00000100) /* SERR enable */
  309. #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
  310. #define PCI_SCR_PER (0x00000040) /* Parity error response */
  311. #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
  312. #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
  313. #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
  314. #define PCI_SCR_B (0x00000004) /* Bus master enable */
  315. #define PCI_SCR_M (0x00000002) /* Memory access control */
  316. #define PCI_SCR_IO (0x00000001) /* I/O access control */
  317. #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
  318. #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
  319. #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
  320. #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
  321. #define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
  322. #define PCI_BAR_BAR1(x) (x & 0xC0000000)
  323. #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
  324. #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
  325. #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
  326. #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
  327. #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
  328. #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
  329. #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
  330. #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
  331. #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
  332. #define PCI_GSCR_SE (0x10000000) /* SERR detected */
  333. #define PCI_GSCR_ER (0x08000000) /* Error response detected */
  334. #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
  335. #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
  336. #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
  337. #define PCI_GSCR_PR (0x00000001) /* PCI reset */
  338. #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
  339. #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
  340. #define PCI_TCR1_P (0x00010000) /* Prefetch reads */
  341. #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
  342. #define PCI_TCR1_B5E (0x00002000) /* */
  343. #define PCI_TCR1_B4E (0x00001000) /* */
  344. #define PCI_TCR1_B3E (0x00000800) /* */
  345. #define PCI_TCR1_B2E (0x00000400) /* */
  346. #define PCI_TCR1_B1E (0x00000200) /* */
  347. #define PCI_TCR1_B0E (0x00000100) /* */
  348. #define PCI_TCR1_CR (0x00000001) /* */
  349. #define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
  350. #define PCI_TBATR_BAT1(x) (x & 0xC0000000)
  351. #define PCI_TBATR_EN (0x00000001) /* Enable */
  352. #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
  353. #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
  354. #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
  355. #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
  356. #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
  357. #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
  358. #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
  359. #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
  360. #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
  361. #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
  362. #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
  363. #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
  364. #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
  365. #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
  366. #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
  367. #define PCI_ICR_REE (0x04000000) /* Retry error enable */
  368. #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
  369. #define PCI_ICR_TAE (0x01000000) /* Target abort enable */
  370. #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
  371. #define PCIARB_ACR_DS (0x80000000)
  372. #define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
  373. #define PCIARB_ARC_INTMINTEN (0x00010000)
  374. #define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
  375. #define PCIARB_ARC_INTMPRI (0x00000001)
  376. #endif /* mcf547x_8x_h */