immap_547x_8x.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * MCF547x_8x Internal Memory Map
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef __IMMAP_547x_8x__
  9. #define __IMMAP_547x_8x__
  10. #define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
  11. #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
  12. #define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
  13. #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
  14. #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
  15. #define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
  16. #define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
  17. #define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
  18. #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
  19. #define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
  20. #define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
  21. #define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
  22. #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
  23. #define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
  24. #define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
  25. #define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
  26. #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
  27. #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
  28. #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
  29. #define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
  30. #define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
  31. #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
  32. #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
  33. #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
  34. #define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
  35. #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
  36. #define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
  37. #define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
  38. #define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
  39. #define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
  40. #include <asm/coldfire/dspi.h>
  41. #include <asm/coldfire/eport.h>
  42. #include <asm/coldfire/flexbus.h>
  43. #include <asm/coldfire/flexcan.h>
  44. #include <asm/coldfire/intctrl.h>
  45. typedef struct siu {
  46. u32 mbar; /* 0x00 */
  47. u32 drv; /* 0x04 */
  48. u32 rsvd1[2]; /* 0x08 - 0x1F */
  49. u32 sbcr; /* 0x10 */
  50. u32 rsvd2[3]; /* 0x14 - 0x1F */
  51. u32 cs0cfg; /* 0x20 */
  52. u32 cs1cfg; /* 0x24 */
  53. u32 cs2cfg; /* 0x28 */
  54. u32 cs3cfg; /* 0x2C */
  55. u32 rsvd3[2]; /* 0x30 - 0x37 */
  56. u32 secsacr; /* 0x38 */
  57. u32 rsvd4[2]; /* 0x3C - 0x43 */
  58. u32 rsr; /* 0x44 */
  59. u32 rsvd5[2]; /* 0x48 - 0x4F */
  60. u32 jtagid; /* 0x50 */
  61. } siu_t;
  62. typedef struct sdram {
  63. u32 mode; /* 0x00 */
  64. u32 ctrl; /* 0x04 */
  65. u32 cfg1; /* 0x08 */
  66. u32 cfg2; /* 0x0c */
  67. } sdram_t;
  68. typedef struct xlb_arb {
  69. u32 cfg; /* 0x240 */
  70. u32 ver; /* 0x244 */
  71. u32 sr; /* 0x248 */
  72. u32 imr; /* 0x24c */
  73. u32 adrcap; /* 0x250 */
  74. u32 sigcap; /* 0x254 */
  75. u32 adrto; /* 0x258 */
  76. u32 datto; /* 0x25c */
  77. u32 busto; /* 0x260 */
  78. u32 prien; /* 0x264 */
  79. u32 pri; /* 0x268 */
  80. } xlbarb_t;
  81. typedef struct gptmr {
  82. u8 ocpw;
  83. u8 octict;
  84. u8 ctrl;
  85. u8 mode;
  86. u16 pre; /* Prescale */
  87. u16 cnt;
  88. u16 pwmwidth;
  89. u8 pwmop; /* Output Polarity */
  90. u8 pwmld; /* Immediate Update */
  91. u16 cap; /* Capture internal counter */
  92. u8 ovfpin; /* Ovf and Pin */
  93. u8 intr; /* Interrupts */
  94. } gptmr_t;
  95. typedef struct canex_ctrl {
  96. can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
  97. } canex_t;
  98. typedef struct slt {
  99. u32 tcnt; /* 0x00 */
  100. u32 cr; /* 0x04 */
  101. u32 cnt; /* 0x08 */
  102. u32 sr; /* 0x0C */
  103. } slt_t;
  104. typedef struct gpio {
  105. /* Port Output Data Registers */
  106. u8 podr_fbctl; /*0x00 */
  107. u8 podr_fbcs; /*0x01 */
  108. u8 podr_dma; /*0x02 */
  109. u8 rsvd1; /*0x03 */
  110. u8 podr_fec0h; /*0x04 */
  111. u8 podr_fec0l; /*0x05 */
  112. u8 podr_fec1h; /*0x06 */
  113. u8 podr_fec1l; /*0x07 */
  114. u8 podr_feci2c; /*0x08 */
  115. u8 podr_pcibg; /*0x09 */
  116. u8 podr_pcibr; /*0x0A */
  117. u8 rsvd2; /*0x0B */
  118. u8 podr_psc3psc2; /*0x0C */
  119. u8 podr_psc1psc0; /*0x0D */
  120. u8 podr_dspi; /*0x0E */
  121. u8 rsvd3; /*0x0F */
  122. /* Port Data Direction Registers */
  123. u8 pddr_fbctl; /*0x10 */
  124. u8 pddr_fbcs; /*0x11 */
  125. u8 pddr_dma; /*0x12 */
  126. u8 rsvd4; /*0x13 */
  127. u8 pddr_fec0h; /*0x14 */
  128. u8 pddr_fec0l; /*0x15 */
  129. u8 pddr_fec1h; /*0x16 */
  130. u8 pddr_fec1l; /*0x17 */
  131. u8 pddr_feci2c; /*0x18 */
  132. u8 pddr_pcibg; /*0x19 */
  133. u8 pddr_pcibr; /*0x1A */
  134. u8 rsvd5; /*0x1B */
  135. u8 pddr_psc3psc2; /*0x1C */
  136. u8 pddr_psc1psc0; /*0x1D */
  137. u8 pddr_dspi; /*0x1E */
  138. u8 rsvd6; /*0x1F */
  139. /* Port Pin Data/Set Data Registers */
  140. u8 ppdsdr_fbctl; /*0x20 */
  141. u8 ppdsdr_fbcs; /*0x21 */
  142. u8 ppdsdr_dma; /*0x22 */
  143. u8 rsvd7; /*0x23 */
  144. u8 ppdsdr_fec0h; /*0x24 */
  145. u8 ppdsdr_fec0l; /*0x25 */
  146. u8 ppdsdr_fec1h; /*0x26 */
  147. u8 ppdsdr_fec1l; /*0x27 */
  148. u8 ppdsdr_feci2c; /*0x28 */
  149. u8 ppdsdr_pcibg; /*0x29 */
  150. u8 ppdsdr_pcibr; /*0x2A */
  151. u8 rsvd8; /*0x2B */
  152. u8 ppdsdr_psc3psc2; /*0x2C */
  153. u8 ppdsdr_psc1psc0; /*0x2D */
  154. u8 ppdsdr_dspi; /*0x2E */
  155. u8 rsvd9; /*0x2F */
  156. /* Port Clear Output Data Registers */
  157. u8 pclrr_fbctl; /*0x30 */
  158. u8 pclrr_fbcs; /*0x31 */
  159. u8 pclrr_dma; /*0x32 */
  160. u8 rsvd10; /*0x33 */
  161. u8 pclrr_fec0h; /*0x34 */
  162. u8 pclrr_fec0l; /*0x35 */
  163. u8 pclrr_fec1h; /*0x36 */
  164. u8 pclrr_fec1l; /*0x37 */
  165. u8 pclrr_feci2c; /*0x38 */
  166. u8 pclrr_pcibg; /*0x39 */
  167. u8 pclrr_pcibr; /*0x3A */
  168. u8 rsvd11; /*0x3B */
  169. u8 pclrr_psc3psc2; /*0x3C */
  170. u8 pclrr_psc1psc0; /*0x3D */
  171. u8 pclrr_dspi; /*0x3E */
  172. u8 rsvd12; /*0x3F */
  173. /* Pin Assignment Registers */
  174. u16 par_fbctl; /*0x40 */
  175. u8 par_fbcs; /*0x42 */
  176. u8 par_dma; /*0x43 */
  177. u16 par_feci2cirq; /*0x44 */
  178. u16 rsvd13; /*0x46 */
  179. u16 par_pcibg; /*0x48 */
  180. u16 par_pcibr; /*0x4A */
  181. u8 par_psc3; /*0x4C */
  182. u8 par_psc2; /*0x4D */
  183. u8 par_psc1; /*0x4E */
  184. u8 par_psc0; /*0x4F */
  185. u16 par_dspi; /*0x50 */
  186. u8 par_timer; /*0x52 */
  187. u8 rsvd14; /*0x53 */
  188. } gpio_t;
  189. typedef struct pci {
  190. u32 idr; /* 0x00 Device Id / Vendor Id */
  191. u32 scr; /* 0x04 Status / command */
  192. u32 ccrir; /* 0x08 Class Code / Revision Id */
  193. u32 cr1; /* 0x0c Configuration 1 */
  194. u32 bar0; /* 0x10 Base address register 0 */
  195. u32 bar1; /* 0x14 Base address register 1 */
  196. u32 bar2; /* 0x18 NA */
  197. u32 bar3; /* 0x1c NA */
  198. u32 bar4; /* 0x20 NA */
  199. u32 bar5; /* 0x24 NA */
  200. u32 ccpr; /* 0x28 Cardbus CIS Pointer */
  201. u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
  202. u32 erbar; /* 0x30 Expansion ROM Base Address */
  203. u32 cpr; /* 0x34 Capabilities Pointer */
  204. u32 rsvd1; /* 0x38 */
  205. u32 cr2; /* 0x3c Configuration 2 */
  206. u32 rsvd2[8]; /* 0x40 - 0x5f */
  207. /* General control / status registers */
  208. u32 gscr; /* 0x60 Global Status / Control */
  209. u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
  210. u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
  211. u32 tcr1; /* 0x6c Target Control 1 Register */
  212. u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
  213. u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
  214. u32 iw2btar; /* 0x78 NA */
  215. u32 rsvd3; /* 0x7c */
  216. u32 iwcr; /* 0x80 Initiator Window Configuration */
  217. u32 icr; /* 0x84 Initiator Control */
  218. u32 isr; /* 0x88 Initiator Status */
  219. u32 tcr2; /* 0x8c NA */
  220. u32 tbatr0; /* 0x90 NA */
  221. u32 tbatr1; /* 0x94 NA */
  222. u32 tbatr2; /* 0x98 NA */
  223. u32 tbatr3; /* 0x9c NA */
  224. u32 tbatr4; /* 0xa0 NA */
  225. u32 tbatr5; /* 0xa4 NA */
  226. u32 intr; /* 0xa8 NA */
  227. u32 rsvd4[19]; /* 0xac - 0xf7 */
  228. u32 car; /* 0xf8 Configuration Address */
  229. } pci_t;
  230. typedef struct pci_arbiter {
  231. /* Pci Arbiter Registers */
  232. union {
  233. u32 acr; /* Arbiter Control */
  234. u32 asr; /* Arbiter Status */
  235. };
  236. } pciarb_t;
  237. #endif /* __IMMAP_547x_8x__ */