pci.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. /*
  7. * PCI Configuration space access support
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <asm/io.h>
  12. #include <asm/immap.h>
  13. #include <linux/delay.h>
  14. #if defined(CONFIG_PCI)
  15. /* System RAM mapped over PCI */
  16. #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
  17. #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  18. #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  19. #define cfg_read(val, addr, type, op) *val = op((type)(addr));
  20. #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
  21. #define PCI_OP(rw, size, type, op, mask) \
  22. int pci_##rw##_cfg_##size(struct pci_controller *hose, \
  23. pci_dev_t dev, int offset, type val) \
  24. { \
  25. u32 addr = 0; \
  26. u16 cfg_type = 0; \
  27. addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
  28. out_be32(hose->cfg_addr, addr); \
  29. cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
  30. __asm__ __volatile__("nop"); \
  31. __asm__ __volatile__("nop"); \
  32. out_be32(hose->cfg_addr, addr & 0x7fffffff); \
  33. return 0; \
  34. }
  35. PCI_OP(read, byte, u8 *, in_8, 3)
  36. PCI_OP(read, word, u16 *, in_le16, 2)
  37. PCI_OP(write, byte, u8, out_8, 3)
  38. PCI_OP(write, word, u16, out_le16, 2)
  39. PCI_OP(write, dword, u32, out_le32, 0)
  40. int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
  41. int offset, u32 * val)
  42. {
  43. u32 addr;
  44. u32 tmpv;
  45. u32 mask = 2; /* word access */
  46. /* Read lower 16 bits */
  47. addr = ((offset & 0xfc) | (dev) | 0x80000000);
  48. out_be32(hose->cfg_addr, addr);
  49. *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
  50. __asm__ __volatile__("nop");
  51. out_be32(hose->cfg_addr, addr & 0x7fffffff);
  52. /* Read upper 16 bits */
  53. offset += 2;
  54. addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
  55. out_be32(hose->cfg_addr, addr);
  56. tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
  57. __asm__ __volatile__("nop");
  58. out_be32(hose->cfg_addr, addr & 0x7fffffff);
  59. /* combine results into dword value */
  60. *val = (tmpv << 16) | *val;
  61. return 0;
  62. }
  63. void pci_mcf547x_8x_init(struct pci_controller *hose)
  64. {
  65. pci_t *pci = (pci_t *) MMAP_PCI;
  66. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  67. /* Port configuration */
  68. out_be16(&gpio->par_pcibg,
  69. GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
  70. GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
  71. GPIO_PAR_PCIBG_PCIBG4(3));
  72. out_be16(&gpio->par_pcibr,
  73. GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
  74. GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
  75. GPIO_PAR_PCIBR_PCIBR4(3));
  76. /* Assert reset bit */
  77. setbits_be32(&pci->gscr, PCI_GSCR_PR);
  78. out_be32(&pci->tcr1, PCI_TCR1_P);
  79. /* Initiator windows */
  80. out_be32(&pci->iw0btar,
  81. CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
  82. out_be32(&pci->iw1btar,
  83. CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
  84. out_be32(&pci->iw2btar,
  85. CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
  86. out_be32(&pci->iwcr,
  87. PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
  88. PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
  89. out_be32(&pci->icr, 0);
  90. /* Enable bus master and mem access */
  91. out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
  92. /* Cache line size and master latency */
  93. out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
  94. out_be32(&pci->cr2, 0);
  95. #ifdef CONFIG_SYS_PCI_BAR0
  96. out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
  97. out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
  98. #endif
  99. #ifdef CONFIG_SYS_PCI_BAR1
  100. out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
  101. out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
  102. #endif
  103. /* Deassert reset bit */
  104. clrbits_be32(&pci->gscr, PCI_GSCR_PR);
  105. udelay(1000);
  106. /* Enable PCI bus master support */
  107. hose->first_busno = 0;
  108. hose->last_busno = 0xff;
  109. pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
  110. CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
  111. pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
  112. CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
  113. pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
  114. CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
  115. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  116. hose->region_count = 3;
  117. hose->cfg_addr = &(pci->car);
  118. hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
  119. pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
  120. pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
  121. pci_write_cfg_dword);
  122. /* Hose scan */
  123. pci_register_hose(hose);
  124. hose->last_busno = pci_hose_scan(hose);
  125. }
  126. #endif /* CONFIG_PCI */