cpu_init.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <MCD_dma.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <asm/immap.h>
  15. #include <asm/io.h>
  16. #if defined(CONFIG_CMD_NET)
  17. #include <config.h>
  18. #include <net.h>
  19. #include <asm/fec.h>
  20. #include <asm/fsl_mcdmafec.h>
  21. #endif
  22. /*
  23. * Breath some life into the CPU...
  24. *
  25. * Set up the memory map,
  26. * initialize a bunch of registers,
  27. * initialize the UPM's
  28. */
  29. void cpu_init_f(void)
  30. {
  31. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  32. fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  33. xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
  34. out_be32(&xlbarb->adrto, 0x2000);
  35. out_be32(&xlbarb->datto, 0x2500);
  36. out_be32(&xlbarb->busto, 0x3000);
  37. out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
  38. /* Master Priority Enable */
  39. out_be32(&xlbarb->prien, 0xff);
  40. out_be32(&xlbarb->pri, 0);
  41. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  42. out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  43. out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  44. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  45. #endif
  46. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  47. out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  48. out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  49. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  50. #endif
  51. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  52. out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  53. out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  54. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  55. #endif
  56. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  57. out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  58. out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  59. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  60. #endif
  61. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  62. out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  63. out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  64. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  65. #endif
  66. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  67. out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  68. out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  69. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  70. #endif
  71. #ifdef CONFIG_SYS_I2C_FSL
  72. out_be16(&gpio->par_feci2cirq,
  73. GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
  74. #endif
  75. icache_enable();
  76. }
  77. /*
  78. * initialize higher level parts of CPU like timers
  79. */
  80. int cpu_init_r(void)
  81. {
  82. #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
  83. MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
  84. MCD_RELOC_TASKS);
  85. #endif
  86. return (0);
  87. }
  88. void uart_port_conf(int port)
  89. {
  90. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  91. u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
  92. /* Setup Ports: */
  93. switch (port) {
  94. case 0:
  95. out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
  96. break;
  97. case 1:
  98. out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
  99. break;
  100. case 2:
  101. out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
  102. break;
  103. case 3:
  104. out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
  105. break;
  106. }
  107. clrbits_8(pscsicr, 0x07);
  108. }
  109. #if defined(CONFIG_CMD_NET)
  110. int fecpin_setclear(fec_info_t *info, int setclear)
  111. {
  112. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  113. u32 fec0_base;
  114. if (fec_get_base_addr(0, &fec0_base))
  115. return -1;
  116. if (setclear) {
  117. if (info->iobase == fec0_base)
  118. setbits_be16(&gpio->par_feci2cirq, 0xf000);
  119. else
  120. setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
  121. } else {
  122. if (info->iobase == fec0_base)
  123. clrbits_be16(&gpio->par_feci2cirq, 0xf000);
  124. else
  125. clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
  126. }
  127. return 0;
  128. }
  129. #endif