cppi5.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * CPPI5 descriptors interface
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
  6. */
  7. #ifndef __TI_CPPI5_H__
  8. #define __TI_CPPI5_H__
  9. #include <hexdump.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bug.h>
  12. /**
  13. * Descriptor header, present in all types of descriptors
  14. */
  15. struct cppi5_desc_hdr_t {
  16. u32 pkt_info0; /* Packet info word 0 (n/a in Buffer desc) */
  17. u32 pkt_info1; /* Packet info word 1 (n/a in Buffer desc) */
  18. u32 pkt_info2; /* Packet info word 2 Buffer reclamation info */
  19. u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */
  20. } __packed;
  21. /**
  22. * Host-mode packet and buffer descriptor definition
  23. */
  24. struct cppi5_host_desc_t {
  25. struct cppi5_desc_hdr_t hdr;
  26. u64 next_desc; /* w4/5: Linking word */
  27. u64 buf_ptr; /* w6/7: Buffer pointer */
  28. u32 buf_info1; /* w8: Buffer valid data length */
  29. u32 org_buf_len; /* w9: Original buffer length */
  30. u64 org_buf_ptr; /* w10/11: Original buffer pointer */
  31. u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */
  32. /*
  33. * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
  34. * and/or Other Software Data (0-N bytes, optional)
  35. */
  36. } __packed;
  37. #define CPPI5_DESC_MIN_ALIGN (16U)
  38. #define CPPI5_INFO0_HDESC_EPIB_SIZE (16U)
  39. #define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
  40. #define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
  41. #define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
  42. #define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
  43. #define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
  44. #define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
  45. #define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
  46. /*
  47. * Protocol Specific Words location:
  48. * 0 - located in the descriptor,
  49. * 1 = located in the SOP Buffer immediately prior to the data.
  50. */
  51. #define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
  52. #define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U)
  53. #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
  54. #define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
  55. #define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
  56. #define CPPI5_INFO1_DESC_PKTERROR_SHIFT (28U)
  57. #define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
  58. #define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
  59. #define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
  60. #define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
  61. #define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
  62. #define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
  63. #define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
  64. #define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT (27U)
  65. #define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
  66. /* Return Policy: 0 - Entire packet 1 - Each buffer */
  67. #define CPPI5_INFO2_HDESC_RETPOLICY BIT(18)
  68. /*
  69. * Early Return:
  70. * 0 = desc pointers should be returned after all reads have been completed
  71. * 1 = desc pointers should be returned immediately upon fetching
  72. * the descriptor and beginning to transfer data.
  73. */
  74. #define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
  75. /*
  76. * Return Push Policy:
  77. * 0 = Descriptor must be returned to tail of queue
  78. * 1 = Descriptor must be returned to head of queue
  79. */
  80. #define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
  81. #define CPPI5_INFO2_DESC_RETQ_SHIFT (0)
  82. #define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
  83. #define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
  84. #define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
  85. #define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
  86. #define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
  87. #define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0)
  88. #define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
  89. #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0)
  90. #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)
  91. /*
  92. * Host Packet Descriptor Extended Packet Info Block
  93. */
  94. struct cppi5_desc_epib_t {
  95. u32 timestamp; /* w0: application specific timestamp */
  96. u32 sw_info0; /* w1: Software Info 0 */
  97. u32 sw_info1; /* w2: Software Info 1 */
  98. u32 sw_info2; /* w3: Software Info 2 */
  99. };
  100. /**
  101. * Monolithic-mode packet descriptor
  102. */
  103. struct cppi5_monolithic_desc_t {
  104. struct cppi5_desc_hdr_t hdr;
  105. u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */
  106. /*
  107. * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
  108. * and/or Other Software Data (0-N bytes, optional)
  109. */
  110. };
  111. #define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT (18U)
  112. #define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK GENMASK(26, 18)
  113. /*
  114. * Reload Enable:
  115. * 0 = Finish the packet and place the descriptor back on the return queue
  116. * 1 = Vector to the Reload Index and resume processing
  117. */
  118. #define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT (20U)
  119. #define CPPI5_INFO0_TRDESC_RLDCNT_MASK GENMASK(28, 20)
  120. #define CPPI5_INFO0_TRDESC_RLDCNT_MAX (0x1ff)
  121. #define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE CPPI5_INFO0_TRDESC_RLDCNT_MAX
  122. #define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT (14U)
  123. #define CPPI5_INFO0_TRDESC_RLDIDX_MASK GENMASK(19, 14)
  124. #define CPPI5_INFO0_TRDESC_RLDIDX_MAX (0x3f)
  125. #define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT (0)
  126. #define CPPI5_INFO0_TRDESC_LASTIDX_MASK GENMASK(13, 0)
  127. #define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT (24U)
  128. #define CPPI5_INFO1_TRDESC_RECSIZE_MASK GENMASK(26, 24)
  129. #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B (0)
  130. #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B (1U)
  131. #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B (2U)
  132. #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B (3U)
  133. static inline void cppi5_desc_dump(void *desc, u32 size)
  134. {
  135. print_hex_dump(KERN_ERR "dump udmap_desc: ", DUMP_PREFIX_NONE,
  136. 32, 4, desc, size, false);
  137. }
  138. /**
  139. * cppi5_desc_get_type - get descriptor type
  140. * @desc_hdr: packet descriptor/TR header
  141. *
  142. * Returns descriptor type:
  143. * CPPI5_INFO0_DESC_TYPE_VAL_HOST
  144. * CPPI5_INFO0_DESC_TYPE_VAL_MONO
  145. * CPPI5_INFO0_DESC_TYPE_VAL_TR
  146. */
  147. static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
  148. {
  149. WARN_ON(!desc_hdr);
  150. return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
  151. CPPI5_INFO0_HDESC_TYPE_SHIFT;
  152. }
  153. /**
  154. * cppi5_desc_get_errflags - get Error Flags from Desc
  155. * @desc_hdr: packet/TR descriptor header
  156. *
  157. * Returns Error Flags from Packet/TR Descriptor
  158. */
  159. static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
  160. {
  161. WARN_ON(!desc_hdr);
  162. return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
  163. CPPI5_INFO1_DESC_PKTERROR_SHIFT;
  164. }
  165. /**
  166. * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
  167. * @desc_hdr: packet/TR descriptor header
  168. * @pkt_id: Packet ID
  169. * @flow_id: Flow ID
  170. *
  171. * Returns Packet and Flow ids from packet/TR descriptor
  172. */
  173. static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
  174. u32 *pkt_id, u32 *flow_id)
  175. {
  176. WARN_ON(!desc_hdr);
  177. *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
  178. CPPI5_INFO1_DESC_PKTID_SHIFT;
  179. *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
  180. CPPI5_INFO1_DESC_FLOWID_SHIFT;
  181. }
  182. /**
  183. * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
  184. * @desc_hdr: packet/TR descriptor header
  185. * @pkt_id: Packet ID
  186. * @flow_id: Flow ID
  187. */
  188. static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
  189. u32 pkt_id, u32 flow_id)
  190. {
  191. WARN_ON(!desc_hdr);
  192. desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
  193. CPPI5_INFO1_DESC_PKTID_MASK;
  194. desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
  195. CPPI5_INFO1_DESC_FLOWID_MASK;
  196. }
  197. /**
  198. * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
  199. * @desc_hdr: packet/TR descriptor header
  200. * @flags: fags, supported values
  201. * CPPI5_INFO2_HDESC_RETPOLICY
  202. * CPPI5_INFO2_HDESC_EARLYRET
  203. * CPPI5_INFO2_DESC_RETPUSHPOLICY
  204. * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
  205. */
  206. static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
  207. u32 flags, u32 return_ring_id)
  208. {
  209. WARN_ON(!desc_hdr);
  210. desc_hdr->pkt_info2 |= flags;
  211. desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
  212. }
  213. /**
  214. * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
  215. * @desc_hdr: packet/TR descriptor header
  216. * @src_tag_id: Source Tag
  217. * @dst_tag_id: Dest Tag
  218. *
  219. * Returns Packet Src/Dst Tags from packet/TR descriptor
  220. */
  221. static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
  222. u32 *src_tag_id, u32 *dst_tag_id)
  223. {
  224. WARN_ON(!desc_hdr);
  225. if (src_tag_id)
  226. *src_tag_id = (desc_hdr->src_dst_tag &
  227. CPPI5_INFO3_DESC_SRCTAG_MASK) >>
  228. CPPI5_INFO3_DESC_SRCTAG_SHIFT;
  229. if (dst_tag_id)
  230. *dst_tag_id = desc_hdr->src_dst_tag &
  231. CPPI5_INFO3_DESC_DSTTAG_MASK;
  232. }
  233. /**
  234. * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
  235. * @desc_hdr: packet/TR descriptor header
  236. * @src_tag_id: Source Tag
  237. * @dst_tag_id: Dest Tag
  238. *
  239. * Returns Packet Src/Dst Tags from packet/TR descriptor
  240. */
  241. static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
  242. u32 src_tag_id, u32 dst_tag_id)
  243. {
  244. WARN_ON(!desc_hdr);
  245. desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
  246. CPPI5_INFO3_DESC_SRCTAG_MASK;
  247. desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
  248. }
  249. /**
  250. * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
  251. * @epib: is EPIB present
  252. * @psdata_size: PSDATA size
  253. * @sw_data_size: SWDATA size
  254. *
  255. * Returns required Host Packet Descriptor size
  256. * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
  257. */
  258. static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
  259. u32 sw_data_size)
  260. {
  261. u32 desc_size;
  262. if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
  263. return 0;
  264. //TODO_GS: align
  265. desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
  266. sw_data_size;
  267. if (epib)
  268. desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
  269. return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
  270. }
  271. /**
  272. * cppi5_hdesc_init - Init Host Packet Descriptor size
  273. * @desc: Host packet descriptor
  274. * @flags: supported values
  275. * CPPI5_INFO0_HDESC_EPIB_PRESENT
  276. * CPPI5_INFO0_HDESC_PSINFO_LOCATION
  277. * @psdata_size: PSDATA size
  278. *
  279. * Returns required Host Packet Descriptor size
  280. * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
  281. */
  282. static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
  283. u32 psdata_size)
  284. {
  285. WARN_ON(!desc);
  286. WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
  287. WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
  288. CPPI5_INFO0_HDESC_PSINFO_LOCATION));
  289. desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
  290. CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
  291. desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
  292. CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
  293. CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
  294. desc->next_desc = 0;
  295. }
  296. /**
  297. * cppi5_hdesc_update_flags - Replace descriptor flags
  298. * @desc: Host packet descriptor
  299. * @flags: supported values
  300. * CPPI5_INFO0_HDESC_EPIB_PRESENT
  301. * CPPI5_INFO0_HDESC_PSINFO_LOCATION
  302. */
  303. static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
  304. u32 flags)
  305. {
  306. WARN_ON(!desc);
  307. WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
  308. CPPI5_INFO0_HDESC_PSINFO_LOCATION));
  309. desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
  310. CPPI5_INFO0_HDESC_PSINFO_LOCATION);
  311. desc->hdr.pkt_info0 |= flags;
  312. }
  313. /**
  314. * cppi5_hdesc_update_psdata_size - Replace PSdata size
  315. * @desc: Host packet descriptor
  316. * @psdata_size: PSDATA size
  317. */
  318. static inline void cppi5_hdesc_update_psdata_size(
  319. struct cppi5_host_desc_t *desc, u32 psdata_size)
  320. {
  321. WARN_ON(!desc);
  322. WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
  323. desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
  324. desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
  325. CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
  326. CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
  327. }
  328. /**
  329. * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
  330. * @desc: Host packet descriptor
  331. */
  332. static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
  333. {
  334. u32 psdata_size = 0;
  335. WARN_ON(!desc);
  336. if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
  337. psdata_size = (desc->hdr.pkt_info0 &
  338. CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
  339. CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
  340. return (psdata_size << 2);
  341. }
  342. /**
  343. * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
  344. * @desc: Host packet descriptor
  345. *
  346. * Returns Packet Length from Host Packet Descriptor
  347. */
  348. static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
  349. {
  350. WARN_ON(!desc);
  351. return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
  352. }
  353. /**
  354. * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
  355. * @desc: Host packet descriptor
  356. */
  357. static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
  358. u32 pkt_len)
  359. {
  360. WARN_ON(!desc);
  361. desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
  362. }
  363. /**
  364. * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
  365. * @desc: Host packet descriptor
  366. *
  367. * Returns Protocol Specific Flags from Host Packet Descriptor
  368. */
  369. static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
  370. {
  371. WARN_ON(!desc);
  372. return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
  373. CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
  374. }
  375. /**
  376. * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
  377. * @desc: Host packet descriptor
  378. */
  379. static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
  380. u32 ps_flags)
  381. {
  382. WARN_ON(!desc);
  383. desc->hdr.pkt_info1 |= (ps_flags <<
  384. CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
  385. CPPI5_INFO1_HDESC_PSFLGS_MASK;
  386. }
  387. /**
  388. * cppi5_hdesc_get_errflags - get Packet Type from HDesc
  389. * @desc: Host packet descriptor
  390. */
  391. static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
  392. {
  393. WARN_ON(!desc);
  394. return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
  395. CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
  396. }
  397. /**
  398. * cppi5_hdesc_get_errflags - set Packet Type in HDesc
  399. * @desc: Host packet descriptor
  400. * @pkt_type: Packet Type
  401. */
  402. static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
  403. u32 pkt_type)
  404. {
  405. WARN_ON(!desc);
  406. desc->hdr.pkt_info2 |=
  407. (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
  408. CPPI5_INFO2_HDESC_PKTTYPE_MASK;
  409. }
  410. /**
  411. * cppi5_hdesc_attach_buf - attach buffer to HDesc
  412. * @desc: Host packet descriptor
  413. * @buf: Buffer physical address
  414. * @buf_data_len: Buffer length
  415. * @obuf: Original Buffer physical address
  416. * @obuf_len: Original Buffer length
  417. *
  418. * Attaches buffer to Host Packet Descriptor
  419. */
  420. static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
  421. dma_addr_t buf, u32 buf_data_len,
  422. dma_addr_t obuf, u32 obuf_len)
  423. {
  424. WARN_ON(!desc);
  425. WARN_ON(!buf && !obuf);
  426. desc->buf_ptr = buf;
  427. desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
  428. desc->org_buf_ptr = obuf;
  429. desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
  430. }
  431. static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
  432. dma_addr_t *obuf, u32 *obuf_len)
  433. {
  434. WARN_ON(!desc);
  435. WARN_ON(!obuf);
  436. WARN_ON(!obuf_len);
  437. *obuf = desc->org_buf_ptr;
  438. *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
  439. }
  440. static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
  441. {
  442. WARN_ON(!desc);
  443. desc->buf_ptr = desc->org_buf_ptr;
  444. desc->buf_info1 = desc->org_buf_len;
  445. }
  446. /**
  447. * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
  448. * @desc: Host Packet Descriptor
  449. * @buf_desc: Host Buffer Descriptor physical address
  450. *
  451. * add and link Host Buffer Descriptor to HDesc
  452. */
  453. static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
  454. dma_addr_t hbuf_desc)
  455. {
  456. WARN_ON(!desc);
  457. WARN_ON(!hbuf_desc);
  458. desc->next_desc = hbuf_desc;
  459. }
  460. static inline dma_addr_t cppi5_hdesc_get_next_hbdesc(
  461. struct cppi5_host_desc_t *desc)
  462. {
  463. WARN_ON(!desc);
  464. return (dma_addr_t)desc->next_desc;
  465. }
  466. static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
  467. {
  468. WARN_ON(!desc);
  469. desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
  470. desc->next_desc = 0;
  471. }
  472. /**
  473. * cppi5_hdesc_epib_present - check if EPIB present
  474. * @desc_hdr: packet descriptor/TR header
  475. *
  476. * Returns true if EPIB present in the packet
  477. */
  478. static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
  479. {
  480. WARN_ON(!desc_hdr);
  481. return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
  482. }
  483. /**
  484. * cppi5_hdesc_get_psdata - Get pointer on PSDATA
  485. * @desc: Host packet descriptor
  486. *
  487. * Returns pointer on PSDATA in HDesc.
  488. * NULL - if ps_data placed at the start of data buffer.
  489. */
  490. static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
  491. {
  492. u32 psdata_size;
  493. void *psdata;
  494. WARN_ON(!desc);
  495. if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
  496. return NULL;
  497. psdata_size = (desc->hdr.pkt_info0 &
  498. CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
  499. CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
  500. if (!psdata_size)
  501. return NULL;
  502. psdata = &desc->epib;
  503. if (cppi5_hdesc_epib_present(&desc->hdr))
  504. psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
  505. return psdata;
  506. }
  507. static inline u32 *cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t *desc)
  508. {
  509. return (u32 *)cppi5_hdesc_get_psdata(desc);
  510. }
  511. /**
  512. * cppi5_hdesc_get_swdata - Get pointer on swdata
  513. * @desc: Host packet descriptor
  514. *
  515. * Returns pointer on SWDATA in HDesc.
  516. * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
  517. */
  518. static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
  519. {
  520. u32 psdata_size = 0;
  521. void *swdata;
  522. WARN_ON(!desc);
  523. if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
  524. psdata_size = (desc->hdr.pkt_info0 &
  525. CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
  526. CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
  527. swdata = &desc->epib;
  528. if (cppi5_hdesc_epib_present(&desc->hdr))
  529. swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
  530. swdata += (psdata_size << 2);
  531. return swdata;
  532. }
  533. /* ================================== TR ================================== */
  534. #define CPPI5_TR_TYPE_SHIFT (0U)
  535. #define CPPI5_TR_TYPE_MASK GENMASK(3, 0)
  536. #define CPPI5_TR_STATIC BIT(4)
  537. #define CPPI5_TR_WAIT BIT(5)
  538. #define CPPI5_TR_EVENT_SIZE_SHIFT (6U)
  539. #define CPPI5_TR_EVENT_SIZE_MASK GENMASK(7, 6)
  540. #define CPPI5_TR_TRIGGER0_SHIFT (8U)
  541. #define CPPI5_TR_TRIGGER0_MASK GENMASK(9, 8)
  542. #define CPPI5_TR_TRIGGER0_TYPE_SHIFT (10U)
  543. #define CPPI5_TR_TRIGGER0_TYPE_MASK GENMASK(11, 10)
  544. #define CPPI5_TR_TRIGGER1_SHIFT (12U)
  545. #define CPPI5_TR_TRIGGER1_MASK GENMASK(13, 12)
  546. #define CPPI5_TR_TRIGGER1_TYPE_SHIFT (14U)
  547. #define CPPI5_TR_TRIGGER1_TYPE_MASK GENMASK(15, 14)
  548. #define CPPI5_TR_CMD_ID_SHIFT (16U)
  549. #define CPPI5_TR_CMD_ID_MASK GENMASK(23, 16)
  550. #define CPPI5_TR_CSF_FLAGS_SHIFT (24U)
  551. #define CPPI5_TR_CSF_FLAGS_MASK GENMASK(31, 24)
  552. #define CPPI5_TR_CSF_SA_INDIRECT BIT(0)
  553. #define CPPI5_TR_CSF_DA_INDIRECT BIT(1)
  554. #define CPPI5_TR_CSF_SUPR_EVT BIT(2)
  555. #define CPPI5_TR_CSF_EOL_ADV_SHIFT (4U)
  556. #define CPPI5_TR_CSF_EOL_ADV_MASK GENMASK(6, 4)
  557. #define CPPI5_TR_CSF_EOP BIT(7)
  558. /* Udmap TR flags Type field specifies the type of TR. */
  559. enum cppi5_tr_types {
  560. /* type0: One dimensional data move */
  561. CPPI5_TR_TYPE0 = 0,
  562. /* type1: Two dimensional data move */
  563. CPPI5_TR_TYPE1,
  564. /* type2: Three dimensional data move */
  565. CPPI5_TR_TYPE2,
  566. /* type3: Four dimensional data move */
  567. CPPI5_TR_TYPE3,
  568. /* type4: Four dimensional data move with data formatting */
  569. CPPI5_TR_TYPE4,
  570. /* type5: Four dimensional Cache Warm */
  571. CPPI5_TR_TYPE5,
  572. /* type6-7: Reserved */
  573. /* type8: Four Dimensional Block Move */
  574. CPPI5_TR_TYPE8 = 8,
  575. /* type9: Four Dimensional Block Move with Repacking */
  576. CPPI5_TR_TYPE9,
  577. /* type10: Two Dimensional Block Move */
  578. CPPI5_TR_TYPE10,
  579. /* type11: Two Dimensional Block Move with Repacking */
  580. CPPI5_TR_TYPE11,
  581. /* type12-14: Reserved */
  582. /* type15 Four Dimensional Block Move with Repacking and Indirection */
  583. CPPI5_TR_TYPE15 = 15,
  584. CPPI5_TR_TYPE_MAX
  585. };
  586. /*
  587. * Udmap TR Flags EVENT_SIZE field specifies when an event is generated
  588. * for each TR.
  589. */
  590. enum cppi5_tr_event_size {
  591. /* When TR is complete and all status for the TR has been received */
  592. CPPI5_TR_EVENT_SIZE_COMPLETION,
  593. /*
  594. * Type 0: when the last data transaction is sent for the TR;
  595. * Type 1-11: when ICNT1 is decremented
  596. */
  597. CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
  598. /*
  599. * Type 0-1,10-11: when the last data transaction is sent for the TR;
  600. * All other types: when ICNT2 is decremented
  601. */
  602. CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
  603. /*
  604. * Type 0-2,10-11: when the last data transaction is sent for the TR;
  605. * All other types: when ICNT3 is decremented
  606. */
  607. CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
  608. CPPI5_TR_EVENT_SIZE_MAX
  609. };
  610. /*
  611. * Udmap TR Flags TRIGGERx field specifies the type of trigger used to
  612. * enable the TR to transfer data as specified by TRIGGERx_TYPE field.
  613. */
  614. enum cppi5_tr_trigger {
  615. CPPI5_TR_TRIGGER_NONE, /* No Trigger */
  616. CPPI5_TR_TRIGGER_GLOBAL0, /* Global Trigger 0 */
  617. CPPI5_TR_TRIGGER_GLOBAL1, /* Global Trigger 1 */
  618. CPPI5_TR_TRIGGER_LOCAL_EVENT, /* Local Event */
  619. CPPI5_TR_TRIGGER_MAX
  620. };
  621. /*
  622. * Udmap TR Flags TRIGGERx_TYPE field specifies the type of data transfer
  623. * that will be enabled by receiving a trigger as specified by TRIGGERx.
  624. */
  625. enum cppi5_tr_trigger_type {
  626. /* The second inner most loop (ICNT1) will be decremented by 1 */
  627. CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
  628. /* The third inner most loop (ICNT2) will be decremented by 1 */
  629. CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
  630. /* The outer most loop (ICNT3) will be decremented by 1 */
  631. CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
  632. /* The entire TR will be allowed to complete */
  633. CPPI5_TR_TRIGGER_TYPE_ALL,
  634. CPPI5_TR_TRIGGER_TYPE_MAX
  635. };
  636. typedef u32 cppi5_tr_flags_t;
  637. /* Type 0 (One dimensional data move) TR (16 byte) */
  638. struct cppi5_tr_type0_t {
  639. cppi5_tr_flags_t flags;
  640. u16 icnt0;
  641. u16 unused;
  642. u64 addr;
  643. } __aligned(16) __packed;
  644. /* Type 1 (Two dimensional data move) TR (32 byte) */
  645. struct cppi5_tr_type1_t {
  646. cppi5_tr_flags_t flags;
  647. u16 icnt0;
  648. u16 icnt1;
  649. u64 addr;
  650. s32 dim1;
  651. } __aligned(32) __packed;
  652. /* Type 2 (Three dimensional data move) TR (32 byte) */
  653. struct cppi5_tr_type2_t {
  654. cppi5_tr_flags_t flags;
  655. u16 icnt0;
  656. u16 icnt1;
  657. u64 addr;
  658. s32 dim1;
  659. u16 icnt2;
  660. u16 unused;
  661. s32 dim2;
  662. } __aligned(32) __packed;
  663. /* Type 3 (Four dimensional data move) TR (32 byte) */
  664. struct cppi5_tr_type3_t {
  665. cppi5_tr_flags_t flags;
  666. u16 icnt0;
  667. u16 icnt1;
  668. u64 addr;
  669. s32 dim1;
  670. u16 icnt2;
  671. u16 icnt3;
  672. s32 dim2;
  673. s32 dim3;
  674. } __aligned(32) __packed;
  675. /*
  676. * Type 15 (Four Dimensional Block Copy with Repacking and
  677. * Indirection Support) TR (64 byte).
  678. */
  679. struct cppi5_tr_type15_t {
  680. cppi5_tr_flags_t flags;
  681. u16 icnt0;
  682. u16 icnt1;
  683. u64 addr;
  684. s32 dim1;
  685. u16 icnt2;
  686. u16 icnt3;
  687. s32 dim2;
  688. s32 dim3;
  689. u32 _reserved;
  690. s32 ddim1;
  691. u64 daddr;
  692. s32 ddim2;
  693. s32 ddim3;
  694. u16 dicnt0;
  695. u16 dicnt1;
  696. u16 dicnt2;
  697. u16 dicnt3;
  698. } __aligned(64) __packed;
  699. struct cppi5_tr_resp_t {
  700. u8 status;
  701. u8 reserved;
  702. u8 cmd_id;
  703. u8 flags;
  704. } __packed;
  705. #define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT (0U)
  706. #define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK GENMASK(3, 0)
  707. #define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT (4U)
  708. #define CPPI5_TR_RESPONSE_STATUS_INFO_MASK GENMASK(7, 4)
  709. #define CPPI5_TR_RESPONSE_CMDID_SHIFT (16U)
  710. #define CPPI5_TR_RESPONSE_CMDID_MASK GENMASK(23, 16)
  711. #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT (24U)
  712. #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24)
  713. /*
  714. * Udmap TR Response Status Type field is used to determine
  715. * what type of status is being returned.
  716. */
  717. enum cppi5_tr_resp_status_type {
  718. CPPI5_TR_RESPONSE_STATUS_COMPLETE, /* None */
  719. CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR, /* Transfer Error */
  720. CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR, /* Aborted Error */
  721. CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR, /* Submission Error */
  722. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR, /* Unsup. Feature */
  723. CPPI5_TR_RESPONSE_STATUS_MAX
  724. };
  725. /*
  726. * Udmap TR Response Status field values which corresponds
  727. * CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR
  728. */
  729. enum cppi5_tr_resp_status_submission {
  730. /* ICNT0 was 0 */
  731. CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
  732. /* Channel FIFO was full when TR received */
  733. CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
  734. /* Channel is not owned by the submitter */
  735. CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
  736. CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
  737. };
  738. /*
  739. * Udmap TR Response Status field values which corresponds
  740. * CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR
  741. */
  742. enum cppi5_tr_resp_status_unsupported {
  743. /* TR Type not supported */
  744. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
  745. /* STATIC not supported */
  746. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
  747. /* EOL not supported */
  748. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
  749. /* CONFIGURATION SPECIFIC not supported */
  750. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
  751. /* AMODE not supported */
  752. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
  753. /* ELTYPE not supported */
  754. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
  755. /* DFMT not supported */
  756. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
  757. /* SECTR not supported */
  758. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
  759. /* AMODE SPECIFIC field not supported */
  760. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
  761. CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
  762. };
  763. /**
  764. * cppi5_trdesc_calc_size - Calculate TR Descriptor size
  765. * @tr_count: number of TR records
  766. * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
  767. *
  768. * Returns required TR Descriptor size
  769. */
  770. static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
  771. {
  772. /*
  773. * The Size of a TR descriptor is:
  774. * 1 x tr_size : the first 16 bytes is used by the packet info block +
  775. * tr_count x tr_size : Transfer Request Records +
  776. * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
  777. */
  778. return tr_size * (tr_count + 1) +
  779. sizeof(struct cppi5_tr_resp_t) * tr_count;
  780. }
  781. /**
  782. * cppi5_trdesc_init - Init TR Descriptor
  783. * @desc: TR Descriptor
  784. * @tr_count: number of TR records
  785. * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
  786. * @reload_idx: Absolute index to jump to on the 2nd and following passes
  787. * through the TR packet.
  788. * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
  789. * indicates infinite looping.
  790. *
  791. * Init TR Descriptor
  792. */
  793. static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
  794. u32 tr_count, u32 tr_size, u32 reload_idx,
  795. u32 reload_count)
  796. {
  797. WARN_ON(!desc_hdr);
  798. WARN_ON(tr_count & ~CPPI5_INFO0_TRDESC_LASTIDX_MASK);
  799. WARN_ON(reload_idx > CPPI5_INFO0_TRDESC_RLDIDX_MAX);
  800. WARN_ON(reload_count > CPPI5_INFO0_TRDESC_RLDCNT_MAX);
  801. desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
  802. CPPI5_INFO0_HDESC_TYPE_SHIFT;
  803. desc_hdr->pkt_info0 |= (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
  804. CPPI5_INFO0_TRDESC_RLDCNT_MASK;
  805. desc_hdr->pkt_info0 |= (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
  806. CPPI5_INFO0_TRDESC_RLDIDX_MASK;
  807. desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
  808. desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
  809. CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
  810. CPPI5_INFO1_TRDESC_RECSIZE_MASK;
  811. }
  812. /**
  813. * cppi5_tr_init - Init TR record
  814. * @flags: Pointer to the TR's flags
  815. * @type: TR type
  816. * @static_tr: TR is static
  817. * @wait: Wait for TR completion before allow the next TR to start
  818. * @event_size: output event generation cfg
  819. * @cmd_id: TR identifier (application specifics)
  820. *
  821. * Init TR record
  822. */
  823. static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
  824. enum cppi5_tr_types type, bool static_tr,
  825. bool wait, enum cppi5_tr_event_size event_size,
  826. u32 cmd_id)
  827. {
  828. WARN_ON(!flags);
  829. *flags = type;
  830. *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
  831. CPPI5_TR_EVENT_SIZE_MASK;
  832. *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
  833. CPPI5_TR_CMD_ID_MASK;
  834. if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
  835. *flags |= CPPI5_TR_STATIC;
  836. if (wait)
  837. *flags |= CPPI5_TR_WAIT;
  838. }
  839. /**
  840. * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
  841. * @flags: Pointer to the TR's flags
  842. * @trigger0: trigger0 selection
  843. * @trigger0_type: type of data transfer that will be enabled by trigger0
  844. * @trigger1: trigger1 selection
  845. * @trigger1_type: type of data transfer that will be enabled by trigger1
  846. *
  847. * Configure the triggers for the TR
  848. */
  849. static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
  850. enum cppi5_tr_trigger trigger0,
  851. enum cppi5_tr_trigger_type trigger0_type,
  852. enum cppi5_tr_trigger trigger1,
  853. enum cppi5_tr_trigger_type trigger1_type)
  854. {
  855. WARN_ON(!flags);
  856. *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
  857. CPPI5_TR_TRIGGER0_MASK;
  858. *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
  859. CPPI5_TR_TRIGGER0_TYPE_MASK;
  860. *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
  861. CPPI5_TR_TRIGGER1_MASK;
  862. *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
  863. CPPI5_TR_TRIGGER1_TYPE_MASK;
  864. }
  865. /**
  866. * cppi5_tr_cflag_set - Update the Configuration specific flags
  867. * @flags: Pointer to the TR's flags
  868. * @csf: Configuration specific flags
  869. *
  870. * Set a bit in Configuration Specific Flags section of the TR flags.
  871. */
  872. static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
  873. {
  874. WARN_ON(!flags);
  875. *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
  876. CPPI5_TR_CSF_FLAGS_MASK;
  877. }
  878. #endif /* __TI_CPPI5_H__ */