musb_host.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver host support
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #ifndef __UBOOT__
  11. #include <dm/device_compat.h>
  12. #include <dm/devres.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/sched.h>
  17. #include <linux/slab.h>
  18. #include <linux/errno.h>
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/dma-mapping.h>
  22. #else
  23. #include <common.h>
  24. #include <usb.h>
  25. #include <linux/bug.h>
  26. #include "linux-compat.h"
  27. #include "usb-compat.h"
  28. #endif
  29. #include "musb_core.h"
  30. #include "musb_host.h"
  31. /* MUSB HOST status 22-mar-2006
  32. *
  33. * - There's still lots of partial code duplication for fault paths, so
  34. * they aren't handled as consistently as they need to be.
  35. *
  36. * - PIO mostly behaved when last tested.
  37. * + including ep0, with all usbtest cases 9, 10
  38. * + usbtest 14 (ep0out) doesn't seem to run at all
  39. * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
  40. * configurations, but otherwise double buffering passes basic tests.
  41. * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
  42. *
  43. * - DMA (CPPI) ... partially behaves, not currently recommended
  44. * + about 1/15 the speed of typical EHCI implementations (PCI)
  45. * + RX, all too often reqpkt seems to misbehave after tx
  46. * + TX, no known issues (other than evident silicon issue)
  47. *
  48. * - DMA (Mentor/OMAP) ...has at least toggle update problems
  49. *
  50. * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
  51. * starvation ... nothing yet for TX, interrupt, or bulk.
  52. *
  53. * - Not tested with HNP, but some SRP paths seem to behave.
  54. *
  55. * NOTE 24-August-2006:
  56. *
  57. * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
  58. * extra endpoint for periodic use enabling hub + keybd + mouse. That
  59. * mostly works, except that with "usbnet" it's easy to trigger cases
  60. * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
  61. * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
  62. * although ARP RX wins. (That test was done with a full speed link.)
  63. */
  64. /*
  65. * NOTE on endpoint usage:
  66. *
  67. * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
  68. * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
  69. * (Yes, bulk _could_ use more of the endpoints than that, and would even
  70. * benefit from it.)
  71. *
  72. * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
  73. * So far that scheduling is both dumb and optimistic: the endpoint will be
  74. * "claimed" until its software queue is no longer refilled. No multiplexing
  75. * of transfers between endpoints, or anything clever.
  76. */
  77. static void musb_ep_program(struct musb *musb, u8 epnum,
  78. struct urb *urb, int is_out,
  79. u8 *buf, u32 offset, u32 len);
  80. /*
  81. * Clear TX fifo. Needed to avoid BABBLE errors.
  82. */
  83. static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
  84. {
  85. struct musb *musb = ep->musb;
  86. void __iomem *epio = ep->regs;
  87. u16 csr;
  88. u16 lastcsr = 0;
  89. int retries = 1000;
  90. csr = musb_readw(epio, MUSB_TXCSR);
  91. while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  92. if (csr != lastcsr)
  93. dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
  94. lastcsr = csr;
  95. csr |= MUSB_TXCSR_FLUSHFIFO;
  96. musb_writew(epio, MUSB_TXCSR, csr);
  97. csr = musb_readw(epio, MUSB_TXCSR);
  98. if (WARN(retries-- < 1,
  99. "Could not flush host TX%d fifo: csr: %04x\n",
  100. ep->epnum, csr))
  101. return;
  102. mdelay(1);
  103. }
  104. }
  105. static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
  106. {
  107. void __iomem *epio = ep->regs;
  108. u16 csr;
  109. int retries = 5;
  110. /* scrub any data left in the fifo */
  111. do {
  112. csr = musb_readw(epio, MUSB_TXCSR);
  113. if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
  114. break;
  115. musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
  116. csr = musb_readw(epio, MUSB_TXCSR);
  117. udelay(10);
  118. } while (--retries);
  119. WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
  120. ep->epnum, csr);
  121. /* and reset for the next transfer */
  122. musb_writew(epio, MUSB_TXCSR, 0);
  123. }
  124. /*
  125. * Start transmit. Caller is responsible for locking shared resources.
  126. * musb must be locked.
  127. */
  128. static inline void musb_h_tx_start(struct musb_hw_ep *ep)
  129. {
  130. u16 txcsr;
  131. /* NOTE: no locks here; caller should lock and select EP */
  132. if (ep->epnum) {
  133. txcsr = musb_readw(ep->regs, MUSB_TXCSR);
  134. txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
  135. musb_writew(ep->regs, MUSB_TXCSR, txcsr);
  136. } else {
  137. txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
  138. musb_writew(ep->regs, MUSB_CSR0, txcsr);
  139. }
  140. }
  141. static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
  142. {
  143. u16 txcsr;
  144. /* NOTE: no locks here; caller should lock and select EP */
  145. txcsr = musb_readw(ep->regs, MUSB_TXCSR);
  146. txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
  147. if (is_cppi_enabled())
  148. txcsr |= MUSB_TXCSR_DMAMODE;
  149. musb_writew(ep->regs, MUSB_TXCSR, txcsr);
  150. }
  151. static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
  152. {
  153. if (is_in != 0 || ep->is_shared_fifo)
  154. ep->in_qh = qh;
  155. if (is_in == 0 || ep->is_shared_fifo)
  156. ep->out_qh = qh;
  157. }
  158. static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
  159. {
  160. return is_in ? ep->in_qh : ep->out_qh;
  161. }
  162. /*
  163. * Start the URB at the front of an endpoint's queue
  164. * end must be claimed from the caller.
  165. *
  166. * Context: controller locked, irqs blocked
  167. */
  168. static void
  169. musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
  170. {
  171. u16 frame;
  172. u32 len;
  173. void __iomem *mbase = musb->mregs;
  174. struct urb *urb = next_urb(qh);
  175. void *buf = urb->transfer_buffer;
  176. u32 offset = 0;
  177. struct musb_hw_ep *hw_ep = qh->hw_ep;
  178. unsigned pipe = urb->pipe;
  179. u8 address = usb_pipedevice(pipe);
  180. int epnum = hw_ep->epnum;
  181. /* initialize software qh state */
  182. qh->offset = 0;
  183. qh->segsize = 0;
  184. /* gather right source of data */
  185. switch (qh->type) {
  186. case USB_ENDPOINT_XFER_CONTROL:
  187. /* control transfers always start with SETUP */
  188. is_in = 0;
  189. musb->ep0_stage = MUSB_EP0_START;
  190. buf = urb->setup_packet;
  191. len = 8;
  192. break;
  193. #ifndef __UBOOT__
  194. case USB_ENDPOINT_XFER_ISOC:
  195. qh->iso_idx = 0;
  196. qh->frame = 0;
  197. offset = urb->iso_frame_desc[0].offset;
  198. len = urb->iso_frame_desc[0].length;
  199. break;
  200. #endif
  201. default: /* bulk, interrupt */
  202. /* actual_length may be nonzero on retry paths */
  203. buf = urb->transfer_buffer + urb->actual_length;
  204. len = urb->transfer_buffer_length - urb->actual_length;
  205. }
  206. dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
  207. qh, urb, address, qh->epnum,
  208. is_in ? "in" : "out",
  209. ({char *s; switch (qh->type) {
  210. case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
  211. case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
  212. #ifndef __UBOOT__
  213. case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
  214. #endif
  215. default: s = "-intr"; break;
  216. }; s; }),
  217. epnum, buf + offset, len);
  218. /* Configure endpoint */
  219. musb_ep_set_qh(hw_ep, is_in, qh);
  220. musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
  221. /* transmit may have more work: start it when it is time */
  222. if (is_in)
  223. return;
  224. /* determine if the time is right for a periodic transfer */
  225. switch (qh->type) {
  226. #ifndef __UBOOT__
  227. case USB_ENDPOINT_XFER_ISOC:
  228. #endif
  229. case USB_ENDPOINT_XFER_INT:
  230. dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
  231. frame = musb_readw(mbase, MUSB_FRAME);
  232. /* FIXME this doesn't implement that scheduling policy ...
  233. * or handle framecounter wrapping
  234. */
  235. #ifndef __UBOOT__
  236. if ((urb->transfer_flags & URB_ISO_ASAP)
  237. || (frame >= urb->start_frame)) {
  238. /* REVISIT the SOF irq handler shouldn't duplicate
  239. * this code; and we don't init urb->start_frame...
  240. */
  241. qh->frame = 0;
  242. goto start;
  243. } else {
  244. #endif
  245. qh->frame = urb->start_frame;
  246. /* enable SOF interrupt so we can count down */
  247. dev_dbg(musb->controller, "SOF for %d\n", epnum);
  248. #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
  249. musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
  250. #endif
  251. #ifndef __UBOOT__
  252. }
  253. #endif
  254. break;
  255. default:
  256. start:
  257. dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
  258. hw_ep->tx_channel ? "dma" : "pio");
  259. if (!hw_ep->tx_channel)
  260. musb_h_tx_start(hw_ep);
  261. else if (is_cppi_enabled() || tusb_dma_omap())
  262. musb_h_tx_dma_start(hw_ep);
  263. }
  264. }
  265. /* Context: caller owns controller lock, IRQs are blocked */
  266. static void musb_giveback(struct musb *musb, struct urb *urb, int status)
  267. __releases(musb->lock)
  268. __acquires(musb->lock)
  269. {
  270. dev_dbg(musb->controller,
  271. "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
  272. urb, urb->complete, status,
  273. usb_pipedevice(urb->pipe),
  274. usb_pipeendpoint(urb->pipe),
  275. usb_pipein(urb->pipe) ? "in" : "out",
  276. urb->actual_length, urb->transfer_buffer_length
  277. );
  278. usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
  279. spin_unlock(&musb->lock);
  280. usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
  281. spin_lock(&musb->lock);
  282. }
  283. /* For bulk/interrupt endpoints only */
  284. static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
  285. struct urb *urb)
  286. {
  287. void __iomem *epio = qh->hw_ep->regs;
  288. u16 csr;
  289. /*
  290. * FIXME: the current Mentor DMA code seems to have
  291. * problems getting toggle correct.
  292. */
  293. if (is_in)
  294. csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
  295. else
  296. csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
  297. usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
  298. }
  299. /*
  300. * Advance this hardware endpoint's queue, completing the specified URB and
  301. * advancing to either the next URB queued to that qh, or else invalidating
  302. * that qh and advancing to the next qh scheduled after the current one.
  303. *
  304. * Context: caller owns controller lock, IRQs are blocked
  305. */
  306. static void musb_advance_schedule(struct musb *musb, struct urb *urb,
  307. struct musb_hw_ep *hw_ep, int is_in)
  308. {
  309. struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
  310. struct musb_hw_ep *ep = qh->hw_ep;
  311. int ready = qh->is_ready;
  312. int status;
  313. status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
  314. /* save toggle eagerly, for paranoia */
  315. switch (qh->type) {
  316. case USB_ENDPOINT_XFER_BULK:
  317. case USB_ENDPOINT_XFER_INT:
  318. musb_save_toggle(qh, is_in, urb);
  319. break;
  320. #ifndef __UBOOT__
  321. case USB_ENDPOINT_XFER_ISOC:
  322. if (status == 0 && urb->error_count)
  323. status = -EXDEV;
  324. break;
  325. #endif
  326. }
  327. qh->is_ready = 0;
  328. musb_giveback(musb, urb, status);
  329. qh->is_ready = ready;
  330. /* reclaim resources (and bandwidth) ASAP; deschedule it, and
  331. * invalidate qh as soon as list_empty(&hep->urb_list)
  332. */
  333. if (list_empty(&qh->hep->urb_list)) {
  334. struct list_head *head;
  335. struct dma_controller *dma = musb->dma_controller;
  336. if (is_in) {
  337. ep->rx_reinit = 1;
  338. if (ep->rx_channel) {
  339. dma->channel_release(ep->rx_channel);
  340. ep->rx_channel = NULL;
  341. }
  342. } else {
  343. ep->tx_reinit = 1;
  344. if (ep->tx_channel) {
  345. dma->channel_release(ep->tx_channel);
  346. ep->tx_channel = NULL;
  347. }
  348. }
  349. /* Clobber old pointers to this qh */
  350. musb_ep_set_qh(ep, is_in, NULL);
  351. qh->hep->hcpriv = NULL;
  352. switch (qh->type) {
  353. case USB_ENDPOINT_XFER_CONTROL:
  354. case USB_ENDPOINT_XFER_BULK:
  355. /* fifo policy for these lists, except that NAKing
  356. * should rotate a qh to the end (for fairness).
  357. */
  358. if (qh->mux == 1) {
  359. head = qh->ring.prev;
  360. list_del(&qh->ring);
  361. kfree(qh);
  362. qh = first_qh(head);
  363. break;
  364. }
  365. case USB_ENDPOINT_XFER_ISOC:
  366. case USB_ENDPOINT_XFER_INT:
  367. /* this is where periodic bandwidth should be
  368. * de-allocated if it's tracked and allocated;
  369. * and where we'd update the schedule tree...
  370. */
  371. kfree(qh);
  372. qh = NULL;
  373. break;
  374. }
  375. }
  376. if (qh != NULL && qh->is_ready) {
  377. dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
  378. hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
  379. musb_start_urb(musb, is_in, qh);
  380. }
  381. }
  382. static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
  383. {
  384. /* we don't want fifo to fill itself again;
  385. * ignore dma (various models),
  386. * leave toggle alone (may not have been saved yet)
  387. */
  388. csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
  389. csr &= ~(MUSB_RXCSR_H_REQPKT
  390. | MUSB_RXCSR_H_AUTOREQ
  391. | MUSB_RXCSR_AUTOCLEAR);
  392. /* write 2x to allow double buffering */
  393. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  394. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  395. /* flush writebuffer */
  396. return musb_readw(hw_ep->regs, MUSB_RXCSR);
  397. }
  398. /*
  399. * PIO RX for a packet (or part of it).
  400. */
  401. static bool
  402. musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
  403. {
  404. u16 rx_count;
  405. u8 *buf;
  406. u16 csr;
  407. bool done = false;
  408. u32 length;
  409. int do_flush = 0;
  410. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  411. void __iomem *epio = hw_ep->regs;
  412. struct musb_qh *qh = hw_ep->in_qh;
  413. int pipe = urb->pipe;
  414. void *buffer = urb->transfer_buffer;
  415. /* musb_ep_select(mbase, epnum); */
  416. rx_count = musb_readw(epio, MUSB_RXCOUNT);
  417. dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
  418. urb->transfer_buffer, qh->offset,
  419. urb->transfer_buffer_length);
  420. /* unload FIFO */
  421. #ifndef __UBOOT__
  422. if (usb_pipeisoc(pipe)) {
  423. int status = 0;
  424. struct usb_iso_packet_descriptor *d;
  425. if (iso_err) {
  426. status = -EILSEQ;
  427. urb->error_count++;
  428. }
  429. d = urb->iso_frame_desc + qh->iso_idx;
  430. buf = buffer + d->offset;
  431. length = d->length;
  432. if (rx_count > length) {
  433. if (status == 0) {
  434. status = -EOVERFLOW;
  435. urb->error_count++;
  436. }
  437. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
  438. do_flush = 1;
  439. } else
  440. length = rx_count;
  441. urb->actual_length += length;
  442. d->actual_length = length;
  443. d->status = status;
  444. /* see if we are done */
  445. done = (++qh->iso_idx >= urb->number_of_packets);
  446. } else {
  447. #endif
  448. /* non-isoch */
  449. buf = buffer + qh->offset;
  450. length = urb->transfer_buffer_length - qh->offset;
  451. if (rx_count > length) {
  452. if (urb->status == -EINPROGRESS)
  453. urb->status = -EOVERFLOW;
  454. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
  455. do_flush = 1;
  456. } else
  457. length = rx_count;
  458. urb->actual_length += length;
  459. qh->offset += length;
  460. /* see if we are done */
  461. done = (urb->actual_length == urb->transfer_buffer_length)
  462. || (rx_count < qh->maxpacket)
  463. || (urb->status != -EINPROGRESS);
  464. if (done
  465. && (urb->status == -EINPROGRESS)
  466. && (urb->transfer_flags & URB_SHORT_NOT_OK)
  467. && (urb->actual_length
  468. < urb->transfer_buffer_length))
  469. urb->status = -EREMOTEIO;
  470. #ifndef __UBOOT__
  471. }
  472. #endif
  473. musb_read_fifo(hw_ep, length, buf);
  474. csr = musb_readw(epio, MUSB_RXCSR);
  475. csr |= MUSB_RXCSR_H_WZC_BITS;
  476. if (unlikely(do_flush))
  477. musb_h_flush_rxfifo(hw_ep, csr);
  478. else {
  479. /* REVISIT this assumes AUTOCLEAR is never set */
  480. csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
  481. if (!done)
  482. csr |= MUSB_RXCSR_H_REQPKT;
  483. musb_writew(epio, MUSB_RXCSR, csr);
  484. }
  485. return done;
  486. }
  487. /* we don't always need to reinit a given side of an endpoint...
  488. * when we do, use tx/rx reinit routine and then construct a new CSR
  489. * to address data toggle, NYET, and DMA or PIO.
  490. *
  491. * it's possible that driver bugs (especially for DMA) or aborting a
  492. * transfer might have left the endpoint busier than it should be.
  493. * the busy/not-empty tests are basically paranoia.
  494. */
  495. static void
  496. musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
  497. {
  498. u16 csr;
  499. /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
  500. * That always uses tx_reinit since ep0 repurposes TX register
  501. * offsets; the initial SETUP packet is also a kind of OUT.
  502. */
  503. /* if programmed for Tx, put it in RX mode */
  504. if (ep->is_shared_fifo) {
  505. csr = musb_readw(ep->regs, MUSB_TXCSR);
  506. if (csr & MUSB_TXCSR_MODE) {
  507. musb_h_tx_flush_fifo(ep);
  508. csr = musb_readw(ep->regs, MUSB_TXCSR);
  509. musb_writew(ep->regs, MUSB_TXCSR,
  510. csr | MUSB_TXCSR_FRCDATATOG);
  511. }
  512. /*
  513. * Clear the MODE bit (and everything else) to enable Rx.
  514. * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
  515. */
  516. if (csr & MUSB_TXCSR_DMAMODE)
  517. musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
  518. musb_writew(ep->regs, MUSB_TXCSR, 0);
  519. /* scrub all previous state, clearing toggle */
  520. } else {
  521. csr = musb_readw(ep->regs, MUSB_RXCSR);
  522. if (csr & MUSB_RXCSR_RXPKTRDY)
  523. WARNING("rx%d, packet/%d ready?\n", ep->epnum,
  524. musb_readw(ep->regs, MUSB_RXCOUNT));
  525. musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
  526. }
  527. /* target addr and (for multipoint) hub addr/port */
  528. if (musb->is_multipoint) {
  529. musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
  530. musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
  531. musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
  532. } else
  533. musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
  534. /* protocol/endpoint, interval/NAKlimit, i/o size */
  535. musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
  536. musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
  537. /* NOTE: bulk combining rewrites high bits of maxpacket */
  538. /* Set RXMAXP with the FIFO size of the endpoint
  539. * to disable double buffer mode.
  540. */
  541. if (musb->double_buffer_not_ok)
  542. musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
  543. else
  544. musb_writew(ep->regs, MUSB_RXMAXP,
  545. qh->maxpacket | ((qh->hb_mult - 1) << 11));
  546. ep->rx_reinit = 0;
  547. }
  548. static bool musb_tx_dma_program(struct dma_controller *dma,
  549. struct musb_hw_ep *hw_ep, struct musb_qh *qh,
  550. struct urb *urb, u32 offset, u32 length)
  551. {
  552. struct dma_channel *channel = hw_ep->tx_channel;
  553. void __iomem *epio = hw_ep->regs;
  554. u16 pkt_size = qh->maxpacket;
  555. u16 csr;
  556. u8 mode;
  557. #ifdef CONFIG_USB_INVENTRA_DMA
  558. if (length > channel->max_len)
  559. length = channel->max_len;
  560. csr = musb_readw(epio, MUSB_TXCSR);
  561. if (length > pkt_size) {
  562. mode = 1;
  563. csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
  564. /* autoset shouldn't be set in high bandwidth */
  565. if (qh->hb_mult == 1)
  566. csr |= MUSB_TXCSR_AUTOSET;
  567. } else {
  568. mode = 0;
  569. csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
  570. csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
  571. }
  572. channel->desired_mode = mode;
  573. musb_writew(epio, MUSB_TXCSR, csr);
  574. #else
  575. if (!is_cppi_enabled() && !tusb_dma_omap())
  576. return false;
  577. channel->actual_len = 0;
  578. /*
  579. * TX uses "RNDIS" mode automatically but needs help
  580. * to identify the zero-length-final-packet case.
  581. */
  582. mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
  583. #endif
  584. qh->segsize = length;
  585. /*
  586. * Ensure the data reaches to main memory before starting
  587. * DMA transfer
  588. */
  589. wmb();
  590. if (!dma->channel_program(channel, pkt_size, mode,
  591. urb->transfer_dma + offset, length)) {
  592. dma->channel_release(channel);
  593. hw_ep->tx_channel = NULL;
  594. csr = musb_readw(epio, MUSB_TXCSR);
  595. csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
  596. musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
  597. return false;
  598. }
  599. return true;
  600. }
  601. /*
  602. * Program an HDRC endpoint as per the given URB
  603. * Context: irqs blocked, controller lock held
  604. */
  605. static void musb_ep_program(struct musb *musb, u8 epnum,
  606. struct urb *urb, int is_out,
  607. u8 *buf, u32 offset, u32 len)
  608. {
  609. struct dma_controller *dma_controller;
  610. struct dma_channel *dma_channel;
  611. u8 dma_ok;
  612. void __iomem *mbase = musb->mregs;
  613. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  614. void __iomem *epio = hw_ep->regs;
  615. struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
  616. u16 packet_sz = qh->maxpacket;
  617. dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
  618. "h_addr%02x h_port%02x bytes %d\n",
  619. is_out ? "-->" : "<--",
  620. epnum, urb, urb->dev->speed,
  621. qh->addr_reg, qh->epnum, is_out ? "out" : "in",
  622. qh->h_addr_reg, qh->h_port_reg,
  623. len);
  624. musb_ep_select(mbase, epnum);
  625. /* candidate for DMA? */
  626. dma_controller = musb->dma_controller;
  627. if (is_dma_capable() && epnum && dma_controller) {
  628. dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
  629. if (!dma_channel) {
  630. dma_channel = dma_controller->channel_alloc(
  631. dma_controller, hw_ep, is_out);
  632. if (is_out)
  633. hw_ep->tx_channel = dma_channel;
  634. else
  635. hw_ep->rx_channel = dma_channel;
  636. }
  637. } else
  638. dma_channel = NULL;
  639. /* make sure we clear DMAEnab, autoSet bits from previous run */
  640. /* OUT/transmit/EP0 or IN/receive? */
  641. if (is_out) {
  642. u16 csr;
  643. u16 int_txe;
  644. u16 load_count;
  645. csr = musb_readw(epio, MUSB_TXCSR);
  646. /* disable interrupt in case we flush */
  647. int_txe = musb_readw(mbase, MUSB_INTRTXE);
  648. musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
  649. /* general endpoint setup */
  650. if (epnum) {
  651. /* flush all old state, set default */
  652. musb_h_tx_flush_fifo(hw_ep);
  653. /*
  654. * We must not clear the DMAMODE bit before or in
  655. * the same cycle with the DMAENAB bit, so we clear
  656. * the latter first...
  657. */
  658. csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
  659. | MUSB_TXCSR_AUTOSET
  660. | MUSB_TXCSR_DMAENAB
  661. | MUSB_TXCSR_FRCDATATOG
  662. | MUSB_TXCSR_H_RXSTALL
  663. | MUSB_TXCSR_H_ERROR
  664. | MUSB_TXCSR_TXPKTRDY
  665. );
  666. csr |= MUSB_TXCSR_MODE;
  667. if (usb_gettoggle(urb->dev, qh->epnum, 1))
  668. csr |= MUSB_TXCSR_H_WR_DATATOGGLE
  669. | MUSB_TXCSR_H_DATATOGGLE;
  670. else
  671. csr |= MUSB_TXCSR_CLRDATATOG;
  672. musb_writew(epio, MUSB_TXCSR, csr);
  673. /* REVISIT may need to clear FLUSHFIFO ... */
  674. csr &= ~MUSB_TXCSR_DMAMODE;
  675. musb_writew(epio, MUSB_TXCSR, csr);
  676. csr = musb_readw(epio, MUSB_TXCSR);
  677. } else {
  678. /* endpoint 0: just flush */
  679. musb_h_ep0_flush_fifo(hw_ep);
  680. }
  681. /* target addr and (for multipoint) hub addr/port */
  682. if (musb->is_multipoint) {
  683. musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
  684. musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
  685. musb_write_txhubport(mbase, epnum, qh->h_port_reg);
  686. /* FIXME if !epnum, do the same for RX ... */
  687. } else
  688. musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
  689. /* protocol/endpoint/interval/NAKlimit */
  690. if (epnum) {
  691. musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
  692. if (musb->double_buffer_not_ok)
  693. musb_writew(epio, MUSB_TXMAXP,
  694. hw_ep->max_packet_sz_tx);
  695. else if (can_bulk_split(musb, qh->type))
  696. musb_writew(epio, MUSB_TXMAXP, packet_sz
  697. | ((hw_ep->max_packet_sz_tx /
  698. packet_sz) - 1) << 11);
  699. else
  700. musb_writew(epio, MUSB_TXMAXP,
  701. qh->maxpacket |
  702. ((qh->hb_mult - 1) << 11));
  703. musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
  704. } else {
  705. musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
  706. if (musb->is_multipoint)
  707. musb_writeb(epio, MUSB_TYPE0,
  708. qh->type_reg);
  709. }
  710. if (can_bulk_split(musb, qh->type))
  711. load_count = min((u32) hw_ep->max_packet_sz_tx,
  712. len);
  713. else
  714. load_count = min((u32) packet_sz, len);
  715. if (dma_channel && musb_tx_dma_program(dma_controller,
  716. hw_ep, qh, urb, offset, len))
  717. load_count = 0;
  718. if (load_count) {
  719. /* PIO to load FIFO */
  720. qh->segsize = load_count;
  721. musb_write_fifo(hw_ep, load_count, buf);
  722. }
  723. /* re-enable interrupt */
  724. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  725. /* IN/receive */
  726. } else {
  727. u16 csr;
  728. if (hw_ep->rx_reinit) {
  729. musb_rx_reinit(musb, qh, hw_ep);
  730. /* init new state: toggle and NYET, maybe DMA later */
  731. if (usb_gettoggle(urb->dev, qh->epnum, 0))
  732. csr = MUSB_RXCSR_H_WR_DATATOGGLE
  733. | MUSB_RXCSR_H_DATATOGGLE;
  734. else
  735. csr = 0;
  736. if (qh->type == USB_ENDPOINT_XFER_INT)
  737. csr |= MUSB_RXCSR_DISNYET;
  738. } else {
  739. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  740. if (csr & (MUSB_RXCSR_RXPKTRDY
  741. | MUSB_RXCSR_DMAENAB
  742. | MUSB_RXCSR_H_REQPKT))
  743. ERR("broken !rx_reinit, ep%d csr %04x\n",
  744. hw_ep->epnum, csr);
  745. /* scrub any stale state, leaving toggle alone */
  746. csr &= MUSB_RXCSR_DISNYET;
  747. }
  748. /* kick things off */
  749. if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
  750. /* Candidate for DMA */
  751. dma_channel->actual_len = 0L;
  752. qh->segsize = len;
  753. /* AUTOREQ is in a DMA register */
  754. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  755. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  756. /*
  757. * Unless caller treats short RX transfers as
  758. * errors, we dare not queue multiple transfers.
  759. */
  760. dma_ok = dma_controller->channel_program(dma_channel,
  761. packet_sz, !(urb->transfer_flags &
  762. URB_SHORT_NOT_OK),
  763. urb->transfer_dma + offset,
  764. qh->segsize);
  765. if (!dma_ok) {
  766. dma_controller->channel_release(dma_channel);
  767. hw_ep->rx_channel = dma_channel = NULL;
  768. } else
  769. csr |= MUSB_RXCSR_DMAENAB;
  770. }
  771. csr |= MUSB_RXCSR_H_REQPKT;
  772. dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
  773. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  774. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  775. }
  776. }
  777. /*
  778. * Service the default endpoint (ep0) as host.
  779. * Return true until it's time to start the status stage.
  780. */
  781. static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
  782. {
  783. bool more = false;
  784. u8 *fifo_dest = NULL;
  785. u16 fifo_count = 0;
  786. struct musb_hw_ep *hw_ep = musb->control_ep;
  787. struct musb_qh *qh = hw_ep->in_qh;
  788. struct usb_ctrlrequest *request;
  789. switch (musb->ep0_stage) {
  790. case MUSB_EP0_IN:
  791. fifo_dest = urb->transfer_buffer + urb->actual_length;
  792. fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
  793. urb->actual_length);
  794. if (fifo_count < len)
  795. urb->status = -EOVERFLOW;
  796. musb_read_fifo(hw_ep, fifo_count, fifo_dest);
  797. urb->actual_length += fifo_count;
  798. if (len < qh->maxpacket) {
  799. /* always terminate on short read; it's
  800. * rarely reported as an error.
  801. */
  802. } else if (urb->actual_length <
  803. urb->transfer_buffer_length)
  804. more = true;
  805. break;
  806. case MUSB_EP0_START:
  807. request = (struct usb_ctrlrequest *) urb->setup_packet;
  808. if (!request->wLength) {
  809. dev_dbg(musb->controller, "start no-DATA\n");
  810. break;
  811. } else if (request->bRequestType & USB_DIR_IN) {
  812. dev_dbg(musb->controller, "start IN-DATA\n");
  813. musb->ep0_stage = MUSB_EP0_IN;
  814. more = true;
  815. break;
  816. } else {
  817. dev_dbg(musb->controller, "start OUT-DATA\n");
  818. musb->ep0_stage = MUSB_EP0_OUT;
  819. more = true;
  820. }
  821. /* FALLTHROUGH */
  822. case MUSB_EP0_OUT:
  823. fifo_count = min_t(size_t, qh->maxpacket,
  824. urb->transfer_buffer_length -
  825. urb->actual_length);
  826. if (fifo_count) {
  827. fifo_dest = (u8 *) (urb->transfer_buffer
  828. + urb->actual_length);
  829. dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
  830. fifo_count,
  831. (fifo_count == 1) ? "" : "s",
  832. fifo_dest);
  833. musb_write_fifo(hw_ep, fifo_count, fifo_dest);
  834. urb->actual_length += fifo_count;
  835. more = true;
  836. }
  837. break;
  838. default:
  839. ERR("bogus ep0 stage %d\n", musb->ep0_stage);
  840. break;
  841. }
  842. return more;
  843. }
  844. /*
  845. * Handle default endpoint interrupt as host. Only called in IRQ time
  846. * from musb_interrupt().
  847. *
  848. * called with controller irqlocked
  849. */
  850. irqreturn_t musb_h_ep0_irq(struct musb *musb)
  851. {
  852. struct urb *urb;
  853. u16 csr, len;
  854. int status = 0;
  855. void __iomem *mbase = musb->mregs;
  856. struct musb_hw_ep *hw_ep = musb->control_ep;
  857. void __iomem *epio = hw_ep->regs;
  858. struct musb_qh *qh = hw_ep->in_qh;
  859. bool complete = false;
  860. irqreturn_t retval = IRQ_NONE;
  861. /* ep0 only has one queue, "in" */
  862. urb = next_urb(qh);
  863. musb_ep_select(mbase, 0);
  864. csr = musb_readw(epio, MUSB_CSR0);
  865. len = (csr & MUSB_CSR0_RXPKTRDY)
  866. ? musb_readb(epio, MUSB_COUNT0)
  867. : 0;
  868. dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
  869. csr, qh, len, urb, musb->ep0_stage);
  870. /* if we just did status stage, we are done */
  871. if (MUSB_EP0_STATUS == musb->ep0_stage) {
  872. retval = IRQ_HANDLED;
  873. complete = true;
  874. }
  875. /* prepare status */
  876. if (csr & MUSB_CSR0_H_RXSTALL) {
  877. dev_dbg(musb->controller, "STALLING ENDPOINT\n");
  878. status = -EPIPE;
  879. } else if (csr & MUSB_CSR0_H_ERROR) {
  880. dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
  881. status = -EPROTO;
  882. } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
  883. dev_dbg(musb->controller, "control NAK timeout\n");
  884. /* NOTE: this code path would be a good place to PAUSE a
  885. * control transfer, if another one is queued, so that
  886. * ep0 is more likely to stay busy. That's already done
  887. * for bulk RX transfers.
  888. *
  889. * if (qh->ring.next != &musb->control), then
  890. * we have a candidate... NAKing is *NOT* an error
  891. */
  892. musb_writew(epio, MUSB_CSR0, 0);
  893. retval = IRQ_HANDLED;
  894. }
  895. if (status) {
  896. dev_dbg(musb->controller, "aborting\n");
  897. retval = IRQ_HANDLED;
  898. if (urb)
  899. urb->status = status;
  900. complete = true;
  901. /* use the proper sequence to abort the transfer */
  902. if (csr & MUSB_CSR0_H_REQPKT) {
  903. csr &= ~MUSB_CSR0_H_REQPKT;
  904. musb_writew(epio, MUSB_CSR0, csr);
  905. csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
  906. musb_writew(epio, MUSB_CSR0, csr);
  907. } else {
  908. musb_h_ep0_flush_fifo(hw_ep);
  909. }
  910. musb_writeb(epio, MUSB_NAKLIMIT0, 0);
  911. /* clear it */
  912. musb_writew(epio, MUSB_CSR0, 0);
  913. }
  914. if (unlikely(!urb)) {
  915. /* stop endpoint since we have no place for its data, this
  916. * SHOULD NEVER HAPPEN! */
  917. ERR("no URB for end 0\n");
  918. musb_h_ep0_flush_fifo(hw_ep);
  919. goto done;
  920. }
  921. if (!complete) {
  922. /* call common logic and prepare response */
  923. if (musb_h_ep0_continue(musb, len, urb)) {
  924. /* more packets required */
  925. csr = (MUSB_EP0_IN == musb->ep0_stage)
  926. ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
  927. } else {
  928. /* data transfer complete; perform status phase */
  929. if (usb_pipeout(urb->pipe)
  930. || !urb->transfer_buffer_length)
  931. csr = MUSB_CSR0_H_STATUSPKT
  932. | MUSB_CSR0_H_REQPKT;
  933. else
  934. csr = MUSB_CSR0_H_STATUSPKT
  935. | MUSB_CSR0_TXPKTRDY;
  936. /* flag status stage */
  937. musb->ep0_stage = MUSB_EP0_STATUS;
  938. dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
  939. }
  940. musb_writew(epio, MUSB_CSR0, csr);
  941. retval = IRQ_HANDLED;
  942. } else
  943. musb->ep0_stage = MUSB_EP0_IDLE;
  944. /* call completion handler if done */
  945. if (complete)
  946. musb_advance_schedule(musb, urb, hw_ep, 1);
  947. done:
  948. return retval;
  949. }
  950. #ifdef CONFIG_USB_INVENTRA_DMA
  951. /* Host side TX (OUT) using Mentor DMA works as follows:
  952. submit_urb ->
  953. - if queue was empty, Program Endpoint
  954. - ... which starts DMA to fifo in mode 1 or 0
  955. DMA Isr (transfer complete) -> TxAvail()
  956. - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
  957. only in musb_cleanup_urb)
  958. - TxPktRdy has to be set in mode 0 or for
  959. short packets in mode 1.
  960. */
  961. #endif
  962. /* Service a Tx-Available or dma completion irq for the endpoint */
  963. void musb_host_tx(struct musb *musb, u8 epnum)
  964. {
  965. int pipe;
  966. bool done = false;
  967. u16 tx_csr;
  968. size_t length = 0;
  969. size_t offset = 0;
  970. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  971. void __iomem *epio = hw_ep->regs;
  972. struct musb_qh *qh = hw_ep->out_qh;
  973. struct urb *urb = next_urb(qh);
  974. u32 status = 0;
  975. void __iomem *mbase = musb->mregs;
  976. struct dma_channel *dma;
  977. bool transfer_pending = false;
  978. musb_ep_select(mbase, epnum);
  979. tx_csr = musb_readw(epio, MUSB_TXCSR);
  980. /* with CPPI, DMA sometimes triggers "extra" irqs */
  981. if (!urb) {
  982. dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
  983. return;
  984. }
  985. pipe = urb->pipe;
  986. dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
  987. dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
  988. dma ? ", dma" : "");
  989. /* check for errors */
  990. if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
  991. /* dma was disabled, fifo flushed */
  992. dev_dbg(musb->controller, "TX end %d stall\n", epnum);
  993. /* stall; record URB status */
  994. status = -EPIPE;
  995. } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
  996. /* (NON-ISO) dma was disabled, fifo flushed */
  997. dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
  998. status = -ETIMEDOUT;
  999. } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
  1000. dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
  1001. /* NOTE: this code path would be a good place to PAUSE a
  1002. * transfer, if there's some other (nonperiodic) tx urb
  1003. * that could use this fifo. (dma complicates it...)
  1004. * That's already done for bulk RX transfers.
  1005. *
  1006. * if (bulk && qh->ring.next != &musb->out_bulk), then
  1007. * we have a candidate... NAKing is *NOT* an error
  1008. */
  1009. musb_ep_select(mbase, epnum);
  1010. musb_writew(epio, MUSB_TXCSR,
  1011. MUSB_TXCSR_H_WZC_BITS
  1012. | MUSB_TXCSR_TXPKTRDY);
  1013. return;
  1014. }
  1015. if (status) {
  1016. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1017. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1018. (void) musb->dma_controller->channel_abort(dma);
  1019. }
  1020. /* do the proper sequence to abort the transfer in the
  1021. * usb core; the dma engine should already be stopped.
  1022. */
  1023. musb_h_tx_flush_fifo(hw_ep);
  1024. tx_csr &= ~(MUSB_TXCSR_AUTOSET
  1025. | MUSB_TXCSR_DMAENAB
  1026. | MUSB_TXCSR_H_ERROR
  1027. | MUSB_TXCSR_H_RXSTALL
  1028. | MUSB_TXCSR_H_NAKTIMEOUT
  1029. );
  1030. musb_ep_select(mbase, epnum);
  1031. musb_writew(epio, MUSB_TXCSR, tx_csr);
  1032. /* REVISIT may need to clear FLUSHFIFO ... */
  1033. musb_writew(epio, MUSB_TXCSR, tx_csr);
  1034. musb_writeb(epio, MUSB_TXINTERVAL, 0);
  1035. done = true;
  1036. }
  1037. /* second cppi case */
  1038. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1039. dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
  1040. return;
  1041. }
  1042. if (is_dma_capable() && dma && !status) {
  1043. /*
  1044. * DMA has completed. But if we're using DMA mode 1 (multi
  1045. * packet DMA), we need a terminal TXPKTRDY interrupt before
  1046. * we can consider this transfer completed, lest we trash
  1047. * its last packet when writing the next URB's data. So we
  1048. * switch back to mode 0 to get that interrupt; we'll come
  1049. * back here once it happens.
  1050. */
  1051. if (tx_csr & MUSB_TXCSR_DMAMODE) {
  1052. /*
  1053. * We shouldn't clear DMAMODE with DMAENAB set; so
  1054. * clear them in a safe order. That should be OK
  1055. * once TXPKTRDY has been set (and I've never seen
  1056. * it being 0 at this moment -- DMA interrupt latency
  1057. * is significant) but if it hasn't been then we have
  1058. * no choice but to stop being polite and ignore the
  1059. * programmer's guide... :-)
  1060. *
  1061. * Note that we must write TXCSR with TXPKTRDY cleared
  1062. * in order not to re-trigger the packet send (this bit
  1063. * can't be cleared by CPU), and there's another caveat:
  1064. * TXPKTRDY may be set shortly and then cleared in the
  1065. * double-buffered FIFO mode, so we do an extra TXCSR
  1066. * read for debouncing...
  1067. */
  1068. tx_csr &= musb_readw(epio, MUSB_TXCSR);
  1069. if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
  1070. tx_csr &= ~(MUSB_TXCSR_DMAENAB |
  1071. MUSB_TXCSR_TXPKTRDY);
  1072. musb_writew(epio, MUSB_TXCSR,
  1073. tx_csr | MUSB_TXCSR_H_WZC_BITS);
  1074. }
  1075. tx_csr &= ~(MUSB_TXCSR_DMAMODE |
  1076. MUSB_TXCSR_TXPKTRDY);
  1077. musb_writew(epio, MUSB_TXCSR,
  1078. tx_csr | MUSB_TXCSR_H_WZC_BITS);
  1079. /*
  1080. * There is no guarantee that we'll get an interrupt
  1081. * after clearing DMAMODE as we might have done this
  1082. * too late (after TXPKTRDY was cleared by controller).
  1083. * Re-read TXCSR as we have spoiled its previous value.
  1084. */
  1085. tx_csr = musb_readw(epio, MUSB_TXCSR);
  1086. }
  1087. /*
  1088. * We may get here from a DMA completion or TXPKTRDY interrupt.
  1089. * In any case, we must check the FIFO status here and bail out
  1090. * only if the FIFO still has data -- that should prevent the
  1091. * "missed" TXPKTRDY interrupts and deal with double-buffered
  1092. * FIFO mode too...
  1093. */
  1094. if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
  1095. dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
  1096. "CSR %04x\n", tx_csr);
  1097. return;
  1098. }
  1099. }
  1100. if (!status || dma || usb_pipeisoc(pipe)) {
  1101. if (dma)
  1102. length = dma->actual_len;
  1103. else
  1104. length = qh->segsize;
  1105. qh->offset += length;
  1106. if (usb_pipeisoc(pipe)) {
  1107. #ifndef __UBOOT__
  1108. struct usb_iso_packet_descriptor *d;
  1109. d = urb->iso_frame_desc + qh->iso_idx;
  1110. d->actual_length = length;
  1111. d->status = status;
  1112. if (++qh->iso_idx >= urb->number_of_packets) {
  1113. done = true;
  1114. } else {
  1115. d++;
  1116. offset = d->offset;
  1117. length = d->length;
  1118. }
  1119. #endif
  1120. } else if (dma && urb->transfer_buffer_length == qh->offset) {
  1121. done = true;
  1122. } else {
  1123. /* see if we need to send more data, or ZLP */
  1124. if (qh->segsize < qh->maxpacket)
  1125. done = true;
  1126. else if (qh->offset == urb->transfer_buffer_length
  1127. && !(urb->transfer_flags
  1128. & URB_ZERO_PACKET))
  1129. done = true;
  1130. if (!done) {
  1131. offset = qh->offset;
  1132. length = urb->transfer_buffer_length - offset;
  1133. transfer_pending = true;
  1134. }
  1135. }
  1136. }
  1137. /* urb->status != -EINPROGRESS means request has been faulted,
  1138. * so we must abort this transfer after cleanup
  1139. */
  1140. if (urb->status != -EINPROGRESS) {
  1141. done = true;
  1142. if (status == 0)
  1143. status = urb->status;
  1144. }
  1145. if (done) {
  1146. /* set status */
  1147. urb->status = status;
  1148. urb->actual_length = qh->offset;
  1149. musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
  1150. return;
  1151. } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
  1152. if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
  1153. offset, length)) {
  1154. if (is_cppi_enabled() || tusb_dma_omap())
  1155. musb_h_tx_dma_start(hw_ep);
  1156. return;
  1157. }
  1158. } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
  1159. dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
  1160. return;
  1161. }
  1162. /*
  1163. * PIO: start next packet in this URB.
  1164. *
  1165. * REVISIT: some docs say that when hw_ep->tx_double_buffered,
  1166. * (and presumably, FIFO is not half-full) we should write *two*
  1167. * packets before updating TXCSR; other docs disagree...
  1168. */
  1169. if (length > qh->maxpacket)
  1170. length = qh->maxpacket;
  1171. /* Unmap the buffer so that CPU can use it */
  1172. usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
  1173. musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
  1174. qh->segsize = length;
  1175. musb_ep_select(mbase, epnum);
  1176. musb_writew(epio, MUSB_TXCSR,
  1177. MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
  1178. }
  1179. #ifdef CONFIG_USB_INVENTRA_DMA
  1180. /* Host side RX (IN) using Mentor DMA works as follows:
  1181. submit_urb ->
  1182. - if queue was empty, ProgramEndpoint
  1183. - first IN token is sent out (by setting ReqPkt)
  1184. LinuxIsr -> RxReady()
  1185. /\ => first packet is received
  1186. | - Set in mode 0 (DmaEnab, ~ReqPkt)
  1187. | -> DMA Isr (transfer complete) -> RxReady()
  1188. | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
  1189. | - if urb not complete, send next IN token (ReqPkt)
  1190. | | else complete urb.
  1191. | |
  1192. ---------------------------
  1193. *
  1194. * Nuances of mode 1:
  1195. * For short packets, no ack (+RxPktRdy) is sent automatically
  1196. * (even if AutoClear is ON)
  1197. * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
  1198. * automatically => major problem, as collecting the next packet becomes
  1199. * difficult. Hence mode 1 is not used.
  1200. *
  1201. * REVISIT
  1202. * All we care about at this driver level is that
  1203. * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
  1204. * (b) termination conditions are: short RX, or buffer full;
  1205. * (c) fault modes include
  1206. * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
  1207. * (and that endpoint's dma queue stops immediately)
  1208. * - overflow (full, PLUS more bytes in the terminal packet)
  1209. *
  1210. * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
  1211. * thus be a great candidate for using mode 1 ... for all but the
  1212. * last packet of one URB's transfer.
  1213. */
  1214. #endif
  1215. /* Schedule next QH from musb->in_bulk and move the current qh to
  1216. * the end; avoids starvation for other endpoints.
  1217. */
  1218. static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
  1219. {
  1220. struct dma_channel *dma;
  1221. struct urb *urb;
  1222. void __iomem *mbase = musb->mregs;
  1223. void __iomem *epio = ep->regs;
  1224. struct musb_qh *cur_qh, *next_qh;
  1225. u16 rx_csr;
  1226. musb_ep_select(mbase, ep->epnum);
  1227. dma = is_dma_capable() ? ep->rx_channel : NULL;
  1228. /* clear nak timeout bit */
  1229. rx_csr = musb_readw(epio, MUSB_RXCSR);
  1230. rx_csr |= MUSB_RXCSR_H_WZC_BITS;
  1231. rx_csr &= ~MUSB_RXCSR_DATAERROR;
  1232. musb_writew(epio, MUSB_RXCSR, rx_csr);
  1233. cur_qh = first_qh(&musb->in_bulk);
  1234. if (cur_qh) {
  1235. urb = next_urb(cur_qh);
  1236. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1237. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1238. musb->dma_controller->channel_abort(dma);
  1239. urb->actual_length += dma->actual_len;
  1240. dma->actual_len = 0L;
  1241. }
  1242. musb_save_toggle(cur_qh, 1, urb);
  1243. /* move cur_qh to end of queue */
  1244. list_move_tail(&cur_qh->ring, &musb->in_bulk);
  1245. /* get the next qh from musb->in_bulk */
  1246. next_qh = first_qh(&musb->in_bulk);
  1247. /* set rx_reinit and schedule the next qh */
  1248. ep->rx_reinit = 1;
  1249. musb_start_urb(musb, 1, next_qh);
  1250. }
  1251. }
  1252. /*
  1253. * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
  1254. * and high-bandwidth IN transfer cases.
  1255. */
  1256. void musb_host_rx(struct musb *musb, u8 epnum)
  1257. {
  1258. struct urb *urb;
  1259. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  1260. void __iomem *epio = hw_ep->regs;
  1261. struct musb_qh *qh = hw_ep->in_qh;
  1262. size_t xfer_len;
  1263. void __iomem *mbase = musb->mregs;
  1264. int pipe;
  1265. u16 rx_csr, val;
  1266. bool iso_err = false;
  1267. bool done = false;
  1268. u32 status;
  1269. struct dma_channel *dma;
  1270. musb_ep_select(mbase, epnum);
  1271. urb = next_urb(qh);
  1272. dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
  1273. status = 0;
  1274. xfer_len = 0;
  1275. rx_csr = musb_readw(epio, MUSB_RXCSR);
  1276. val = rx_csr;
  1277. if (unlikely(!urb)) {
  1278. /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
  1279. * usbtest #11 (unlinks) triggers it regularly, sometimes
  1280. * with fifo full. (Only with DMA??)
  1281. */
  1282. dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
  1283. musb_readw(epio, MUSB_RXCOUNT));
  1284. musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
  1285. return;
  1286. }
  1287. pipe = urb->pipe;
  1288. dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
  1289. epnum, rx_csr, urb->actual_length,
  1290. dma ? dma->actual_len : 0);
  1291. /* check for errors, concurrent stall & unlink is not really
  1292. * handled yet! */
  1293. if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
  1294. dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
  1295. /* stall; record URB status */
  1296. status = -EPIPE;
  1297. } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
  1298. dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
  1299. status = -EPROTO;
  1300. musb_writeb(epio, MUSB_RXINTERVAL, 0);
  1301. } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
  1302. if (USB_ENDPOINT_XFER_ISOC != qh->type) {
  1303. dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
  1304. /* NOTE: NAKing is *NOT* an error, so we want to
  1305. * continue. Except ... if there's a request for
  1306. * another QH, use that instead of starving it.
  1307. *
  1308. * Devices like Ethernet and serial adapters keep
  1309. * reads posted at all times, which will starve
  1310. * other devices without this logic.
  1311. */
  1312. if (usb_pipebulk(urb->pipe)
  1313. && qh->mux == 1
  1314. && !list_is_singular(&musb->in_bulk)) {
  1315. musb_bulk_rx_nak_timeout(musb, hw_ep);
  1316. return;
  1317. }
  1318. musb_ep_select(mbase, epnum);
  1319. rx_csr |= MUSB_RXCSR_H_WZC_BITS;
  1320. rx_csr &= ~MUSB_RXCSR_DATAERROR;
  1321. musb_writew(epio, MUSB_RXCSR, rx_csr);
  1322. goto finish;
  1323. } else {
  1324. dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
  1325. /* packet error reported later */
  1326. iso_err = true;
  1327. }
  1328. } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
  1329. dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
  1330. epnum);
  1331. status = -EPROTO;
  1332. }
  1333. /* faults abort the transfer */
  1334. if (status) {
  1335. /* clean up dma and collect transfer count */
  1336. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1337. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1338. (void) musb->dma_controller->channel_abort(dma);
  1339. xfer_len = dma->actual_len;
  1340. }
  1341. musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
  1342. musb_writeb(epio, MUSB_RXINTERVAL, 0);
  1343. done = true;
  1344. goto finish;
  1345. }
  1346. if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
  1347. /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
  1348. ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
  1349. goto finish;
  1350. }
  1351. /* thorough shutdown for now ... given more precise fault handling
  1352. * and better queueing support, we might keep a DMA pipeline going
  1353. * while processing this irq for earlier completions.
  1354. */
  1355. /* FIXME this is _way_ too much in-line logic for Mentor DMA */
  1356. #ifndef CONFIG_USB_INVENTRA_DMA
  1357. if (rx_csr & MUSB_RXCSR_H_REQPKT) {
  1358. /* REVISIT this happened for a while on some short reads...
  1359. * the cleanup still needs investigation... looks bad...
  1360. * and also duplicates dma cleanup code above ... plus,
  1361. * shouldn't this be the "half full" double buffer case?
  1362. */
  1363. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1364. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1365. (void) musb->dma_controller->channel_abort(dma);
  1366. xfer_len = dma->actual_len;
  1367. done = true;
  1368. }
  1369. dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
  1370. xfer_len, dma ? ", dma" : "");
  1371. rx_csr &= ~MUSB_RXCSR_H_REQPKT;
  1372. musb_ep_select(mbase, epnum);
  1373. musb_writew(epio, MUSB_RXCSR,
  1374. MUSB_RXCSR_H_WZC_BITS | rx_csr);
  1375. }
  1376. #endif
  1377. if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
  1378. xfer_len = dma->actual_len;
  1379. val &= ~(MUSB_RXCSR_DMAENAB
  1380. | MUSB_RXCSR_H_AUTOREQ
  1381. | MUSB_RXCSR_AUTOCLEAR
  1382. | MUSB_RXCSR_RXPKTRDY);
  1383. musb_writew(hw_ep->regs, MUSB_RXCSR, val);
  1384. #ifdef CONFIG_USB_INVENTRA_DMA
  1385. if (usb_pipeisoc(pipe)) {
  1386. struct usb_iso_packet_descriptor *d;
  1387. d = urb->iso_frame_desc + qh->iso_idx;
  1388. d->actual_length = xfer_len;
  1389. /* even if there was an error, we did the dma
  1390. * for iso_frame_desc->length
  1391. */
  1392. if (d->status != -EILSEQ && d->status != -EOVERFLOW)
  1393. d->status = 0;
  1394. if (++qh->iso_idx >= urb->number_of_packets)
  1395. done = true;
  1396. else
  1397. done = false;
  1398. } else {
  1399. /* done if urb buffer is full or short packet is recd */
  1400. done = (urb->actual_length + xfer_len >=
  1401. urb->transfer_buffer_length
  1402. || dma->actual_len < qh->maxpacket);
  1403. }
  1404. /* send IN token for next packet, without AUTOREQ */
  1405. if (!done) {
  1406. val |= MUSB_RXCSR_H_REQPKT;
  1407. musb_writew(epio, MUSB_RXCSR,
  1408. MUSB_RXCSR_H_WZC_BITS | val);
  1409. }
  1410. dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
  1411. done ? "off" : "reset",
  1412. musb_readw(epio, MUSB_RXCSR),
  1413. musb_readw(epio, MUSB_RXCOUNT));
  1414. #else
  1415. done = true;
  1416. #endif
  1417. } else if (urb->status == -EINPROGRESS) {
  1418. /* if no errors, be sure a packet is ready for unloading */
  1419. if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
  1420. status = -EPROTO;
  1421. ERR("Rx interrupt with no errors or packet!\n");
  1422. /* FIXME this is another "SHOULD NEVER HAPPEN" */
  1423. /* SCRUB (RX) */
  1424. /* do the proper sequence to abort the transfer */
  1425. musb_ep_select(mbase, epnum);
  1426. val &= ~MUSB_RXCSR_H_REQPKT;
  1427. musb_writew(epio, MUSB_RXCSR, val);
  1428. goto finish;
  1429. }
  1430. /* we are expecting IN packets */
  1431. #ifdef CONFIG_USB_INVENTRA_DMA
  1432. if (dma) {
  1433. struct dma_controller *c;
  1434. u16 rx_count;
  1435. int ret, length;
  1436. dma_addr_t buf;
  1437. rx_count = musb_readw(epio, MUSB_RXCOUNT);
  1438. dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
  1439. epnum, rx_count,
  1440. urb->transfer_dma
  1441. + urb->actual_length,
  1442. qh->offset,
  1443. urb->transfer_buffer_length);
  1444. c = musb->dma_controller;
  1445. if (usb_pipeisoc(pipe)) {
  1446. int d_status = 0;
  1447. struct usb_iso_packet_descriptor *d;
  1448. d = urb->iso_frame_desc + qh->iso_idx;
  1449. if (iso_err) {
  1450. d_status = -EILSEQ;
  1451. urb->error_count++;
  1452. }
  1453. if (rx_count > d->length) {
  1454. if (d_status == 0) {
  1455. d_status = -EOVERFLOW;
  1456. urb->error_count++;
  1457. }
  1458. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
  1459. rx_count, d->length);
  1460. length = d->length;
  1461. } else
  1462. length = rx_count;
  1463. d->status = d_status;
  1464. buf = urb->transfer_dma + d->offset;
  1465. } else {
  1466. length = rx_count;
  1467. buf = urb->transfer_dma +
  1468. urb->actual_length;
  1469. }
  1470. dma->desired_mode = 0;
  1471. #ifdef USE_MODE1
  1472. /* because of the issue below, mode 1 will
  1473. * only rarely behave with correct semantics.
  1474. */
  1475. if ((urb->transfer_flags &
  1476. URB_SHORT_NOT_OK)
  1477. && (urb->transfer_buffer_length -
  1478. urb->actual_length)
  1479. > qh->maxpacket)
  1480. dma->desired_mode = 1;
  1481. if (rx_count < hw_ep->max_packet_sz_rx) {
  1482. length = rx_count;
  1483. dma->desired_mode = 0;
  1484. } else {
  1485. length = urb->transfer_buffer_length;
  1486. }
  1487. #endif
  1488. /* Disadvantage of using mode 1:
  1489. * It's basically usable only for mass storage class; essentially all
  1490. * other protocols also terminate transfers on short packets.
  1491. *
  1492. * Details:
  1493. * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
  1494. * If you try to use mode 1 for (transfer_buffer_length - 512), and try
  1495. * to use the extra IN token to grab the last packet using mode 0, then
  1496. * the problem is that you cannot be sure when the device will send the
  1497. * last packet and RxPktRdy set. Sometimes the packet is recd too soon
  1498. * such that it gets lost when RxCSR is re-set at the end of the mode 1
  1499. * transfer, while sometimes it is recd just a little late so that if you
  1500. * try to configure for mode 0 soon after the mode 1 transfer is
  1501. * completed, you will find rxcount 0. Okay, so you might think why not
  1502. * wait for an interrupt when the pkt is recd. Well, you won't get any!
  1503. */
  1504. val = musb_readw(epio, MUSB_RXCSR);
  1505. val &= ~MUSB_RXCSR_H_REQPKT;
  1506. if (dma->desired_mode == 0)
  1507. val &= ~MUSB_RXCSR_H_AUTOREQ;
  1508. else
  1509. val |= MUSB_RXCSR_H_AUTOREQ;
  1510. val |= MUSB_RXCSR_DMAENAB;
  1511. /* autoclear shouldn't be set in high bandwidth */
  1512. if (qh->hb_mult == 1)
  1513. val |= MUSB_RXCSR_AUTOCLEAR;
  1514. musb_writew(epio, MUSB_RXCSR,
  1515. MUSB_RXCSR_H_WZC_BITS | val);
  1516. /* REVISIT if when actual_length != 0,
  1517. * transfer_buffer_length needs to be
  1518. * adjusted first...
  1519. */
  1520. ret = c->channel_program(
  1521. dma, qh->maxpacket,
  1522. dma->desired_mode, buf, length);
  1523. if (!ret) {
  1524. c->channel_release(dma);
  1525. hw_ep->rx_channel = NULL;
  1526. dma = NULL;
  1527. val = musb_readw(epio, MUSB_RXCSR);
  1528. val &= ~(MUSB_RXCSR_DMAENAB
  1529. | MUSB_RXCSR_H_AUTOREQ
  1530. | MUSB_RXCSR_AUTOCLEAR);
  1531. musb_writew(epio, MUSB_RXCSR, val);
  1532. }
  1533. }
  1534. #endif /* Mentor DMA */
  1535. if (!dma) {
  1536. /* Unmap the buffer so that CPU can use it */
  1537. usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
  1538. done = musb_host_packet_rx(musb, urb,
  1539. epnum, iso_err);
  1540. dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
  1541. }
  1542. }
  1543. finish:
  1544. urb->actual_length += xfer_len;
  1545. qh->offset += xfer_len;
  1546. if (done) {
  1547. if (urb->status == -EINPROGRESS)
  1548. urb->status = status;
  1549. musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
  1550. }
  1551. }
  1552. /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
  1553. * the software schedule associates multiple such nodes with a given
  1554. * host side hardware endpoint + direction; scheduling may activate
  1555. * that hardware endpoint.
  1556. */
  1557. static int musb_schedule(
  1558. struct musb *musb,
  1559. struct musb_qh *qh,
  1560. int is_in)
  1561. {
  1562. int idle;
  1563. int best_diff;
  1564. int best_end, epnum;
  1565. struct musb_hw_ep *hw_ep = NULL;
  1566. struct list_head *head = NULL;
  1567. u8 toggle;
  1568. u8 txtype;
  1569. struct urb *urb = next_urb(qh);
  1570. /* use fixed hardware for control and bulk */
  1571. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1572. head = &musb->control;
  1573. hw_ep = musb->control_ep;
  1574. goto success;
  1575. }
  1576. /* else, periodic transfers get muxed to other endpoints */
  1577. /*
  1578. * We know this qh hasn't been scheduled, so all we need to do
  1579. * is choose which hardware endpoint to put it on ...
  1580. *
  1581. * REVISIT what we really want here is a regular schedule tree
  1582. * like e.g. OHCI uses.
  1583. */
  1584. best_diff = 4096;
  1585. best_end = -1;
  1586. for (epnum = 1, hw_ep = musb->endpoints + 1;
  1587. epnum < musb->nr_endpoints;
  1588. epnum++, hw_ep++) {
  1589. int diff;
  1590. if (musb_ep_get_qh(hw_ep, is_in) != NULL)
  1591. continue;
  1592. if (hw_ep == musb->bulk_ep)
  1593. continue;
  1594. if (is_in)
  1595. diff = hw_ep->max_packet_sz_rx;
  1596. else
  1597. diff = hw_ep->max_packet_sz_tx;
  1598. diff -= (qh->maxpacket * qh->hb_mult);
  1599. if (diff >= 0 && best_diff > diff) {
  1600. /*
  1601. * Mentor controller has a bug in that if we schedule
  1602. * a BULK Tx transfer on an endpoint that had earlier
  1603. * handled ISOC then the BULK transfer has to start on
  1604. * a zero toggle. If the BULK transfer starts on a 1
  1605. * toggle then this transfer will fail as the mentor
  1606. * controller starts the Bulk transfer on a 0 toggle
  1607. * irrespective of the programming of the toggle bits
  1608. * in the TXCSR register. Check for this condition
  1609. * while allocating the EP for a Tx Bulk transfer. If
  1610. * so skip this EP.
  1611. */
  1612. hw_ep = musb->endpoints + epnum;
  1613. toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
  1614. txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
  1615. >> 4) & 0x3;
  1616. if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
  1617. toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
  1618. continue;
  1619. best_diff = diff;
  1620. best_end = epnum;
  1621. }
  1622. }
  1623. /* use bulk reserved ep1 if no other ep is free */
  1624. if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
  1625. hw_ep = musb->bulk_ep;
  1626. if (is_in)
  1627. head = &musb->in_bulk;
  1628. else
  1629. head = &musb->out_bulk;
  1630. /* Enable bulk RX NAK timeout scheme when bulk requests are
  1631. * multiplexed. This scheme doen't work in high speed to full
  1632. * speed scenario as NAK interrupts are not coming from a
  1633. * full speed device connected to a high speed device.
  1634. * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
  1635. * 4 (8 frame or 8ms) for FS device.
  1636. */
  1637. if (is_in && qh->dev)
  1638. qh->intv_reg =
  1639. (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
  1640. goto success;
  1641. } else if (best_end < 0) {
  1642. return -ENOSPC;
  1643. }
  1644. idle = 1;
  1645. qh->mux = 0;
  1646. hw_ep = musb->endpoints + best_end;
  1647. dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
  1648. success:
  1649. if (head) {
  1650. idle = list_empty(head);
  1651. list_add_tail(&qh->ring, head);
  1652. qh->mux = 1;
  1653. }
  1654. qh->hw_ep = hw_ep;
  1655. qh->hep->hcpriv = qh;
  1656. if (idle)
  1657. musb_start_urb(musb, is_in, qh);
  1658. return 0;
  1659. }
  1660. #ifdef __UBOOT__
  1661. /* check if transaction translator is needed for device */
  1662. static int tt_needed(struct musb *musb, struct usb_device *dev)
  1663. {
  1664. if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) &&
  1665. (dev->speed < USB_SPEED_HIGH))
  1666. return 1;
  1667. return 0;
  1668. }
  1669. #endif
  1670. #ifndef __UBOOT__
  1671. static int musb_urb_enqueue(
  1672. #else
  1673. int musb_urb_enqueue(
  1674. #endif
  1675. struct usb_hcd *hcd,
  1676. struct urb *urb,
  1677. gfp_t mem_flags)
  1678. {
  1679. unsigned long flags;
  1680. struct musb *musb = hcd_to_musb(hcd);
  1681. struct usb_host_endpoint *hep = urb->ep;
  1682. struct musb_qh *qh;
  1683. struct usb_endpoint_descriptor *epd = &hep->desc;
  1684. int ret;
  1685. unsigned type_reg;
  1686. unsigned interval;
  1687. /* host role must be active */
  1688. if (!is_host_active(musb) || !musb->is_active)
  1689. return -ENODEV;
  1690. spin_lock_irqsave(&musb->lock, flags);
  1691. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  1692. qh = ret ? NULL : hep->hcpriv;
  1693. if (qh)
  1694. urb->hcpriv = qh;
  1695. spin_unlock_irqrestore(&musb->lock, flags);
  1696. /* DMA mapping was already done, if needed, and this urb is on
  1697. * hep->urb_list now ... so we're done, unless hep wasn't yet
  1698. * scheduled onto a live qh.
  1699. *
  1700. * REVISIT best to keep hep->hcpriv valid until the endpoint gets
  1701. * disabled, testing for empty qh->ring and avoiding qh setup costs
  1702. * except for the first urb queued after a config change.
  1703. */
  1704. if (qh || ret)
  1705. return ret;
  1706. /* Allocate and initialize qh, minimizing the work done each time
  1707. * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
  1708. *
  1709. * REVISIT consider a dedicated qh kmem_cache, so it's harder
  1710. * for bugs in other kernel code to break this driver...
  1711. */
  1712. qh = kzalloc(sizeof *qh, mem_flags);
  1713. if (!qh) {
  1714. spin_lock_irqsave(&musb->lock, flags);
  1715. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1716. spin_unlock_irqrestore(&musb->lock, flags);
  1717. return -ENOMEM;
  1718. }
  1719. qh->hep = hep;
  1720. qh->dev = urb->dev;
  1721. INIT_LIST_HEAD(&qh->ring);
  1722. qh->is_ready = 1;
  1723. qh->maxpacket = usb_endpoint_maxp(epd);
  1724. qh->type = usb_endpoint_type(epd);
  1725. /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
  1726. * Some musb cores don't support high bandwidth ISO transfers; and
  1727. * we don't (yet!) support high bandwidth interrupt transfers.
  1728. */
  1729. qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
  1730. if (qh->hb_mult > 1) {
  1731. int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
  1732. if (ok)
  1733. ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
  1734. || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
  1735. if (!ok) {
  1736. ret = -EMSGSIZE;
  1737. goto done;
  1738. }
  1739. qh->maxpacket &= 0x7ff;
  1740. }
  1741. qh->epnum = usb_endpoint_num(epd);
  1742. /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
  1743. qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
  1744. /* precompute rxtype/txtype/type0 register */
  1745. type_reg = (qh->type << 4) | qh->epnum;
  1746. switch (urb->dev->speed) {
  1747. case USB_SPEED_LOW:
  1748. type_reg |= 0xc0;
  1749. break;
  1750. case USB_SPEED_FULL:
  1751. type_reg |= 0x80;
  1752. break;
  1753. default:
  1754. type_reg |= 0x40;
  1755. }
  1756. qh->type_reg = type_reg;
  1757. /* Precompute RXINTERVAL/TXINTERVAL register */
  1758. switch (qh->type) {
  1759. case USB_ENDPOINT_XFER_INT:
  1760. /*
  1761. * Full/low speeds use the linear encoding,
  1762. * high speed uses the logarithmic encoding.
  1763. */
  1764. if (urb->dev->speed <= USB_SPEED_FULL) {
  1765. interval = max_t(u8, epd->bInterval, 1);
  1766. break;
  1767. }
  1768. /* FALLTHROUGH */
  1769. case USB_ENDPOINT_XFER_ISOC:
  1770. /* ISO always uses logarithmic encoding */
  1771. interval = min_t(u8, epd->bInterval, 16);
  1772. break;
  1773. default:
  1774. /* REVISIT we actually want to use NAK limits, hinting to the
  1775. * transfer scheduling logic to try some other qh, e.g. try
  1776. * for 2 msec first:
  1777. *
  1778. * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
  1779. *
  1780. * The downside of disabling this is that transfer scheduling
  1781. * gets VERY unfair for nonperiodic transfers; a misbehaving
  1782. * peripheral could make that hurt. That's perfectly normal
  1783. * for reads from network or serial adapters ... so we have
  1784. * partial NAKlimit support for bulk RX.
  1785. *
  1786. * The upside of disabling it is simpler transfer scheduling.
  1787. */
  1788. interval = 0;
  1789. }
  1790. qh->intv_reg = interval;
  1791. /* precompute addressing for external hub/tt ports */
  1792. if (musb->is_multipoint) {
  1793. #ifndef __UBOOT__
  1794. struct usb_device *parent = urb->dev->parent;
  1795. #else
  1796. struct usb_device *parent = usb_dev_get_parent(urb->dev);
  1797. #endif
  1798. #ifndef __UBOOT__
  1799. if (parent != hcd->self.root_hub) {
  1800. #else
  1801. if (parent) {
  1802. #endif
  1803. qh->h_addr_reg = (u8) parent->devnum;
  1804. #ifndef __UBOOT__
  1805. /* set up tt info if needed */
  1806. if (urb->dev->tt) {
  1807. qh->h_port_reg = (u8) urb->dev->ttport;
  1808. if (urb->dev->tt->hub)
  1809. qh->h_addr_reg =
  1810. (u8) urb->dev->tt->hub->devnum;
  1811. if (urb->dev->tt->multi)
  1812. qh->h_addr_reg |= 0x80;
  1813. }
  1814. #else
  1815. if (tt_needed(musb, urb->dev)) {
  1816. uint8_t portnr = 0;
  1817. uint8_t hubaddr = 0;
  1818. usb_find_usb2_hub_address_port(urb->dev,
  1819. &hubaddr,
  1820. &portnr);
  1821. qh->h_addr_reg = hubaddr;
  1822. qh->h_port_reg = portnr;
  1823. }
  1824. #endif
  1825. }
  1826. }
  1827. /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
  1828. * until we get real dma queues (with an entry for each urb/buffer),
  1829. * we only have work to do in the former case.
  1830. */
  1831. spin_lock_irqsave(&musb->lock, flags);
  1832. if (hep->hcpriv) {
  1833. /* some concurrent activity submitted another urb to hep...
  1834. * odd, rare, error prone, but legal.
  1835. */
  1836. kfree(qh);
  1837. qh = NULL;
  1838. ret = 0;
  1839. } else
  1840. ret = musb_schedule(musb, qh,
  1841. epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
  1842. if (ret == 0) {
  1843. urb->hcpriv = qh;
  1844. /* FIXME set urb->start_frame for iso/intr, it's tested in
  1845. * musb_start_urb(), but otherwise only konicawc cares ...
  1846. */
  1847. }
  1848. spin_unlock_irqrestore(&musb->lock, flags);
  1849. done:
  1850. if (ret != 0) {
  1851. spin_lock_irqsave(&musb->lock, flags);
  1852. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1853. spin_unlock_irqrestore(&musb->lock, flags);
  1854. kfree(qh);
  1855. }
  1856. return ret;
  1857. }
  1858. /*
  1859. * abort a transfer that's at the head of a hardware queue.
  1860. * called with controller locked, irqs blocked
  1861. * that hardware queue advances to the next transfer, unless prevented
  1862. */
  1863. static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
  1864. {
  1865. struct musb_hw_ep *ep = qh->hw_ep;
  1866. struct musb *musb = ep->musb;
  1867. void __iomem *epio = ep->regs;
  1868. unsigned hw_end = ep->epnum;
  1869. void __iomem *regs = ep->musb->mregs;
  1870. int is_in = usb_pipein(urb->pipe);
  1871. int status = 0;
  1872. u16 csr;
  1873. musb_ep_select(regs, hw_end);
  1874. if (is_dma_capable()) {
  1875. struct dma_channel *dma;
  1876. dma = is_in ? ep->rx_channel : ep->tx_channel;
  1877. if (dma) {
  1878. status = ep->musb->dma_controller->channel_abort(dma);
  1879. dev_dbg(musb->controller,
  1880. "abort %cX%d DMA for urb %p --> %d\n",
  1881. is_in ? 'R' : 'T', ep->epnum,
  1882. urb, status);
  1883. urb->actual_length += dma->actual_len;
  1884. }
  1885. }
  1886. /* turn off DMA requests, discard state, stop polling ... */
  1887. if (ep->epnum && is_in) {
  1888. /* giveback saves bulk toggle */
  1889. csr = musb_h_flush_rxfifo(ep, 0);
  1890. /* REVISIT we still get an irq; should likely clear the
  1891. * endpoint's irq status here to avoid bogus irqs.
  1892. * clearing that status is platform-specific...
  1893. */
  1894. } else if (ep->epnum) {
  1895. musb_h_tx_flush_fifo(ep);
  1896. csr = musb_readw(epio, MUSB_TXCSR);
  1897. csr &= ~(MUSB_TXCSR_AUTOSET
  1898. | MUSB_TXCSR_DMAENAB
  1899. | MUSB_TXCSR_H_RXSTALL
  1900. | MUSB_TXCSR_H_NAKTIMEOUT
  1901. | MUSB_TXCSR_H_ERROR
  1902. | MUSB_TXCSR_TXPKTRDY);
  1903. musb_writew(epio, MUSB_TXCSR, csr);
  1904. /* REVISIT may need to clear FLUSHFIFO ... */
  1905. musb_writew(epio, MUSB_TXCSR, csr);
  1906. /* flush cpu writebuffer */
  1907. csr = musb_readw(epio, MUSB_TXCSR);
  1908. } else {
  1909. musb_h_ep0_flush_fifo(ep);
  1910. }
  1911. if (status == 0)
  1912. musb_advance_schedule(ep->musb, urb, ep, is_in);
  1913. return status;
  1914. }
  1915. #ifndef __UBOOT__
  1916. static int musb_urb_dequeue(
  1917. #else
  1918. int musb_urb_dequeue(
  1919. #endif
  1920. struct usb_hcd *hcd,
  1921. struct urb *urb,
  1922. int status)
  1923. {
  1924. struct musb *musb = hcd_to_musb(hcd);
  1925. struct musb_qh *qh;
  1926. unsigned long flags;
  1927. int is_in = usb_pipein(urb->pipe);
  1928. int ret;
  1929. dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
  1930. usb_pipedevice(urb->pipe),
  1931. usb_pipeendpoint(urb->pipe),
  1932. is_in ? "in" : "out");
  1933. spin_lock_irqsave(&musb->lock, flags);
  1934. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  1935. if (ret)
  1936. goto done;
  1937. qh = urb->hcpriv;
  1938. if (!qh)
  1939. goto done;
  1940. /*
  1941. * Any URB not actively programmed into endpoint hardware can be
  1942. * immediately given back; that's any URB not at the head of an
  1943. * endpoint queue, unless someday we get real DMA queues. And even
  1944. * if it's at the head, it might not be known to the hardware...
  1945. *
  1946. * Otherwise abort current transfer, pending DMA, etc.; urb->status
  1947. * has already been updated. This is a synchronous abort; it'd be
  1948. * OK to hold off until after some IRQ, though.
  1949. *
  1950. * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
  1951. */
  1952. if (!qh->is_ready
  1953. || urb->urb_list.prev != &qh->hep->urb_list
  1954. || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
  1955. int ready = qh->is_ready;
  1956. qh->is_ready = 0;
  1957. musb_giveback(musb, urb, 0);
  1958. qh->is_ready = ready;
  1959. /* If nothing else (usually musb_giveback) is using it
  1960. * and its URB list has emptied, recycle this qh.
  1961. */
  1962. if (ready && list_empty(&qh->hep->urb_list)) {
  1963. qh->hep->hcpriv = NULL;
  1964. list_del(&qh->ring);
  1965. kfree(qh);
  1966. }
  1967. } else
  1968. ret = musb_cleanup_urb(urb, qh);
  1969. done:
  1970. spin_unlock_irqrestore(&musb->lock, flags);
  1971. return ret;
  1972. }
  1973. #ifndef __UBOOT__
  1974. /* disable an endpoint */
  1975. static void
  1976. musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
  1977. {
  1978. u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
  1979. unsigned long flags;
  1980. struct musb *musb = hcd_to_musb(hcd);
  1981. struct musb_qh *qh;
  1982. struct urb *urb;
  1983. spin_lock_irqsave(&musb->lock, flags);
  1984. qh = hep->hcpriv;
  1985. if (qh == NULL)
  1986. goto exit;
  1987. /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
  1988. /* Kick the first URB off the hardware, if needed */
  1989. qh->is_ready = 0;
  1990. if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
  1991. urb = next_urb(qh);
  1992. /* make software (then hardware) stop ASAP */
  1993. if (!urb->unlinked)
  1994. urb->status = -ESHUTDOWN;
  1995. /* cleanup */
  1996. musb_cleanup_urb(urb, qh);
  1997. /* Then nuke all the others ... and advance the
  1998. * queue on hw_ep (e.g. bulk ring) when we're done.
  1999. */
  2000. while (!list_empty(&hep->urb_list)) {
  2001. urb = next_urb(qh);
  2002. urb->status = -ESHUTDOWN;
  2003. musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
  2004. }
  2005. } else {
  2006. /* Just empty the queue; the hardware is busy with
  2007. * other transfers, and since !qh->is_ready nothing
  2008. * will activate any of these as it advances.
  2009. */
  2010. while (!list_empty(&hep->urb_list))
  2011. musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
  2012. hep->hcpriv = NULL;
  2013. list_del(&qh->ring);
  2014. kfree(qh);
  2015. }
  2016. exit:
  2017. spin_unlock_irqrestore(&musb->lock, flags);
  2018. }
  2019. static int musb_h_get_frame_number(struct usb_hcd *hcd)
  2020. {
  2021. struct musb *musb = hcd_to_musb(hcd);
  2022. return musb_readw(musb->mregs, MUSB_FRAME);
  2023. }
  2024. static int musb_h_start(struct usb_hcd *hcd)
  2025. {
  2026. struct musb *musb = hcd_to_musb(hcd);
  2027. /* NOTE: musb_start() is called when the hub driver turns
  2028. * on port power, or when (OTG) peripheral starts.
  2029. */
  2030. hcd->state = HC_STATE_RUNNING;
  2031. musb->port1_status = 0;
  2032. return 0;
  2033. }
  2034. static void musb_h_stop(struct usb_hcd *hcd)
  2035. {
  2036. musb_stop(hcd_to_musb(hcd));
  2037. hcd->state = HC_STATE_HALT;
  2038. }
  2039. static int musb_bus_suspend(struct usb_hcd *hcd)
  2040. {
  2041. struct musb *musb = hcd_to_musb(hcd);
  2042. u8 devctl;
  2043. if (!is_host_active(musb))
  2044. return 0;
  2045. switch (musb->xceiv->state) {
  2046. case OTG_STATE_A_SUSPEND:
  2047. return 0;
  2048. case OTG_STATE_A_WAIT_VRISE:
  2049. /* ID could be grounded even if there's no device
  2050. * on the other end of the cable. NOTE that the
  2051. * A_WAIT_VRISE timers are messy with MUSB...
  2052. */
  2053. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  2054. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  2055. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  2056. break;
  2057. default:
  2058. break;
  2059. }
  2060. if (musb->is_active) {
  2061. WARNING("trying to suspend as %s while active\n",
  2062. otg_state_string(musb->xceiv->state));
  2063. return -EBUSY;
  2064. } else
  2065. return 0;
  2066. }
  2067. static int musb_bus_resume(struct usb_hcd *hcd)
  2068. {
  2069. /* resuming child port does the work */
  2070. return 0;
  2071. }
  2072. const struct hc_driver musb_hc_driver = {
  2073. .description = "musb-hcd",
  2074. .product_desc = "MUSB HDRC host driver",
  2075. .hcd_priv_size = sizeof(struct musb),
  2076. .flags = HCD_USB2 | HCD_MEMORY,
  2077. /* not using irq handler or reset hooks from usbcore, since
  2078. * those must be shared with peripheral code for OTG configs
  2079. */
  2080. .start = musb_h_start,
  2081. .stop = musb_h_stop,
  2082. .get_frame_number = musb_h_get_frame_number,
  2083. .urb_enqueue = musb_urb_enqueue,
  2084. .urb_dequeue = musb_urb_dequeue,
  2085. .endpoint_disable = musb_h_disable,
  2086. .hub_status_data = musb_hub_status_data,
  2087. .hub_control = musb_hub_control,
  2088. .bus_suspend = musb_bus_suspend,
  2089. .bus_resume = musb_bus_resume,
  2090. /* .start_port_reset = NULL, */
  2091. /* .hub_irq_enable = NULL, */
  2092. };
  2093. #endif