musb_gadget.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver peripheral support
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #ifndef __UBOOT__
  11. #include <log.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/module.h>
  18. #include <linux/smp.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/delay.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/slab.h>
  23. #else
  24. #include <common.h>
  25. #include <linux/bug.h>
  26. #include <linux/usb/ch9.h>
  27. #include "linux-compat.h"
  28. #endif
  29. #include "musb_core.h"
  30. /* MUSB PERIPHERAL status 3-mar-2006:
  31. *
  32. * - EP0 seems solid. It passes both USBCV and usbtest control cases.
  33. * Minor glitches:
  34. *
  35. * + remote wakeup to Linux hosts work, but saw USBCV failures;
  36. * in one test run (operator error?)
  37. * + endpoint halt tests -- in both usbtest and usbcv -- seem
  38. * to break when dma is enabled ... is something wrongly
  39. * clearing SENDSTALL?
  40. *
  41. * - Mass storage behaved ok when last tested. Network traffic patterns
  42. * (with lots of short transfers etc) need retesting; they turn up the
  43. * worst cases of the DMA, since short packets are typical but are not
  44. * required.
  45. *
  46. * - TX/IN
  47. * + both pio and dma behave in with network and g_zero tests
  48. * + no cppi throughput issues other than no-hw-queueing
  49. * + failed with FLAT_REG (DaVinci)
  50. * + seems to behave with double buffering, PIO -and- CPPI
  51. * + with gadgetfs + AIO, requests got lost?
  52. *
  53. * - RX/OUT
  54. * + both pio and dma behave in with network and g_zero tests
  55. * + dma is slow in typical case (short_not_ok is clear)
  56. * + double buffering ok with PIO
  57. * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
  58. * + request lossage observed with gadgetfs
  59. *
  60. * - ISO not tested ... might work, but only weakly isochronous
  61. *
  62. * - Gadget driver disabling of softconnect during bind() is ignored; so
  63. * drivers can't hold off host requests until userspace is ready.
  64. * (Workaround: they can turn it off later.)
  65. *
  66. * - PORTABILITY (assumes PIO works):
  67. * + DaVinci, basically works with cppi dma
  68. * + OMAP 2430, ditto with mentor dma
  69. * + TUSB 6010, platform-specific dma in the works
  70. */
  71. /* ----------------------------------------------------------------------- */
  72. #define is_buffer_mapped(req) (is_dma_capable() && \
  73. (req->map_state != UN_MAPPED))
  74. #ifndef CONFIG_USB_MUSB_PIO_ONLY
  75. /* Maps the buffer to dma */
  76. static inline void map_dma_buffer(struct musb_request *request,
  77. struct musb *musb, struct musb_ep *musb_ep)
  78. {
  79. int compatible = true;
  80. struct dma_controller *dma = musb->dma_controller;
  81. request->map_state = UN_MAPPED;
  82. if (!is_dma_capable() || !musb_ep->dma)
  83. return;
  84. /* Check if DMA engine can handle this request.
  85. * DMA code must reject the USB request explicitly.
  86. * Default behaviour is to map the request.
  87. */
  88. if (dma->is_compatible)
  89. compatible = dma->is_compatible(musb_ep->dma,
  90. musb_ep->packet_sz, request->request.buf,
  91. request->request.length);
  92. if (!compatible)
  93. return;
  94. if (request->request.dma == DMA_ADDR_INVALID) {
  95. request->request.dma = dma_map_single(
  96. musb->controller,
  97. request->request.buf,
  98. request->request.length,
  99. request->tx
  100. ? DMA_TO_DEVICE
  101. : DMA_FROM_DEVICE);
  102. request->map_state = MUSB_MAPPED;
  103. } else {
  104. dma_sync_single_for_device(musb->controller,
  105. request->request.dma,
  106. request->request.length,
  107. request->tx
  108. ? DMA_TO_DEVICE
  109. : DMA_FROM_DEVICE);
  110. request->map_state = PRE_MAPPED;
  111. }
  112. }
  113. /* Unmap the buffer from dma and maps it back to cpu */
  114. static inline void unmap_dma_buffer(struct musb_request *request,
  115. struct musb *musb)
  116. {
  117. if (!is_buffer_mapped(request))
  118. return;
  119. if (request->request.dma == DMA_ADDR_INVALID) {
  120. dev_vdbg(musb->controller,
  121. "not unmapping a never mapped buffer\n");
  122. return;
  123. }
  124. if (request->map_state == MUSB_MAPPED) {
  125. dma_unmap_single(musb->controller,
  126. request->request.dma,
  127. request->request.length,
  128. request->tx
  129. ? DMA_TO_DEVICE
  130. : DMA_FROM_DEVICE);
  131. request->request.dma = DMA_ADDR_INVALID;
  132. } else { /* PRE_MAPPED */
  133. dma_sync_single_for_cpu(musb->controller,
  134. request->request.dma,
  135. request->request.length,
  136. request->tx
  137. ? DMA_TO_DEVICE
  138. : DMA_FROM_DEVICE);
  139. }
  140. request->map_state = UN_MAPPED;
  141. }
  142. #else
  143. static inline void map_dma_buffer(struct musb_request *request,
  144. struct musb *musb, struct musb_ep *musb_ep)
  145. {
  146. }
  147. static inline void unmap_dma_buffer(struct musb_request *request,
  148. struct musb *musb)
  149. {
  150. }
  151. #endif
  152. /*
  153. * Immediately complete a request.
  154. *
  155. * @param request the request to complete
  156. * @param status the status to complete the request with
  157. * Context: controller locked, IRQs blocked.
  158. */
  159. void musb_g_giveback(
  160. struct musb_ep *ep,
  161. struct usb_request *request,
  162. int status)
  163. __releases(ep->musb->lock)
  164. __acquires(ep->musb->lock)
  165. {
  166. struct musb_request *req;
  167. struct musb *musb;
  168. int busy = ep->busy;
  169. req = to_musb_request(request);
  170. list_del(&req->list);
  171. if (req->request.status == -EINPROGRESS)
  172. req->request.status = status;
  173. musb = req->musb;
  174. ep->busy = 1;
  175. spin_unlock(&musb->lock);
  176. unmap_dma_buffer(req, musb);
  177. if (request->status == 0)
  178. dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
  179. ep->end_point.name, request,
  180. req->request.actual, req->request.length);
  181. else
  182. dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
  183. ep->end_point.name, request,
  184. req->request.actual, req->request.length,
  185. request->status);
  186. req->request.complete(&req->ep->end_point, &req->request);
  187. spin_lock(&musb->lock);
  188. ep->busy = busy;
  189. }
  190. /* ----------------------------------------------------------------------- */
  191. /*
  192. * Abort requests queued to an endpoint using the status. Synchronous.
  193. * caller locked controller and blocked irqs, and selected this ep.
  194. */
  195. static void nuke(struct musb_ep *ep, const int status)
  196. {
  197. struct musb *musb = ep->musb;
  198. struct musb_request *req = NULL;
  199. void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
  200. ep->busy = 1;
  201. if (is_dma_capable() && ep->dma) {
  202. struct dma_controller *c = ep->musb->dma_controller;
  203. int value;
  204. if (ep->is_in) {
  205. /*
  206. * The programming guide says that we must not clear
  207. * the DMAMODE bit before DMAENAB, so we only
  208. * clear it in the second write...
  209. */
  210. musb_writew(epio, MUSB_TXCSR,
  211. MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
  212. musb_writew(epio, MUSB_TXCSR,
  213. 0 | MUSB_TXCSR_FLUSHFIFO);
  214. } else {
  215. musb_writew(epio, MUSB_RXCSR,
  216. 0 | MUSB_RXCSR_FLUSHFIFO);
  217. musb_writew(epio, MUSB_RXCSR,
  218. 0 | MUSB_RXCSR_FLUSHFIFO);
  219. }
  220. value = c->channel_abort(ep->dma);
  221. dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
  222. ep->name, value);
  223. c->channel_release(ep->dma);
  224. ep->dma = NULL;
  225. }
  226. while (!list_empty(&ep->req_list)) {
  227. req = list_first_entry(&ep->req_list, struct musb_request, list);
  228. musb_g_giveback(ep, &req->request, status);
  229. }
  230. }
  231. /* ----------------------------------------------------------------------- */
  232. /* Data transfers - pure PIO, pure DMA, or mixed mode */
  233. /*
  234. * This assumes the separate CPPI engine is responding to DMA requests
  235. * from the usb core ... sequenced a bit differently from mentor dma.
  236. */
  237. static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
  238. {
  239. if (can_bulk_split(musb, ep->type))
  240. return ep->hw_ep->max_packet_sz_tx;
  241. else
  242. return ep->packet_sz;
  243. }
  244. #ifdef CONFIG_USB_INVENTRA_DMA
  245. /* Peripheral tx (IN) using Mentor DMA works as follows:
  246. Only mode 0 is used for transfers <= wPktSize,
  247. mode 1 is used for larger transfers,
  248. One of the following happens:
  249. - Host sends IN token which causes an endpoint interrupt
  250. -> TxAvail
  251. -> if DMA is currently busy, exit.
  252. -> if queue is non-empty, txstate().
  253. - Request is queued by the gadget driver.
  254. -> if queue was previously empty, txstate()
  255. txstate()
  256. -> start
  257. /\ -> setup DMA
  258. | (data is transferred to the FIFO, then sent out when
  259. | IN token(s) are recd from Host.
  260. | -> DMA interrupt on completion
  261. | calls TxAvail.
  262. | -> stop DMA, ~DMAENAB,
  263. | -> set TxPktRdy for last short pkt or zlp
  264. | -> Complete Request
  265. | -> Continue next request (call txstate)
  266. |___________________________________|
  267. * Non-Mentor DMA engines can of course work differently, such as by
  268. * upleveling from irq-per-packet to irq-per-buffer.
  269. */
  270. #endif
  271. /*
  272. * An endpoint is transmitting data. This can be called either from
  273. * the IRQ routine or from ep.queue() to kickstart a request on an
  274. * endpoint.
  275. *
  276. * Context: controller locked, IRQs blocked, endpoint selected
  277. */
  278. static void txstate(struct musb *musb, struct musb_request *req)
  279. {
  280. u8 epnum = req->epnum;
  281. struct musb_ep *musb_ep;
  282. void __iomem *epio = musb->endpoints[epnum].regs;
  283. struct usb_request *request;
  284. u16 fifo_count = 0, csr;
  285. int use_dma = 0;
  286. musb_ep = req->ep;
  287. /* Check if EP is disabled */
  288. if (!musb_ep->desc) {
  289. dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
  290. musb_ep->end_point.name);
  291. return;
  292. }
  293. /* we shouldn't get here while DMA is active ... but we do ... */
  294. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  295. dev_dbg(musb->controller, "dma pending...\n");
  296. return;
  297. }
  298. /* read TXCSR before */
  299. csr = musb_readw(epio, MUSB_TXCSR);
  300. request = &req->request;
  301. fifo_count = min(max_ep_writesize(musb, musb_ep),
  302. (int)(request->length - request->actual));
  303. if (csr & MUSB_TXCSR_TXPKTRDY) {
  304. dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
  305. musb_ep->end_point.name, csr);
  306. return;
  307. }
  308. if (csr & MUSB_TXCSR_P_SENDSTALL) {
  309. dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
  310. musb_ep->end_point.name, csr);
  311. return;
  312. }
  313. dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
  314. epnum, musb_ep->packet_sz, fifo_count,
  315. csr);
  316. #ifndef CONFIG_USB_MUSB_PIO_ONLY
  317. if (is_buffer_mapped(req)) {
  318. struct dma_controller *c = musb->dma_controller;
  319. size_t request_size;
  320. /* setup DMA, then program endpoint CSR */
  321. request_size = min_t(size_t, request->length - request->actual,
  322. musb_ep->dma->max_len);
  323. use_dma = (request->dma != DMA_ADDR_INVALID);
  324. /* MUSB_TXCSR_P_ISO is still set correctly */
  325. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
  326. {
  327. if (request_size < musb_ep->packet_sz)
  328. musb_ep->dma->desired_mode = 0;
  329. else
  330. musb_ep->dma->desired_mode = 1;
  331. use_dma = use_dma && c->channel_program(
  332. musb_ep->dma, musb_ep->packet_sz,
  333. musb_ep->dma->desired_mode,
  334. request->dma + request->actual, request_size);
  335. if (use_dma) {
  336. if (musb_ep->dma->desired_mode == 0) {
  337. /*
  338. * We must not clear the DMAMODE bit
  339. * before the DMAENAB bit -- and the
  340. * latter doesn't always get cleared
  341. * before we get here...
  342. */
  343. csr &= ~(MUSB_TXCSR_AUTOSET
  344. | MUSB_TXCSR_DMAENAB);
  345. musb_writew(epio, MUSB_TXCSR, csr
  346. | MUSB_TXCSR_P_WZC_BITS);
  347. csr &= ~MUSB_TXCSR_DMAMODE;
  348. csr |= (MUSB_TXCSR_DMAENAB |
  349. MUSB_TXCSR_MODE);
  350. /* against programming guide */
  351. } else {
  352. csr |= (MUSB_TXCSR_DMAENAB
  353. | MUSB_TXCSR_DMAMODE
  354. | MUSB_TXCSR_MODE);
  355. if (!musb_ep->hb_mult)
  356. csr |= MUSB_TXCSR_AUTOSET;
  357. }
  358. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  359. musb_writew(epio, MUSB_TXCSR, csr);
  360. }
  361. }
  362. #elif defined(CONFIG_USB_TI_CPPI_DMA)
  363. /* program endpoint CSR first, then setup DMA */
  364. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  365. csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
  366. MUSB_TXCSR_MODE;
  367. musb_writew(epio, MUSB_TXCSR,
  368. (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
  369. | csr);
  370. /* ensure writebuffer is empty */
  371. csr = musb_readw(epio, MUSB_TXCSR);
  372. /* NOTE host side sets DMAENAB later than this; both are
  373. * OK since the transfer dma glue (between CPPI and Mentor
  374. * fifos) just tells CPPI it could start. Data only moves
  375. * to the USB TX fifo when both fifos are ready.
  376. */
  377. /* "mode" is irrelevant here; handle terminating ZLPs like
  378. * PIO does, since the hardware RNDIS mode seems unreliable
  379. * except for the last-packet-is-already-short case.
  380. */
  381. use_dma = use_dma && c->channel_program(
  382. musb_ep->dma, musb_ep->packet_sz,
  383. 0,
  384. request->dma + request->actual,
  385. request_size);
  386. if (!use_dma) {
  387. c->channel_release(musb_ep->dma);
  388. musb_ep->dma = NULL;
  389. csr &= ~MUSB_TXCSR_DMAENAB;
  390. musb_writew(epio, MUSB_TXCSR, csr);
  391. /* invariant: prequest->buf is non-null */
  392. }
  393. #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
  394. use_dma = use_dma && c->channel_program(
  395. musb_ep->dma, musb_ep->packet_sz,
  396. request->zero,
  397. request->dma + request->actual,
  398. request_size);
  399. #endif
  400. }
  401. #endif
  402. if (!use_dma) {
  403. /*
  404. * Unmap the dma buffer back to cpu if dma channel
  405. * programming fails
  406. */
  407. unmap_dma_buffer(req, musb);
  408. musb_write_fifo(musb_ep->hw_ep, fifo_count,
  409. (u8 *) (request->buf + request->actual));
  410. request->actual += fifo_count;
  411. csr |= MUSB_TXCSR_TXPKTRDY;
  412. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  413. musb_writew(epio, MUSB_TXCSR, csr);
  414. }
  415. /* host may already have the data when this message shows... */
  416. dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
  417. musb_ep->end_point.name, use_dma ? "dma" : "pio",
  418. request->actual, request->length,
  419. musb_readw(epio, MUSB_TXCSR),
  420. fifo_count,
  421. musb_readw(epio, MUSB_TXMAXP));
  422. }
  423. /*
  424. * FIFO state update (e.g. data ready).
  425. * Called from IRQ, with controller locked.
  426. */
  427. void musb_g_tx(struct musb *musb, u8 epnum)
  428. {
  429. u16 csr;
  430. struct musb_request *req;
  431. struct usb_request *request;
  432. u8 __iomem *mbase = musb->mregs;
  433. struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
  434. void __iomem *epio = musb->endpoints[epnum].regs;
  435. struct dma_channel *dma;
  436. musb_ep_select(mbase, epnum);
  437. req = next_request(musb_ep);
  438. request = &req->request;
  439. csr = musb_readw(epio, MUSB_TXCSR);
  440. dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
  441. dma = is_dma_capable() ? musb_ep->dma : NULL;
  442. /*
  443. * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
  444. * probably rates reporting as a host error.
  445. */
  446. if (csr & MUSB_TXCSR_P_SENTSTALL) {
  447. csr |= MUSB_TXCSR_P_WZC_BITS;
  448. csr &= ~MUSB_TXCSR_P_SENTSTALL;
  449. musb_writew(epio, MUSB_TXCSR, csr);
  450. return;
  451. }
  452. if (csr & MUSB_TXCSR_P_UNDERRUN) {
  453. /* We NAKed, no big deal... little reason to care. */
  454. csr |= MUSB_TXCSR_P_WZC_BITS;
  455. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  456. musb_writew(epio, MUSB_TXCSR, csr);
  457. dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
  458. epnum, request);
  459. }
  460. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  461. /*
  462. * SHOULD NOT HAPPEN... has with CPPI though, after
  463. * changing SENDSTALL (and other cases); harmless?
  464. */
  465. dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
  466. return;
  467. }
  468. if (request) {
  469. u8 is_dma = 0;
  470. if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
  471. is_dma = 1;
  472. csr |= MUSB_TXCSR_P_WZC_BITS;
  473. csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
  474. MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
  475. musb_writew(epio, MUSB_TXCSR, csr);
  476. /* Ensure writebuffer is empty. */
  477. csr = musb_readw(epio, MUSB_TXCSR);
  478. request->actual += musb_ep->dma->actual_len;
  479. dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
  480. epnum, csr, musb_ep->dma->actual_len, request);
  481. }
  482. /*
  483. * First, maybe a terminating short packet. Some DMA
  484. * engines might handle this by themselves.
  485. */
  486. if ((request->zero && request->length
  487. && (request->length % musb_ep->packet_sz == 0)
  488. && (request->actual == request->length))
  489. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
  490. || (is_dma && (!dma->desired_mode ||
  491. (request->actual &
  492. (musb_ep->packet_sz - 1))))
  493. #endif
  494. ) {
  495. /*
  496. * On DMA completion, FIFO may not be
  497. * available yet...
  498. */
  499. if (csr & MUSB_TXCSR_TXPKTRDY)
  500. return;
  501. dev_dbg(musb->controller, "sending zero pkt\n");
  502. musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
  503. | MUSB_TXCSR_TXPKTRDY);
  504. request->zero = 0;
  505. }
  506. if (request->actual == request->length) {
  507. musb_g_giveback(musb_ep, request, 0);
  508. /*
  509. * In the giveback function the MUSB lock is
  510. * released and acquired after sometime. During
  511. * this time period the INDEX register could get
  512. * changed by the gadget_queue function especially
  513. * on SMP systems. Reselect the INDEX to be sure
  514. * we are reading/modifying the right registers
  515. */
  516. musb_ep_select(mbase, epnum);
  517. req = musb_ep->desc ? next_request(musb_ep) : NULL;
  518. if (!req) {
  519. dev_dbg(musb->controller, "%s idle now\n",
  520. musb_ep->end_point.name);
  521. return;
  522. }
  523. }
  524. txstate(musb, req);
  525. }
  526. }
  527. /* ------------------------------------------------------------ */
  528. #ifdef CONFIG_USB_INVENTRA_DMA
  529. /* Peripheral rx (OUT) using Mentor DMA works as follows:
  530. - Only mode 0 is used.
  531. - Request is queued by the gadget class driver.
  532. -> if queue was previously empty, rxstate()
  533. - Host sends OUT token which causes an endpoint interrupt
  534. /\ -> RxReady
  535. | -> if request queued, call rxstate
  536. | /\ -> setup DMA
  537. | | -> DMA interrupt on completion
  538. | | -> RxReady
  539. | | -> stop DMA
  540. | | -> ack the read
  541. | | -> if data recd = max expected
  542. | | by the request, or host
  543. | | sent a short packet,
  544. | | complete the request,
  545. | | and start the next one.
  546. | |_____________________________________|
  547. | else just wait for the host
  548. | to send the next OUT token.
  549. |__________________________________________________|
  550. * Non-Mentor DMA engines can of course work differently.
  551. */
  552. #endif
  553. /*
  554. * Context: controller locked, IRQs blocked, endpoint selected
  555. */
  556. static void rxstate(struct musb *musb, struct musb_request *req)
  557. {
  558. const u8 epnum = req->epnum;
  559. struct usb_request *request = &req->request;
  560. struct musb_ep *musb_ep;
  561. void __iomem *epio = musb->endpoints[epnum].regs;
  562. unsigned fifo_count = 0;
  563. u16 len;
  564. u16 csr = musb_readw(epio, MUSB_RXCSR);
  565. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  566. u8 use_mode_1;
  567. if (hw_ep->is_shared_fifo)
  568. musb_ep = &hw_ep->ep_in;
  569. else
  570. musb_ep = &hw_ep->ep_out;
  571. len = musb_ep->packet_sz;
  572. /* Check if EP is disabled */
  573. if (!musb_ep->desc) {
  574. dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
  575. musb_ep->end_point.name);
  576. return;
  577. }
  578. /* We shouldn't get here while DMA is active, but we do... */
  579. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  580. dev_dbg(musb->controller, "DMA pending...\n");
  581. return;
  582. }
  583. if (csr & MUSB_RXCSR_P_SENDSTALL) {
  584. dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
  585. musb_ep->end_point.name, csr);
  586. return;
  587. }
  588. if (is_cppi_enabled() && is_buffer_mapped(req)) {
  589. struct dma_controller *c = musb->dma_controller;
  590. struct dma_channel *channel = musb_ep->dma;
  591. /* NOTE: CPPI won't actually stop advancing the DMA
  592. * queue after short packet transfers, so this is almost
  593. * always going to run as IRQ-per-packet DMA so that
  594. * faults will be handled correctly.
  595. */
  596. if (c->channel_program(channel,
  597. musb_ep->packet_sz,
  598. !request->short_not_ok,
  599. request->dma + request->actual,
  600. request->length - request->actual)) {
  601. /* make sure that if an rxpkt arrived after the irq,
  602. * the cppi engine will be ready to take it as soon
  603. * as DMA is enabled
  604. */
  605. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  606. | MUSB_RXCSR_DMAMODE);
  607. csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
  608. musb_writew(epio, MUSB_RXCSR, csr);
  609. return;
  610. }
  611. }
  612. if (csr & MUSB_RXCSR_RXPKTRDY) {
  613. len = musb_readw(epio, MUSB_RXCOUNT);
  614. /*
  615. * Enable Mode 1 on RX transfers only when short_not_ok flag
  616. * is set. Currently short_not_ok flag is set only from
  617. * file_storage and f_mass_storage drivers
  618. */
  619. if (request->short_not_ok && len == musb_ep->packet_sz)
  620. use_mode_1 = 1;
  621. else
  622. use_mode_1 = 0;
  623. if (request->actual < request->length) {
  624. #ifdef CONFIG_USB_INVENTRA_DMA
  625. if (is_buffer_mapped(req)) {
  626. struct dma_controller *c;
  627. struct dma_channel *channel;
  628. int use_dma = 0;
  629. c = musb->dma_controller;
  630. channel = musb_ep->dma;
  631. /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
  632. * mode 0 only. So we do not get endpoint interrupts due to DMA
  633. * completion. We only get interrupts from DMA controller.
  634. *
  635. * We could operate in DMA mode 1 if we knew the size of the tranfer
  636. * in advance. For mass storage class, request->length = what the host
  637. * sends, so that'd work. But for pretty much everything else,
  638. * request->length is routinely more than what the host sends. For
  639. * most these gadgets, end of is signified either by a short packet,
  640. * or filling the last byte of the buffer. (Sending extra data in
  641. * that last pckate should trigger an overflow fault.) But in mode 1,
  642. * we don't get DMA completion interrupt for short packets.
  643. *
  644. * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
  645. * to get endpoint interrupt on every DMA req, but that didn't seem
  646. * to work reliably.
  647. *
  648. * REVISIT an updated g_file_storage can set req->short_not_ok, which
  649. * then becomes usable as a runtime "use mode 1" hint...
  650. */
  651. /* Experimental: Mode1 works with mass storage use cases */
  652. if (use_mode_1) {
  653. csr |= MUSB_RXCSR_AUTOCLEAR;
  654. musb_writew(epio, MUSB_RXCSR, csr);
  655. csr |= MUSB_RXCSR_DMAENAB;
  656. musb_writew(epio, MUSB_RXCSR, csr);
  657. /*
  658. * this special sequence (enabling and then
  659. * disabling MUSB_RXCSR_DMAMODE) is required
  660. * to get DMAReq to activate
  661. */
  662. musb_writew(epio, MUSB_RXCSR,
  663. csr | MUSB_RXCSR_DMAMODE);
  664. musb_writew(epio, MUSB_RXCSR, csr);
  665. } else {
  666. if (!musb_ep->hb_mult &&
  667. musb_ep->hw_ep->rx_double_buffered)
  668. csr |= MUSB_RXCSR_AUTOCLEAR;
  669. csr |= MUSB_RXCSR_DMAENAB;
  670. musb_writew(epio, MUSB_RXCSR, csr);
  671. }
  672. if (request->actual < request->length) {
  673. int transfer_size = 0;
  674. if (use_mode_1) {
  675. transfer_size = min(request->length - request->actual,
  676. channel->max_len);
  677. musb_ep->dma->desired_mode = 1;
  678. } else {
  679. transfer_size = min(request->length - request->actual,
  680. (unsigned)len);
  681. musb_ep->dma->desired_mode = 0;
  682. }
  683. use_dma = c->channel_program(
  684. channel,
  685. musb_ep->packet_sz,
  686. channel->desired_mode,
  687. request->dma
  688. + request->actual,
  689. transfer_size);
  690. }
  691. if (use_dma)
  692. return;
  693. }
  694. #elif defined(CONFIG_USB_UX500_DMA)
  695. if ((is_buffer_mapped(req)) &&
  696. (request->actual < request->length)) {
  697. struct dma_controller *c;
  698. struct dma_channel *channel;
  699. int transfer_size = 0;
  700. c = musb->dma_controller;
  701. channel = musb_ep->dma;
  702. /* In case first packet is short */
  703. if (len < musb_ep->packet_sz)
  704. transfer_size = len;
  705. else if (request->short_not_ok)
  706. transfer_size = min(request->length -
  707. request->actual,
  708. channel->max_len);
  709. else
  710. transfer_size = min(request->length -
  711. request->actual,
  712. (unsigned)len);
  713. csr &= ~MUSB_RXCSR_DMAMODE;
  714. csr |= (MUSB_RXCSR_DMAENAB |
  715. MUSB_RXCSR_AUTOCLEAR);
  716. musb_writew(epio, MUSB_RXCSR, csr);
  717. if (transfer_size <= musb_ep->packet_sz) {
  718. musb_ep->dma->desired_mode = 0;
  719. } else {
  720. musb_ep->dma->desired_mode = 1;
  721. /* Mode must be set after DMAENAB */
  722. csr |= MUSB_RXCSR_DMAMODE;
  723. musb_writew(epio, MUSB_RXCSR, csr);
  724. }
  725. if (c->channel_program(channel,
  726. musb_ep->packet_sz,
  727. channel->desired_mode,
  728. request->dma
  729. + request->actual,
  730. transfer_size))
  731. return;
  732. }
  733. #endif /* Mentor's DMA */
  734. fifo_count = request->length - request->actual;
  735. dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
  736. musb_ep->end_point.name,
  737. len, fifo_count,
  738. musb_ep->packet_sz);
  739. fifo_count = min_t(unsigned, len, fifo_count);
  740. #ifdef CONFIG_USB_TUSB_OMAP_DMA
  741. if (tusb_dma_omap() && is_buffer_mapped(req)) {
  742. struct dma_controller *c = musb->dma_controller;
  743. struct dma_channel *channel = musb_ep->dma;
  744. u32 dma_addr = request->dma + request->actual;
  745. int ret;
  746. ret = c->channel_program(channel,
  747. musb_ep->packet_sz,
  748. channel->desired_mode,
  749. dma_addr,
  750. fifo_count);
  751. if (ret)
  752. return;
  753. }
  754. #endif
  755. /*
  756. * Unmap the dma buffer back to cpu if dma channel
  757. * programming fails. This buffer is mapped if the
  758. * channel allocation is successful
  759. */
  760. if (is_buffer_mapped(req)) {
  761. unmap_dma_buffer(req, musb);
  762. /*
  763. * Clear DMAENAB and AUTOCLEAR for the
  764. * PIO mode transfer
  765. */
  766. csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
  767. musb_writew(epio, MUSB_RXCSR, csr);
  768. }
  769. musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
  770. (request->buf + request->actual));
  771. request->actual += fifo_count;
  772. /* REVISIT if we left anything in the fifo, flush
  773. * it and report -EOVERFLOW
  774. */
  775. /* ack the read! */
  776. csr |= MUSB_RXCSR_P_WZC_BITS;
  777. csr &= ~MUSB_RXCSR_RXPKTRDY;
  778. musb_writew(epio, MUSB_RXCSR, csr);
  779. }
  780. }
  781. /* reach the end or short packet detected */
  782. if (request->actual == request->length || len < musb_ep->packet_sz)
  783. musb_g_giveback(musb_ep, request, 0);
  784. }
  785. /*
  786. * Data ready for a request; called from IRQ
  787. */
  788. void musb_g_rx(struct musb *musb, u8 epnum)
  789. {
  790. u16 csr;
  791. struct musb_request *req;
  792. struct usb_request *request;
  793. void __iomem *mbase = musb->mregs;
  794. struct musb_ep *musb_ep;
  795. void __iomem *epio = musb->endpoints[epnum].regs;
  796. struct dma_channel *dma;
  797. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  798. if (hw_ep->is_shared_fifo)
  799. musb_ep = &hw_ep->ep_in;
  800. else
  801. musb_ep = &hw_ep->ep_out;
  802. musb_ep_select(mbase, epnum);
  803. req = next_request(musb_ep);
  804. if (!req)
  805. return;
  806. request = &req->request;
  807. csr = musb_readw(epio, MUSB_RXCSR);
  808. dma = is_dma_capable() ? musb_ep->dma : NULL;
  809. dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
  810. csr, dma ? " (dma)" : "", request);
  811. if (csr & MUSB_RXCSR_P_SENTSTALL) {
  812. csr |= MUSB_RXCSR_P_WZC_BITS;
  813. csr &= ~MUSB_RXCSR_P_SENTSTALL;
  814. musb_writew(epio, MUSB_RXCSR, csr);
  815. return;
  816. }
  817. if (csr & MUSB_RXCSR_P_OVERRUN) {
  818. /* csr |= MUSB_RXCSR_P_WZC_BITS; */
  819. csr &= ~MUSB_RXCSR_P_OVERRUN;
  820. musb_writew(epio, MUSB_RXCSR, csr);
  821. dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
  822. if (request->status == -EINPROGRESS)
  823. request->status = -EOVERFLOW;
  824. }
  825. if (csr & MUSB_RXCSR_INCOMPRX) {
  826. /* REVISIT not necessarily an error */
  827. dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
  828. }
  829. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  830. /* "should not happen"; likely RXPKTRDY pending for DMA */
  831. dev_dbg(musb->controller, "%s busy, csr %04x\n",
  832. musb_ep->end_point.name, csr);
  833. return;
  834. }
  835. if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
  836. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  837. | MUSB_RXCSR_DMAENAB
  838. | MUSB_RXCSR_DMAMODE);
  839. musb_writew(epio, MUSB_RXCSR,
  840. MUSB_RXCSR_P_WZC_BITS | csr);
  841. request->actual += musb_ep->dma->actual_len;
  842. dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
  843. epnum, csr,
  844. musb_readw(epio, MUSB_RXCSR),
  845. musb_ep->dma->actual_len, request);
  846. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  847. defined(CONFIG_USB_UX500_DMA)
  848. /* Autoclear doesn't clear RxPktRdy for short packets */
  849. if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
  850. || (dma->actual_len
  851. & (musb_ep->packet_sz - 1))) {
  852. /* ack the read! */
  853. csr &= ~MUSB_RXCSR_RXPKTRDY;
  854. musb_writew(epio, MUSB_RXCSR, csr);
  855. }
  856. /* incomplete, and not short? wait for next IN packet */
  857. if ((request->actual < request->length)
  858. && (musb_ep->dma->actual_len
  859. == musb_ep->packet_sz)) {
  860. /* In double buffer case, continue to unload fifo if
  861. * there is Rx packet in FIFO.
  862. **/
  863. csr = musb_readw(epio, MUSB_RXCSR);
  864. if ((csr & MUSB_RXCSR_RXPKTRDY) &&
  865. hw_ep->rx_double_buffered)
  866. goto exit;
  867. return;
  868. }
  869. #endif
  870. musb_g_giveback(musb_ep, request, 0);
  871. /*
  872. * In the giveback function the MUSB lock is
  873. * released and acquired after sometime. During
  874. * this time period the INDEX register could get
  875. * changed by the gadget_queue function especially
  876. * on SMP systems. Reselect the INDEX to be sure
  877. * we are reading/modifying the right registers
  878. */
  879. musb_ep_select(mbase, epnum);
  880. req = next_request(musb_ep);
  881. if (!req)
  882. return;
  883. }
  884. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  885. defined(CONFIG_USB_UX500_DMA)
  886. exit:
  887. #endif
  888. /* Analyze request */
  889. rxstate(musb, req);
  890. }
  891. /* ------------------------------------------------------------ */
  892. static int musb_gadget_enable(struct usb_ep *ep,
  893. const struct usb_endpoint_descriptor *desc)
  894. {
  895. unsigned long flags;
  896. struct musb_ep *musb_ep;
  897. struct musb_hw_ep *hw_ep;
  898. void __iomem *regs;
  899. struct musb *musb;
  900. void __iomem *mbase;
  901. u8 epnum;
  902. u16 csr;
  903. unsigned tmp;
  904. int status = -EINVAL;
  905. if (!ep || !desc)
  906. return -EINVAL;
  907. musb_ep = to_musb_ep(ep);
  908. hw_ep = musb_ep->hw_ep;
  909. regs = hw_ep->regs;
  910. musb = musb_ep->musb;
  911. mbase = musb->mregs;
  912. epnum = musb_ep->current_epnum;
  913. spin_lock_irqsave(&musb->lock, flags);
  914. if (musb_ep->desc) {
  915. status = -EBUSY;
  916. goto fail;
  917. }
  918. musb_ep->type = usb_endpoint_type(desc);
  919. /* check direction and (later) maxpacket size against endpoint */
  920. if (usb_endpoint_num(desc) != epnum)
  921. goto fail;
  922. /* REVISIT this rules out high bandwidth periodic transfers */
  923. tmp = usb_endpoint_maxp(desc);
  924. if (tmp & ~0x07ff) {
  925. int ok;
  926. if (usb_endpoint_dir_in(desc))
  927. ok = musb->hb_iso_tx;
  928. else
  929. ok = musb->hb_iso_rx;
  930. if (!ok) {
  931. dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
  932. goto fail;
  933. }
  934. musb_ep->hb_mult = (tmp >> 11) & 3;
  935. } else {
  936. musb_ep->hb_mult = 0;
  937. }
  938. musb_ep->packet_sz = tmp & 0x7ff;
  939. tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
  940. /* enable the interrupts for the endpoint, set the endpoint
  941. * packet size (or fail), set the mode, clear the fifo
  942. */
  943. musb_ep_select(mbase, epnum);
  944. if (usb_endpoint_dir_in(desc)) {
  945. u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
  946. if (hw_ep->is_shared_fifo)
  947. musb_ep->is_in = 1;
  948. if (!musb_ep->is_in)
  949. goto fail;
  950. if (tmp > hw_ep->max_packet_sz_tx) {
  951. dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
  952. goto fail;
  953. }
  954. int_txe |= (1 << epnum);
  955. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  956. /* REVISIT if can_bulk_split(), use by updating "tmp";
  957. * likewise high bandwidth periodic tx
  958. */
  959. /* Set TXMAXP with the FIFO size of the endpoint
  960. * to disable double buffering mode.
  961. */
  962. if (musb->double_buffer_not_ok)
  963. musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
  964. else
  965. musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
  966. | (musb_ep->hb_mult << 11));
  967. csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
  968. if (musb_readw(regs, MUSB_TXCSR)
  969. & MUSB_TXCSR_FIFONOTEMPTY)
  970. csr |= MUSB_TXCSR_FLUSHFIFO;
  971. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  972. csr |= MUSB_TXCSR_P_ISO;
  973. /* set twice in case of double buffering */
  974. musb_writew(regs, MUSB_TXCSR, csr);
  975. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  976. musb_writew(regs, MUSB_TXCSR, csr);
  977. } else {
  978. u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
  979. if (hw_ep->is_shared_fifo)
  980. musb_ep->is_in = 0;
  981. if (musb_ep->is_in)
  982. goto fail;
  983. if (tmp > hw_ep->max_packet_sz_rx) {
  984. dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
  985. goto fail;
  986. }
  987. int_rxe |= (1 << epnum);
  988. musb_writew(mbase, MUSB_INTRRXE, int_rxe);
  989. /* REVISIT if can_bulk_combine() use by updating "tmp"
  990. * likewise high bandwidth periodic rx
  991. */
  992. /* Set RXMAXP with the FIFO size of the endpoint
  993. * to disable double buffering mode.
  994. */
  995. if (musb->double_buffer_not_ok)
  996. musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
  997. else
  998. musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
  999. | (musb_ep->hb_mult << 11));
  1000. /* force shared fifo to OUT-only mode */
  1001. if (hw_ep->is_shared_fifo) {
  1002. csr = musb_readw(regs, MUSB_TXCSR);
  1003. csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
  1004. musb_writew(regs, MUSB_TXCSR, csr);
  1005. }
  1006. csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
  1007. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  1008. csr |= MUSB_RXCSR_P_ISO;
  1009. else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
  1010. csr |= MUSB_RXCSR_DISNYET;
  1011. /* set twice in case of double buffering */
  1012. musb_writew(regs, MUSB_RXCSR, csr);
  1013. musb_writew(regs, MUSB_RXCSR, csr);
  1014. }
  1015. /* NOTE: all the I/O code _should_ work fine without DMA, in case
  1016. * for some reason you run out of channels here.
  1017. */
  1018. if (is_dma_capable() && musb->dma_controller) {
  1019. struct dma_controller *c = musb->dma_controller;
  1020. musb_ep->dma = c->channel_alloc(c, hw_ep,
  1021. (desc->bEndpointAddress & USB_DIR_IN));
  1022. } else
  1023. musb_ep->dma = NULL;
  1024. musb_ep->desc = desc;
  1025. musb_ep->busy = 0;
  1026. musb_ep->wedged = 0;
  1027. status = 0;
  1028. pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
  1029. musb_driver_name, musb_ep->end_point.name,
  1030. ({ char *s; switch (musb_ep->type) {
  1031. case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
  1032. case USB_ENDPOINT_XFER_INT: s = "int"; break;
  1033. default: s = "iso"; break;
  1034. }; s; }),
  1035. musb_ep->is_in ? "IN" : "OUT",
  1036. musb_ep->dma ? "dma, " : "",
  1037. musb_ep->packet_sz);
  1038. schedule_work(&musb->irq_work);
  1039. fail:
  1040. spin_unlock_irqrestore(&musb->lock, flags);
  1041. return status;
  1042. }
  1043. /*
  1044. * Disable an endpoint flushing all requests queued.
  1045. */
  1046. static int musb_gadget_disable(struct usb_ep *ep)
  1047. {
  1048. unsigned long flags;
  1049. struct musb *musb;
  1050. u8 epnum;
  1051. struct musb_ep *musb_ep;
  1052. void __iomem *epio;
  1053. int status = 0;
  1054. musb_ep = to_musb_ep(ep);
  1055. musb = musb_ep->musb;
  1056. epnum = musb_ep->current_epnum;
  1057. epio = musb->endpoints[epnum].regs;
  1058. spin_lock_irqsave(&musb->lock, flags);
  1059. musb_ep_select(musb->mregs, epnum);
  1060. /* zero the endpoint sizes */
  1061. if (musb_ep->is_in) {
  1062. u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
  1063. int_txe &= ~(1 << epnum);
  1064. musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
  1065. musb_writew(epio, MUSB_TXMAXP, 0);
  1066. } else {
  1067. u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
  1068. int_rxe &= ~(1 << epnum);
  1069. musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
  1070. musb_writew(epio, MUSB_RXMAXP, 0);
  1071. }
  1072. musb_ep->desc = NULL;
  1073. #ifndef __UBOOT__
  1074. musb_ep->end_point.desc = NULL;
  1075. #endif
  1076. /* abort all pending DMA and requests */
  1077. nuke(musb_ep, -ESHUTDOWN);
  1078. schedule_work(&musb->irq_work);
  1079. spin_unlock_irqrestore(&(musb->lock), flags);
  1080. dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
  1081. return status;
  1082. }
  1083. /*
  1084. * Allocate a request for an endpoint.
  1085. * Reused by ep0 code.
  1086. */
  1087. struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1088. {
  1089. struct musb_ep *musb_ep = to_musb_ep(ep);
  1090. struct musb *musb = musb_ep->musb;
  1091. struct musb_request *request = NULL;
  1092. request = kzalloc(sizeof *request, gfp_flags);
  1093. if (!request) {
  1094. dev_dbg(musb->controller, "not enough memory\n");
  1095. return NULL;
  1096. }
  1097. request->request.dma = DMA_ADDR_INVALID;
  1098. request->epnum = musb_ep->current_epnum;
  1099. request->ep = musb_ep;
  1100. return &request->request;
  1101. }
  1102. /*
  1103. * Free a request
  1104. * Reused by ep0 code.
  1105. */
  1106. void musb_free_request(struct usb_ep *ep, struct usb_request *req)
  1107. {
  1108. kfree(to_musb_request(req));
  1109. }
  1110. static LIST_HEAD(buffers);
  1111. struct free_record {
  1112. struct list_head list;
  1113. struct device *dev;
  1114. unsigned bytes;
  1115. dma_addr_t dma;
  1116. };
  1117. /*
  1118. * Context: controller locked, IRQs blocked.
  1119. */
  1120. void musb_ep_restart(struct musb *musb, struct musb_request *req)
  1121. {
  1122. dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
  1123. req->tx ? "TX/IN" : "RX/OUT",
  1124. &req->request, req->request.length, req->epnum);
  1125. musb_ep_select(musb->mregs, req->epnum);
  1126. if (req->tx)
  1127. txstate(musb, req);
  1128. else
  1129. rxstate(musb, req);
  1130. }
  1131. static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
  1132. gfp_t gfp_flags)
  1133. {
  1134. struct musb_ep *musb_ep;
  1135. struct musb_request *request;
  1136. struct musb *musb;
  1137. int status = 0;
  1138. unsigned long lockflags;
  1139. if (!ep || !req)
  1140. return -EINVAL;
  1141. if (!req->buf)
  1142. return -ENODATA;
  1143. musb_ep = to_musb_ep(ep);
  1144. musb = musb_ep->musb;
  1145. request = to_musb_request(req);
  1146. request->musb = musb;
  1147. if (request->ep != musb_ep)
  1148. return -EINVAL;
  1149. dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
  1150. /* request is mine now... */
  1151. request->request.actual = 0;
  1152. request->request.status = -EINPROGRESS;
  1153. request->epnum = musb_ep->current_epnum;
  1154. request->tx = musb_ep->is_in;
  1155. map_dma_buffer(request, musb, musb_ep);
  1156. spin_lock_irqsave(&musb->lock, lockflags);
  1157. /* don't queue if the ep is down */
  1158. if (!musb_ep->desc) {
  1159. dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
  1160. req, ep->name, "disabled");
  1161. status = -ESHUTDOWN;
  1162. goto cleanup;
  1163. }
  1164. /* add request to the list */
  1165. list_add_tail(&request->list, &musb_ep->req_list);
  1166. /* it this is the head of the queue, start i/o ... */
  1167. if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
  1168. musb_ep_restart(musb, request);
  1169. cleanup:
  1170. spin_unlock_irqrestore(&musb->lock, lockflags);
  1171. return status;
  1172. }
  1173. static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
  1174. {
  1175. struct musb_ep *musb_ep = to_musb_ep(ep);
  1176. struct musb_request *req = to_musb_request(request);
  1177. struct musb_request *r;
  1178. unsigned long flags;
  1179. int status = 0;
  1180. struct musb *musb = musb_ep->musb;
  1181. if (!ep || !request || to_musb_request(request)->ep != musb_ep)
  1182. return -EINVAL;
  1183. spin_lock_irqsave(&musb->lock, flags);
  1184. list_for_each_entry(r, &musb_ep->req_list, list) {
  1185. if (r == req)
  1186. break;
  1187. }
  1188. if (r != req) {
  1189. dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
  1190. status = -EINVAL;
  1191. goto done;
  1192. }
  1193. /* if the hardware doesn't have the request, easy ... */
  1194. if (musb_ep->req_list.next != &req->list || musb_ep->busy)
  1195. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1196. /* ... else abort the dma transfer ... */
  1197. else if (is_dma_capable() && musb_ep->dma) {
  1198. struct dma_controller *c = musb->dma_controller;
  1199. musb_ep_select(musb->mregs, musb_ep->current_epnum);
  1200. if (c->channel_abort)
  1201. status = c->channel_abort(musb_ep->dma);
  1202. else
  1203. status = -EBUSY;
  1204. if (status == 0)
  1205. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1206. } else {
  1207. /* NOTE: by sticking to easily tested hardware/driver states,
  1208. * we leave counting of in-flight packets imprecise.
  1209. */
  1210. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1211. }
  1212. done:
  1213. spin_unlock_irqrestore(&musb->lock, flags);
  1214. return status;
  1215. }
  1216. /*
  1217. * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
  1218. * data but will queue requests.
  1219. *
  1220. * exported to ep0 code
  1221. */
  1222. static int musb_gadget_set_halt(struct usb_ep *ep, int value)
  1223. {
  1224. struct musb_ep *musb_ep = to_musb_ep(ep);
  1225. u8 epnum = musb_ep->current_epnum;
  1226. struct musb *musb = musb_ep->musb;
  1227. void __iomem *epio = musb->endpoints[epnum].regs;
  1228. void __iomem *mbase;
  1229. unsigned long flags;
  1230. u16 csr;
  1231. struct musb_request *request;
  1232. int status = 0;
  1233. if (!ep)
  1234. return -EINVAL;
  1235. mbase = musb->mregs;
  1236. spin_lock_irqsave(&musb->lock, flags);
  1237. if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
  1238. status = -EINVAL;
  1239. goto done;
  1240. }
  1241. musb_ep_select(mbase, epnum);
  1242. request = next_request(musb_ep);
  1243. if (value) {
  1244. if (request) {
  1245. dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
  1246. ep->name);
  1247. status = -EAGAIN;
  1248. goto done;
  1249. }
  1250. /* Cannot portably stall with non-empty FIFO */
  1251. if (musb_ep->is_in) {
  1252. csr = musb_readw(epio, MUSB_TXCSR);
  1253. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1254. dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
  1255. status = -EAGAIN;
  1256. goto done;
  1257. }
  1258. }
  1259. } else
  1260. musb_ep->wedged = 0;
  1261. /* set/clear the stall and toggle bits */
  1262. dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
  1263. if (musb_ep->is_in) {
  1264. csr = musb_readw(epio, MUSB_TXCSR);
  1265. csr |= MUSB_TXCSR_P_WZC_BITS
  1266. | MUSB_TXCSR_CLRDATATOG;
  1267. if (value)
  1268. csr |= MUSB_TXCSR_P_SENDSTALL;
  1269. else
  1270. csr &= ~(MUSB_TXCSR_P_SENDSTALL
  1271. | MUSB_TXCSR_P_SENTSTALL);
  1272. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1273. musb_writew(epio, MUSB_TXCSR, csr);
  1274. } else {
  1275. csr = musb_readw(epio, MUSB_RXCSR);
  1276. csr |= MUSB_RXCSR_P_WZC_BITS
  1277. | MUSB_RXCSR_FLUSHFIFO
  1278. | MUSB_RXCSR_CLRDATATOG;
  1279. if (value)
  1280. csr |= MUSB_RXCSR_P_SENDSTALL;
  1281. else
  1282. csr &= ~(MUSB_RXCSR_P_SENDSTALL
  1283. | MUSB_RXCSR_P_SENTSTALL);
  1284. musb_writew(epio, MUSB_RXCSR, csr);
  1285. }
  1286. /* maybe start the first request in the queue */
  1287. if (!musb_ep->busy && !value && request) {
  1288. dev_dbg(musb->controller, "restarting the request\n");
  1289. musb_ep_restart(musb, request);
  1290. }
  1291. done:
  1292. spin_unlock_irqrestore(&musb->lock, flags);
  1293. return status;
  1294. }
  1295. #ifndef __UBOOT__
  1296. /*
  1297. * Sets the halt feature with the clear requests ignored
  1298. */
  1299. static int musb_gadget_set_wedge(struct usb_ep *ep)
  1300. {
  1301. struct musb_ep *musb_ep = to_musb_ep(ep);
  1302. if (!ep)
  1303. return -EINVAL;
  1304. musb_ep->wedged = 1;
  1305. return usb_ep_set_halt(ep);
  1306. }
  1307. #endif
  1308. static int musb_gadget_fifo_status(struct usb_ep *ep)
  1309. {
  1310. struct musb_ep *musb_ep = to_musb_ep(ep);
  1311. void __iomem *epio = musb_ep->hw_ep->regs;
  1312. int retval = -EINVAL;
  1313. if (musb_ep->desc && !musb_ep->is_in) {
  1314. struct musb *musb = musb_ep->musb;
  1315. int epnum = musb_ep->current_epnum;
  1316. void __iomem *mbase = musb->mregs;
  1317. unsigned long flags;
  1318. spin_lock_irqsave(&musb->lock, flags);
  1319. musb_ep_select(mbase, epnum);
  1320. /* FIXME return zero unless RXPKTRDY is set */
  1321. retval = musb_readw(epio, MUSB_RXCOUNT);
  1322. spin_unlock_irqrestore(&musb->lock, flags);
  1323. }
  1324. return retval;
  1325. }
  1326. static void musb_gadget_fifo_flush(struct usb_ep *ep)
  1327. {
  1328. struct musb_ep *musb_ep = to_musb_ep(ep);
  1329. struct musb *musb = musb_ep->musb;
  1330. u8 epnum = musb_ep->current_epnum;
  1331. void __iomem *epio = musb->endpoints[epnum].regs;
  1332. void __iomem *mbase;
  1333. unsigned long flags;
  1334. u16 csr, int_txe;
  1335. mbase = musb->mregs;
  1336. spin_lock_irqsave(&musb->lock, flags);
  1337. musb_ep_select(mbase, (u8) epnum);
  1338. /* disable interrupts */
  1339. int_txe = musb_readw(mbase, MUSB_INTRTXE);
  1340. musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
  1341. if (musb_ep->is_in) {
  1342. csr = musb_readw(epio, MUSB_TXCSR);
  1343. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1344. csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
  1345. /*
  1346. * Setting both TXPKTRDY and FLUSHFIFO makes controller
  1347. * to interrupt current FIFO loading, but not flushing
  1348. * the already loaded ones.
  1349. */
  1350. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1351. musb_writew(epio, MUSB_TXCSR, csr);
  1352. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  1353. musb_writew(epio, MUSB_TXCSR, csr);
  1354. }
  1355. } else {
  1356. csr = musb_readw(epio, MUSB_RXCSR);
  1357. csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
  1358. musb_writew(epio, MUSB_RXCSR, csr);
  1359. musb_writew(epio, MUSB_RXCSR, csr);
  1360. }
  1361. /* re-enable interrupt */
  1362. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  1363. spin_unlock_irqrestore(&musb->lock, flags);
  1364. }
  1365. static const struct usb_ep_ops musb_ep_ops = {
  1366. .enable = musb_gadget_enable,
  1367. .disable = musb_gadget_disable,
  1368. .alloc_request = musb_alloc_request,
  1369. .free_request = musb_free_request,
  1370. .queue = musb_gadget_queue,
  1371. .dequeue = musb_gadget_dequeue,
  1372. .set_halt = musb_gadget_set_halt,
  1373. #ifndef __UBOOT__
  1374. .set_wedge = musb_gadget_set_wedge,
  1375. #endif
  1376. .fifo_status = musb_gadget_fifo_status,
  1377. .fifo_flush = musb_gadget_fifo_flush
  1378. };
  1379. /* ----------------------------------------------------------------------- */
  1380. static int musb_gadget_get_frame(struct usb_gadget *gadget)
  1381. {
  1382. struct musb *musb = gadget_to_musb(gadget);
  1383. return (int)musb_readw(musb->mregs, MUSB_FRAME);
  1384. }
  1385. static int musb_gadget_wakeup(struct usb_gadget *gadget)
  1386. {
  1387. #ifndef __UBOOT__
  1388. struct musb *musb = gadget_to_musb(gadget);
  1389. void __iomem *mregs = musb->mregs;
  1390. unsigned long flags;
  1391. int status = -EINVAL;
  1392. u8 power, devctl;
  1393. int retries;
  1394. spin_lock_irqsave(&musb->lock, flags);
  1395. switch (musb->xceiv->state) {
  1396. case OTG_STATE_B_PERIPHERAL:
  1397. /* NOTE: OTG state machine doesn't include B_SUSPENDED;
  1398. * that's part of the standard usb 1.1 state machine, and
  1399. * doesn't affect OTG transitions.
  1400. */
  1401. if (musb->may_wakeup && musb->is_suspended)
  1402. break;
  1403. goto done;
  1404. case OTG_STATE_B_IDLE:
  1405. /* Start SRP ... OTG not required. */
  1406. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1407. dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
  1408. devctl |= MUSB_DEVCTL_SESSION;
  1409. musb_writeb(mregs, MUSB_DEVCTL, devctl);
  1410. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1411. retries = 100;
  1412. while (!(devctl & MUSB_DEVCTL_SESSION)) {
  1413. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1414. if (retries-- < 1)
  1415. break;
  1416. }
  1417. retries = 10000;
  1418. while (devctl & MUSB_DEVCTL_SESSION) {
  1419. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1420. if (retries-- < 1)
  1421. break;
  1422. }
  1423. spin_unlock_irqrestore(&musb->lock, flags);
  1424. otg_start_srp(musb->xceiv->otg);
  1425. spin_lock_irqsave(&musb->lock, flags);
  1426. /* Block idling for at least 1s */
  1427. musb_platform_try_idle(musb,
  1428. jiffies + msecs_to_jiffies(1 * HZ));
  1429. status = 0;
  1430. goto done;
  1431. default:
  1432. dev_dbg(musb->controller, "Unhandled wake: %s\n",
  1433. otg_state_string(musb->xceiv->state));
  1434. goto done;
  1435. }
  1436. status = 0;
  1437. power = musb_readb(mregs, MUSB_POWER);
  1438. power |= MUSB_POWER_RESUME;
  1439. musb_writeb(mregs, MUSB_POWER, power);
  1440. dev_dbg(musb->controller, "issue wakeup\n");
  1441. /* FIXME do this next chunk in a timer callback, no udelay */
  1442. mdelay(2);
  1443. power = musb_readb(mregs, MUSB_POWER);
  1444. power &= ~MUSB_POWER_RESUME;
  1445. musb_writeb(mregs, MUSB_POWER, power);
  1446. done:
  1447. spin_unlock_irqrestore(&musb->lock, flags);
  1448. return status;
  1449. #else
  1450. return 0;
  1451. #endif
  1452. }
  1453. static int
  1454. musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
  1455. {
  1456. struct musb *musb = gadget_to_musb(gadget);
  1457. musb->is_self_powered = !!is_selfpowered;
  1458. return 0;
  1459. }
  1460. static void musb_pullup(struct musb *musb, int is_on)
  1461. {
  1462. u8 power;
  1463. power = musb_readb(musb->mregs, MUSB_POWER);
  1464. if (is_on)
  1465. power |= MUSB_POWER_SOFTCONN;
  1466. else
  1467. power &= ~MUSB_POWER_SOFTCONN;
  1468. /* FIXME if on, HdrcStart; if off, HdrcStop */
  1469. dev_dbg(musb->controller, "gadget D+ pullup %s\n",
  1470. is_on ? "on" : "off");
  1471. musb_writeb(musb->mregs, MUSB_POWER, power);
  1472. }
  1473. #if 0
  1474. static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
  1475. {
  1476. dev_dbg(musb->controller, "<= %s =>\n", __func__);
  1477. /*
  1478. * FIXME iff driver's softconnect flag is set (as it is during probe,
  1479. * though that can clear it), just musb_pullup().
  1480. */
  1481. return -EINVAL;
  1482. }
  1483. #endif
  1484. static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1485. {
  1486. #ifndef __UBOOT__
  1487. struct musb *musb = gadget_to_musb(gadget);
  1488. if (!musb->xceiv->set_power)
  1489. return -EOPNOTSUPP;
  1490. return usb_phy_set_power(musb->xceiv, mA);
  1491. #else
  1492. return 0;
  1493. #endif
  1494. }
  1495. static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
  1496. {
  1497. struct musb *musb = gadget_to_musb(gadget);
  1498. unsigned long flags;
  1499. is_on = !!is_on;
  1500. pm_runtime_get_sync(musb->controller);
  1501. /* NOTE: this assumes we are sensing vbus; we'd rather
  1502. * not pullup unless the B-session is active.
  1503. */
  1504. spin_lock_irqsave(&musb->lock, flags);
  1505. if (is_on != musb->softconnect) {
  1506. musb->softconnect = is_on;
  1507. musb_pullup(musb, is_on);
  1508. }
  1509. spin_unlock_irqrestore(&musb->lock, flags);
  1510. pm_runtime_put(musb->controller);
  1511. return 0;
  1512. }
  1513. #ifndef __UBOOT__
  1514. static int musb_gadget_start(struct usb_gadget *g,
  1515. struct usb_gadget_driver *driver);
  1516. static int musb_gadget_stop(struct usb_gadget *g,
  1517. struct usb_gadget_driver *driver);
  1518. #else
  1519. static int musb_gadget_stop(struct usb_gadget *g)
  1520. {
  1521. struct musb *musb = gadget_to_musb(g);
  1522. musb_stop(musb);
  1523. return 0;
  1524. }
  1525. #endif
  1526. static const struct usb_gadget_ops musb_gadget_operations = {
  1527. .get_frame = musb_gadget_get_frame,
  1528. .wakeup = musb_gadget_wakeup,
  1529. .set_selfpowered = musb_gadget_set_self_powered,
  1530. /* .vbus_session = musb_gadget_vbus_session, */
  1531. .vbus_draw = musb_gadget_vbus_draw,
  1532. .pullup = musb_gadget_pullup,
  1533. #ifndef __UBOOT__
  1534. .udc_start = musb_gadget_start,
  1535. .udc_stop = musb_gadget_stop,
  1536. #else
  1537. .udc_start = musb_gadget_start,
  1538. .udc_stop = musb_gadget_stop,
  1539. #endif
  1540. };
  1541. /* ----------------------------------------------------------------------- */
  1542. /* Registration */
  1543. /* Only this registration code "knows" the rule (from USB standards)
  1544. * about there being only one external upstream port. It assumes
  1545. * all peripheral ports are external...
  1546. */
  1547. #ifndef __UBOOT__
  1548. static void musb_gadget_release(struct device *dev)
  1549. {
  1550. /* kref_put(WHAT) */
  1551. dev_dbg(dev, "%s\n", __func__);
  1552. }
  1553. #endif
  1554. static void __devinit
  1555. init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
  1556. {
  1557. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  1558. memset(ep, 0, sizeof *ep);
  1559. ep->current_epnum = epnum;
  1560. ep->musb = musb;
  1561. ep->hw_ep = hw_ep;
  1562. ep->is_in = is_in;
  1563. INIT_LIST_HEAD(&ep->req_list);
  1564. sprintf(ep->name, "ep%d%s", epnum,
  1565. (!epnum || hw_ep->is_shared_fifo) ? "" : (
  1566. is_in ? "in" : "out"));
  1567. ep->end_point.name = ep->name;
  1568. INIT_LIST_HEAD(&ep->end_point.ep_list);
  1569. if (!epnum) {
  1570. ep->end_point.maxpacket = 64;
  1571. ep->end_point.ops = &musb_g_ep0_ops;
  1572. musb->g.ep0 = &ep->end_point;
  1573. } else {
  1574. if (is_in)
  1575. ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
  1576. else
  1577. ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
  1578. ep->end_point.ops = &musb_ep_ops;
  1579. list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
  1580. }
  1581. }
  1582. /*
  1583. * Initialize the endpoints exposed to peripheral drivers, with backlinks
  1584. * to the rest of the driver state.
  1585. */
  1586. static inline void __devinit musb_g_init_endpoints(struct musb *musb)
  1587. {
  1588. u8 epnum;
  1589. struct musb_hw_ep *hw_ep;
  1590. unsigned count = 0;
  1591. /* initialize endpoint list just once */
  1592. INIT_LIST_HEAD(&(musb->g.ep_list));
  1593. for (epnum = 0, hw_ep = musb->endpoints;
  1594. epnum < musb->nr_endpoints;
  1595. epnum++, hw_ep++) {
  1596. if (hw_ep->is_shared_fifo /* || !epnum */) {
  1597. init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
  1598. count++;
  1599. } else {
  1600. if (hw_ep->max_packet_sz_tx) {
  1601. init_peripheral_ep(musb, &hw_ep->ep_in,
  1602. epnum, 1);
  1603. count++;
  1604. }
  1605. if (hw_ep->max_packet_sz_rx) {
  1606. init_peripheral_ep(musb, &hw_ep->ep_out,
  1607. epnum, 0);
  1608. count++;
  1609. }
  1610. }
  1611. }
  1612. }
  1613. /* called once during driver setup to initialize and link into
  1614. * the driver model; memory is zeroed.
  1615. */
  1616. int __devinit musb_gadget_setup(struct musb *musb)
  1617. {
  1618. int status;
  1619. /* REVISIT minor race: if (erroneously) setting up two
  1620. * musb peripherals at the same time, only the bus lock
  1621. * is probably held.
  1622. */
  1623. musb->g.ops = &musb_gadget_operations;
  1624. #ifndef __UBOOT__
  1625. musb->g.max_speed = USB_SPEED_HIGH;
  1626. #endif
  1627. musb->g.speed = USB_SPEED_UNKNOWN;
  1628. #ifndef __UBOOT__
  1629. /* this "gadget" abstracts/virtualizes the controller */
  1630. dev_set_name(&musb->g.dev, "gadget");
  1631. musb->g.dev.parent = musb->controller;
  1632. musb->g.dev.dma_mask = musb->controller->dma_mask;
  1633. musb->g.dev.release = musb_gadget_release;
  1634. #endif
  1635. musb->g.name = musb_driver_name;
  1636. #ifndef __UBOOT__
  1637. if (is_otg_enabled(musb))
  1638. musb->g.is_otg = 1;
  1639. #endif
  1640. musb_g_init_endpoints(musb);
  1641. musb->is_active = 0;
  1642. musb_platform_try_idle(musb, 0);
  1643. #ifndef __UBOOT__
  1644. status = device_register(&musb->g.dev);
  1645. if (status != 0) {
  1646. put_device(&musb->g.dev);
  1647. return status;
  1648. }
  1649. status = usb_add_gadget_udc(musb->controller, &musb->g);
  1650. if (status)
  1651. goto err;
  1652. #endif
  1653. return 0;
  1654. #ifndef __UBOOT__
  1655. err:
  1656. musb->g.dev.parent = NULL;
  1657. device_unregister(&musb->g.dev);
  1658. return status;
  1659. #endif
  1660. }
  1661. void musb_gadget_cleanup(struct musb *musb)
  1662. {
  1663. #ifndef __UBOOT__
  1664. usb_del_gadget_udc(&musb->g);
  1665. if (musb->g.dev.parent)
  1666. device_unregister(&musb->g.dev);
  1667. #endif
  1668. }
  1669. /*
  1670. * Register the gadget driver. Used by gadget drivers when
  1671. * registering themselves with the controller.
  1672. *
  1673. * -EINVAL something went wrong (not driver)
  1674. * -EBUSY another gadget is already using the controller
  1675. * -ENOMEM no memory to perform the operation
  1676. *
  1677. * @param driver the gadget driver
  1678. * @return <0 if error, 0 if everything is fine
  1679. */
  1680. #ifndef __UBOOT__
  1681. static int musb_gadget_start(struct usb_gadget *g,
  1682. struct usb_gadget_driver *driver)
  1683. #else
  1684. int musb_gadget_start(struct usb_gadget *g,
  1685. struct usb_gadget_driver *driver)
  1686. #endif
  1687. {
  1688. struct musb *musb = gadget_to_musb(g);
  1689. #ifndef __UBOOT__
  1690. struct usb_otg *otg = musb->xceiv->otg;
  1691. #endif
  1692. unsigned long flags;
  1693. int retval = -EINVAL;
  1694. #ifndef __UBOOT__
  1695. if (driver->max_speed < USB_SPEED_HIGH)
  1696. goto err0;
  1697. #endif
  1698. pm_runtime_get_sync(musb->controller);
  1699. #ifndef __UBOOT__
  1700. dev_dbg(musb->controller, "registering driver %s\n", driver->function);
  1701. #endif
  1702. musb->softconnect = 0;
  1703. musb->gadget_driver = driver;
  1704. spin_lock_irqsave(&musb->lock, flags);
  1705. musb->is_active = 1;
  1706. #ifndef __UBOOT__
  1707. otg_set_peripheral(otg, &musb->g);
  1708. musb->xceiv->state = OTG_STATE_B_IDLE;
  1709. /*
  1710. * FIXME this ignores the softconnect flag. Drivers are
  1711. * allowed hold the peripheral inactive until for example
  1712. * userspace hooks up printer hardware or DSP codecs, so
  1713. * hosts only see fully functional devices.
  1714. */
  1715. if (!is_otg_enabled(musb))
  1716. #endif
  1717. musb_start(musb);
  1718. spin_unlock_irqrestore(&musb->lock, flags);
  1719. #ifndef __UBOOT__
  1720. if (is_otg_enabled(musb)) {
  1721. struct usb_hcd *hcd = musb_to_hcd(musb);
  1722. dev_dbg(musb->controller, "OTG startup...\n");
  1723. /* REVISIT: funcall to other code, which also
  1724. * handles power budgeting ... this way also
  1725. * ensures HdrcStart is indirectly called.
  1726. */
  1727. retval = usb_add_hcd(musb_to_hcd(musb), 0, 0);
  1728. if (retval < 0) {
  1729. dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
  1730. goto err2;
  1731. }
  1732. if ((musb->xceiv->last_event == USB_EVENT_ID)
  1733. && otg->set_vbus)
  1734. otg_set_vbus(otg, 1);
  1735. hcd->self.uses_pio_for_control = 1;
  1736. }
  1737. if (musb->xceiv->last_event == USB_EVENT_NONE)
  1738. pm_runtime_put(musb->controller);
  1739. #endif
  1740. return 0;
  1741. #ifndef __UBOOT__
  1742. err2:
  1743. if (!is_otg_enabled(musb))
  1744. musb_stop(musb);
  1745. err0:
  1746. return retval;
  1747. #endif
  1748. }
  1749. #ifndef __UBOOT__
  1750. static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
  1751. {
  1752. int i;
  1753. struct musb_hw_ep *hw_ep;
  1754. /* don't disconnect if it's not connected */
  1755. if (musb->g.speed == USB_SPEED_UNKNOWN)
  1756. driver = NULL;
  1757. else
  1758. musb->g.speed = USB_SPEED_UNKNOWN;
  1759. /* deactivate the hardware */
  1760. if (musb->softconnect) {
  1761. musb->softconnect = 0;
  1762. musb_pullup(musb, 0);
  1763. }
  1764. musb_stop(musb);
  1765. /* killing any outstanding requests will quiesce the driver;
  1766. * then report disconnect
  1767. */
  1768. if (driver) {
  1769. for (i = 0, hw_ep = musb->endpoints;
  1770. i < musb->nr_endpoints;
  1771. i++, hw_ep++) {
  1772. musb_ep_select(musb->mregs, i);
  1773. if (hw_ep->is_shared_fifo /* || !epnum */) {
  1774. nuke(&hw_ep->ep_in, -ESHUTDOWN);
  1775. } else {
  1776. if (hw_ep->max_packet_sz_tx)
  1777. nuke(&hw_ep->ep_in, -ESHUTDOWN);
  1778. if (hw_ep->max_packet_sz_rx)
  1779. nuke(&hw_ep->ep_out, -ESHUTDOWN);
  1780. }
  1781. }
  1782. }
  1783. }
  1784. /*
  1785. * Unregister the gadget driver. Used by gadget drivers when
  1786. * unregistering themselves from the controller.
  1787. *
  1788. * @param driver the gadget driver to unregister
  1789. */
  1790. static int musb_gadget_stop(struct usb_gadget *g,
  1791. struct usb_gadget_driver *driver)
  1792. {
  1793. struct musb *musb = gadget_to_musb(g);
  1794. unsigned long flags;
  1795. if (musb->xceiv->last_event == USB_EVENT_NONE)
  1796. pm_runtime_get_sync(musb->controller);
  1797. /*
  1798. * REVISIT always use otg_set_peripheral() here too;
  1799. * this needs to shut down the OTG engine.
  1800. */
  1801. spin_lock_irqsave(&musb->lock, flags);
  1802. musb_hnp_stop(musb);
  1803. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1804. musb->xceiv->state = OTG_STATE_UNDEFINED;
  1805. stop_activity(musb, driver);
  1806. otg_set_peripheral(musb->xceiv->otg, NULL);
  1807. dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
  1808. musb->is_active = 0;
  1809. musb_platform_try_idle(musb, 0);
  1810. spin_unlock_irqrestore(&musb->lock, flags);
  1811. if (is_otg_enabled(musb)) {
  1812. usb_remove_hcd(musb_to_hcd(musb));
  1813. /* FIXME we need to be able to register another
  1814. * gadget driver here and have everything work;
  1815. * that currently misbehaves.
  1816. */
  1817. }
  1818. if (!is_otg_enabled(musb))
  1819. musb_stop(musb);
  1820. pm_runtime_put(musb->controller);
  1821. return 0;
  1822. }
  1823. #endif
  1824. /* ----------------------------------------------------------------------- */
  1825. /* lifecycle operations called through plat_uds.c */
  1826. void musb_g_resume(struct musb *musb)
  1827. {
  1828. #ifndef __UBOOT__
  1829. musb->is_suspended = 0;
  1830. switch (musb->xceiv->state) {
  1831. case OTG_STATE_B_IDLE:
  1832. break;
  1833. case OTG_STATE_B_WAIT_ACON:
  1834. case OTG_STATE_B_PERIPHERAL:
  1835. musb->is_active = 1;
  1836. if (musb->gadget_driver && musb->gadget_driver->resume) {
  1837. spin_unlock(&musb->lock);
  1838. musb->gadget_driver->resume(&musb->g);
  1839. spin_lock(&musb->lock);
  1840. }
  1841. break;
  1842. default:
  1843. WARNING("unhandled RESUME transition (%s)\n",
  1844. otg_state_string(musb->xceiv->state));
  1845. }
  1846. #endif
  1847. }
  1848. /* called when SOF packets stop for 3+ msec */
  1849. void musb_g_suspend(struct musb *musb)
  1850. {
  1851. #ifndef __UBOOT__
  1852. u8 devctl;
  1853. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1854. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  1855. switch (musb->xceiv->state) {
  1856. case OTG_STATE_B_IDLE:
  1857. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  1858. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  1859. break;
  1860. case OTG_STATE_B_PERIPHERAL:
  1861. musb->is_suspended = 1;
  1862. if (musb->gadget_driver && musb->gadget_driver->suspend) {
  1863. spin_unlock(&musb->lock);
  1864. musb->gadget_driver->suspend(&musb->g);
  1865. spin_lock(&musb->lock);
  1866. }
  1867. break;
  1868. default:
  1869. /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
  1870. * A_PERIPHERAL may need care too
  1871. */
  1872. WARNING("unhandled SUSPEND transition (%s)\n",
  1873. otg_state_string(musb->xceiv->state));
  1874. }
  1875. #endif
  1876. }
  1877. /* Called during SRP */
  1878. void musb_g_wakeup(struct musb *musb)
  1879. {
  1880. musb_gadget_wakeup(&musb->g);
  1881. }
  1882. /* called when VBUS drops below session threshold, and in other cases */
  1883. void musb_g_disconnect(struct musb *musb)
  1884. {
  1885. void __iomem *mregs = musb->mregs;
  1886. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  1887. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  1888. /* clear HR */
  1889. musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
  1890. /* don't draw vbus until new b-default session */
  1891. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1892. musb->g.speed = USB_SPEED_UNKNOWN;
  1893. if (musb->gadget_driver && musb->gadget_driver->disconnect) {
  1894. spin_unlock(&musb->lock);
  1895. musb->gadget_driver->disconnect(&musb->g);
  1896. spin_lock(&musb->lock);
  1897. }
  1898. #ifndef __UBOOT__
  1899. switch (musb->xceiv->state) {
  1900. default:
  1901. dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
  1902. otg_state_string(musb->xceiv->state));
  1903. musb->xceiv->state = OTG_STATE_A_IDLE;
  1904. MUSB_HST_MODE(musb);
  1905. break;
  1906. case OTG_STATE_A_PERIPHERAL:
  1907. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  1908. MUSB_HST_MODE(musb);
  1909. break;
  1910. case OTG_STATE_B_WAIT_ACON:
  1911. case OTG_STATE_B_HOST:
  1912. case OTG_STATE_B_PERIPHERAL:
  1913. case OTG_STATE_B_IDLE:
  1914. musb->xceiv->state = OTG_STATE_B_IDLE;
  1915. break;
  1916. case OTG_STATE_B_SRP_INIT:
  1917. break;
  1918. }
  1919. #endif
  1920. musb->is_active = 0;
  1921. }
  1922. void musb_g_reset(struct musb *musb)
  1923. __releases(musb->lock)
  1924. __acquires(musb->lock)
  1925. {
  1926. void __iomem *mbase = musb->mregs;
  1927. u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
  1928. u8 power;
  1929. #ifndef __UBOOT__
  1930. dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
  1931. (devctl & MUSB_DEVCTL_BDEVICE)
  1932. ? "B-Device" : "A-Device",
  1933. musb_readb(mbase, MUSB_FADDR),
  1934. musb->gadget_driver
  1935. ? musb->gadget_driver->driver.name
  1936. : NULL
  1937. );
  1938. #endif
  1939. /* report disconnect, if we didn't already (flushing EP state) */
  1940. if (musb->g.speed != USB_SPEED_UNKNOWN)
  1941. musb_g_disconnect(musb);
  1942. /* clear HR */
  1943. else if (devctl & MUSB_DEVCTL_HR)
  1944. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  1945. /* what speed did we negotiate? */
  1946. power = musb_readb(mbase, MUSB_POWER);
  1947. musb->g.speed = (power & MUSB_POWER_HSMODE)
  1948. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  1949. /* start in USB_STATE_DEFAULT */
  1950. musb->is_active = 1;
  1951. musb->is_suspended = 0;
  1952. MUSB_DEV_MODE(musb);
  1953. musb->address = 0;
  1954. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  1955. musb->may_wakeup = 0;
  1956. musb->g.b_hnp_enable = 0;
  1957. musb->g.a_alt_hnp_support = 0;
  1958. musb->g.a_hnp_support = 0;
  1959. #ifndef __UBOOT__
  1960. /* Normal reset, as B-Device;
  1961. * or else after HNP, as A-Device
  1962. */
  1963. if (devctl & MUSB_DEVCTL_BDEVICE) {
  1964. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  1965. musb->g.is_a_peripheral = 0;
  1966. } else if (is_otg_enabled(musb)) {
  1967. musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
  1968. musb->g.is_a_peripheral = 1;
  1969. } else
  1970. WARN_ON(1);
  1971. /* start with default limits on VBUS power draw */
  1972. (void) musb_gadget_vbus_draw(&musb->g,
  1973. is_otg_enabled(musb) ? 8 : 100);
  1974. #endif
  1975. }