am35x.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments AM35x "glue layer"
  4. *
  5. * Copyright (c) 2010, by Texas Instruments
  6. *
  7. * Based on the DA8xx "glue layer" code.
  8. * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  9. *
  10. * This file is part of the Inventra Controller Driver for Linux.
  11. *
  12. */
  13. #ifndef __UBOOT__
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/dma-mapping.h>
  23. #include <plat/usb.h>
  24. #else
  25. #include <common.h>
  26. #include <asm/omap_musb.h>
  27. #include <linux/bug.h>
  28. #include "linux-compat.h"
  29. #endif
  30. #include "musb_core.h"
  31. /*
  32. * AM35x specific definitions
  33. */
  34. /* USB 2.0 OTG module registers */
  35. #define USB_REVISION_REG 0x00
  36. #define USB_CTRL_REG 0x04
  37. #define USB_STAT_REG 0x08
  38. #define USB_EMULATION_REG 0x0c
  39. /* 0x10 Reserved */
  40. #define USB_AUTOREQ_REG 0x14
  41. #define USB_SRP_FIX_TIME_REG 0x18
  42. #define USB_TEARDOWN_REG 0x1c
  43. #define EP_INTR_SRC_REG 0x20
  44. #define EP_INTR_SRC_SET_REG 0x24
  45. #define EP_INTR_SRC_CLEAR_REG 0x28
  46. #define EP_INTR_MASK_REG 0x2c
  47. #define EP_INTR_MASK_SET_REG 0x30
  48. #define EP_INTR_MASK_CLEAR_REG 0x34
  49. #define EP_INTR_SRC_MASKED_REG 0x38
  50. #define CORE_INTR_SRC_REG 0x40
  51. #define CORE_INTR_SRC_SET_REG 0x44
  52. #define CORE_INTR_SRC_CLEAR_REG 0x48
  53. #define CORE_INTR_MASK_REG 0x4c
  54. #define CORE_INTR_MASK_SET_REG 0x50
  55. #define CORE_INTR_MASK_CLEAR_REG 0x54
  56. #define CORE_INTR_SRC_MASKED_REG 0x58
  57. /* 0x5c Reserved */
  58. #define USB_END_OF_INTR_REG 0x60
  59. /* Control register bits */
  60. #define AM35X_SOFT_RESET_MASK 1
  61. /* USB interrupt register bits */
  62. #define AM35X_INTR_USB_SHIFT 16
  63. #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
  64. #define AM35X_INTR_DRVVBUS 0x100
  65. #define AM35X_INTR_RX_SHIFT 16
  66. #define AM35X_INTR_TX_SHIFT 0
  67. #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
  68. #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
  69. #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  70. #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  71. #define USB_MENTOR_CORE_OFFSET 0x400
  72. struct am35x_glue {
  73. struct device *dev;
  74. struct platform_device *musb;
  75. struct clk *phy_clk;
  76. struct clk *clk;
  77. };
  78. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  79. /*
  80. * am35x_musb_enable - enable interrupts
  81. */
  82. #ifndef __UBOOT__
  83. static void am35x_musb_enable(struct musb *musb)
  84. #else
  85. static int am35x_musb_enable(struct musb *musb)
  86. #endif
  87. {
  88. void __iomem *reg_base = musb->ctrl_base;
  89. u32 epmask;
  90. /* Workaround: setup IRQs through both register sets. */
  91. epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
  92. ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
  93. musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
  94. musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
  95. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  96. if (is_otg_enabled(musb))
  97. musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
  98. AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
  99. #ifdef __UBOOT__
  100. return 0;
  101. #endif
  102. }
  103. /*
  104. * am35x_musb_disable - disable HDRC and flush interrupts
  105. */
  106. static void am35x_musb_disable(struct musb *musb)
  107. {
  108. void __iomem *reg_base = musb->ctrl_base;
  109. musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
  110. musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
  111. AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
  112. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  113. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  114. }
  115. #ifndef __UBOOT__
  116. #define portstate(stmt) stmt
  117. static void am35x_musb_set_vbus(struct musb *musb, int is_on)
  118. {
  119. WARN_ON(is_on && is_peripheral_active(musb));
  120. }
  121. #define POLL_SECONDS 2
  122. static struct timer_list otg_workaround;
  123. static void otg_timer(unsigned long _musb)
  124. {
  125. struct musb *musb = (void *)_musb;
  126. void __iomem *mregs = musb->mregs;
  127. u8 devctl;
  128. unsigned long flags;
  129. /*
  130. * We poll because AM35x's won't expose several OTG-critical
  131. * status change events (from the transceiver) otherwise.
  132. */
  133. devctl = musb_readb(mregs, MUSB_DEVCTL);
  134. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  135. otg_state_string(musb->xceiv->state));
  136. spin_lock_irqsave(&musb->lock, flags);
  137. switch (musb->xceiv->state) {
  138. case OTG_STATE_A_WAIT_BCON:
  139. devctl &= ~MUSB_DEVCTL_SESSION;
  140. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  141. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  142. if (devctl & MUSB_DEVCTL_BDEVICE) {
  143. musb->xceiv->state = OTG_STATE_B_IDLE;
  144. MUSB_DEV_MODE(musb);
  145. } else {
  146. musb->xceiv->state = OTG_STATE_A_IDLE;
  147. MUSB_HST_MODE(musb);
  148. }
  149. break;
  150. case OTG_STATE_A_WAIT_VFALL:
  151. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  152. musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
  153. MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
  154. break;
  155. case OTG_STATE_B_IDLE:
  156. if (!is_peripheral_enabled(musb))
  157. break;
  158. devctl = musb_readb(mregs, MUSB_DEVCTL);
  159. if (devctl & MUSB_DEVCTL_BDEVICE)
  160. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  161. else
  162. musb->xceiv->state = OTG_STATE_A_IDLE;
  163. break;
  164. default:
  165. break;
  166. }
  167. spin_unlock_irqrestore(&musb->lock, flags);
  168. }
  169. static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
  170. {
  171. static unsigned long last_timer;
  172. if (!is_otg_enabled(musb))
  173. return;
  174. if (timeout == 0)
  175. timeout = jiffies + msecs_to_jiffies(3);
  176. /* Never idle if active, or when VBUS timeout is not set as host */
  177. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  178. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  179. dev_dbg(musb->controller, "%s active, deleting timer\n",
  180. otg_state_string(musb->xceiv->state));
  181. del_timer(&otg_workaround);
  182. last_timer = jiffies;
  183. return;
  184. }
  185. if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
  186. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
  187. return;
  188. }
  189. last_timer = timeout;
  190. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  191. otg_state_string(musb->xceiv->state),
  192. jiffies_to_msecs(timeout - jiffies));
  193. mod_timer(&otg_workaround, timeout);
  194. }
  195. #endif
  196. static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
  197. {
  198. struct musb *musb = hci;
  199. void __iomem *reg_base = musb->ctrl_base;
  200. #ifndef __UBOOT__
  201. struct device *dev = musb->controller;
  202. struct musb_hdrc_platform_data *plat = dev->platform_data;
  203. struct omap_musb_board_data *data = plat->board_data;
  204. struct usb_otg *otg = musb->xceiv->otg;
  205. #else
  206. struct omap_musb_board_data *data =
  207. (struct omap_musb_board_data *)musb->controller;
  208. #endif
  209. unsigned long flags;
  210. irqreturn_t ret = IRQ_NONE;
  211. u32 epintr, usbintr;
  212. #ifdef __UBOOT__
  213. /*
  214. * It seems that on AM35X interrupt registers can be updated
  215. * before core registers. This confuses the code.
  216. * As a workaround add a small delay here.
  217. */
  218. udelay(10);
  219. #endif
  220. spin_lock_irqsave(&musb->lock, flags);
  221. /* Get endpoint interrupts */
  222. epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
  223. if (epintr) {
  224. musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
  225. musb->int_rx =
  226. (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
  227. musb->int_tx =
  228. (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
  229. }
  230. /* Get usb core interrupts */
  231. usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
  232. if (!usbintr && !epintr)
  233. goto eoi;
  234. if (usbintr) {
  235. musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
  236. musb->int_usb =
  237. (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
  238. }
  239. #ifndef __UBOOT__
  240. /*
  241. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  242. * AM35x's missing ID change IRQ. We need an ID change IRQ to
  243. * switch appropriately between halves of the OTG state machine.
  244. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  245. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  246. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  247. */
  248. if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
  249. int drvvbus = musb_readl(reg_base, USB_STAT_REG);
  250. void __iomem *mregs = musb->mregs;
  251. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  252. int err;
  253. err = is_host_enabled(musb) && (musb->int_usb &
  254. MUSB_INTR_VBUSERROR);
  255. if (err) {
  256. /*
  257. * The Mentor core doesn't debounce VBUS as needed
  258. * to cope with device connect current spikes. This
  259. * means it's not uncommon for bus-powered devices
  260. * to get VBUS errors during enumeration.
  261. *
  262. * This is a workaround, but newer RTL from Mentor
  263. * seems to allow a better one: "re"-starting sessions
  264. * without waiting for VBUS to stop registering in
  265. * devctl.
  266. */
  267. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  268. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  269. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  270. WARNING("VBUS error workaround (delay coming)\n");
  271. } else if (is_host_enabled(musb) && drvvbus) {
  272. MUSB_HST_MODE(musb);
  273. otg->default_a = 1;
  274. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  275. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  276. del_timer(&otg_workaround);
  277. } else {
  278. musb->is_active = 0;
  279. MUSB_DEV_MODE(musb);
  280. otg->default_a = 0;
  281. musb->xceiv->state = OTG_STATE_B_IDLE;
  282. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  283. }
  284. /* NOTE: this must complete power-on within 100 ms. */
  285. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  286. drvvbus ? "on" : "off",
  287. otg_state_string(musb->xceiv->state),
  288. err ? " ERROR" : "",
  289. devctl);
  290. ret = IRQ_HANDLED;
  291. }
  292. #endif
  293. if (musb->int_tx || musb->int_rx || musb->int_usb)
  294. ret |= musb_interrupt(musb);
  295. eoi:
  296. /* EOI needs to be written for the IRQ to be re-asserted. */
  297. if (ret == IRQ_HANDLED || epintr || usbintr) {
  298. /* clear level interrupt */
  299. if (data->clear_irq)
  300. data->clear_irq(data->dev);
  301. /* write EOI */
  302. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  303. }
  304. #ifndef __UBOOT__
  305. /* Poll for ID change */
  306. if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
  307. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  308. #endif
  309. spin_unlock_irqrestore(&musb->lock, flags);
  310. return ret;
  311. }
  312. #ifndef __UBOOT__
  313. static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
  314. {
  315. struct device *dev = musb->controller;
  316. struct musb_hdrc_platform_data *plat = dev->platform_data;
  317. struct omap_musb_board_data *data = plat->board_data;
  318. int retval = 0;
  319. if (data->set_mode)
  320. data->set_mode(musb_mode);
  321. else
  322. retval = -EIO;
  323. return retval;
  324. }
  325. #endif
  326. static int am35x_musb_init(struct musb *musb)
  327. {
  328. #ifndef __UBOOT__
  329. struct device *dev = musb->controller;
  330. struct musb_hdrc_platform_data *plat = dev->platform_data;
  331. struct omap_musb_board_data *data = plat->board_data;
  332. #else
  333. struct omap_musb_board_data *data =
  334. (struct omap_musb_board_data *)musb->controller;
  335. #endif
  336. void __iomem *reg_base = musb->ctrl_base;
  337. u32 rev;
  338. musb->mregs += USB_MENTOR_CORE_OFFSET;
  339. /* Returns zero if e.g. not clocked */
  340. rev = musb_readl(reg_base, USB_REVISION_REG);
  341. if (!rev)
  342. return -ENODEV;
  343. #ifndef __UBOOT__
  344. usb_nop_xceiv_register();
  345. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  346. if (IS_ERR_OR_NULL(musb->xceiv))
  347. return -ENODEV;
  348. if (is_host_enabled(musb))
  349. setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
  350. #endif
  351. /* Reset the musb */
  352. if (data->reset)
  353. data->reset(data->dev);
  354. /* Reset the controller */
  355. musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
  356. /* Start the on-chip PHY and its PLL. */
  357. if (data && data->set_phy_power)
  358. data->set_phy_power(data->dev, 1);
  359. msleep(5);
  360. musb->isr = am35x_musb_interrupt;
  361. /* clear level interrupt */
  362. if (data->clear_irq)
  363. data->clear_irq(data->dev);
  364. return 0;
  365. }
  366. static int am35x_musb_exit(struct musb *musb)
  367. {
  368. #ifndef __UBOOT__
  369. struct device *dev = musb->controller;
  370. struct musb_hdrc_platform_data *plat = dev->platform_data;
  371. struct omap_musb_board_data *data = plat->board_data;
  372. #else
  373. struct omap_musb_board_data *data =
  374. (struct omap_musb_board_data *)musb->controller;
  375. #endif
  376. #ifndef __UBOOT__
  377. if (is_host_enabled(musb))
  378. del_timer_sync(&otg_workaround);
  379. #endif
  380. /* Shutdown the on-chip PHY and its PLL. */
  381. if (data && data->set_phy_power)
  382. data->set_phy_power(data->dev, 0);
  383. #ifndef __UBOOT__
  384. usb_put_phy(musb->xceiv);
  385. usb_nop_xceiv_unregister();
  386. #endif
  387. return 0;
  388. }
  389. /* AM35x supports only 32bit read operation */
  390. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  391. {
  392. void __iomem *fifo = hw_ep->fifo;
  393. u32 val;
  394. int i;
  395. /* Read for 32bit-aligned destination address */
  396. if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
  397. readsl(fifo, dst, len >> 2);
  398. dst += len & ~0x03;
  399. len &= 0x03;
  400. }
  401. /*
  402. * Now read the remaining 1 to 3 byte or complete length if
  403. * unaligned address.
  404. */
  405. if (len > 4) {
  406. for (i = 0; i < (len >> 2); i++) {
  407. *(u32 *) dst = musb_readl(fifo, 0);
  408. dst += 4;
  409. }
  410. len &= 0x03;
  411. }
  412. if (len > 0) {
  413. val = musb_readl(fifo, 0);
  414. memcpy(dst, &val, len);
  415. }
  416. }
  417. #ifndef __UBOOT__
  418. static const struct musb_platform_ops am35x_ops = {
  419. #else
  420. const struct musb_platform_ops am35x_ops = {
  421. #endif
  422. .init = am35x_musb_init,
  423. .exit = am35x_musb_exit,
  424. .enable = am35x_musb_enable,
  425. .disable = am35x_musb_disable,
  426. #ifndef __UBOOT__
  427. .set_mode = am35x_musb_set_mode,
  428. .try_idle = am35x_musb_try_idle,
  429. .set_vbus = am35x_musb_set_vbus,
  430. #endif
  431. };
  432. #ifndef __UBOOT__
  433. static u64 am35x_dmamask = DMA_BIT_MASK(32);
  434. static int __devinit am35x_probe(struct platform_device *pdev)
  435. {
  436. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  437. struct platform_device *musb;
  438. struct am35x_glue *glue;
  439. struct clk *phy_clk;
  440. struct clk *clk;
  441. int ret = -ENOMEM;
  442. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  443. if (!glue) {
  444. dev_err(&pdev->dev, "failed to allocate glue context\n");
  445. goto err0;
  446. }
  447. musb = platform_device_alloc("musb-hdrc", -1);
  448. if (!musb) {
  449. dev_err(&pdev->dev, "failed to allocate musb device\n");
  450. goto err1;
  451. }
  452. phy_clk = clk_get(&pdev->dev, "fck");
  453. if (IS_ERR(phy_clk)) {
  454. dev_err(&pdev->dev, "failed to get PHY clock\n");
  455. ret = PTR_ERR(phy_clk);
  456. goto err2;
  457. }
  458. clk = clk_get(&pdev->dev, "ick");
  459. if (IS_ERR(clk)) {
  460. dev_err(&pdev->dev, "failed to get clock\n");
  461. ret = PTR_ERR(clk);
  462. goto err3;
  463. }
  464. ret = clk_enable(phy_clk);
  465. if (ret) {
  466. dev_err(&pdev->dev, "failed to enable PHY clock\n");
  467. goto err4;
  468. }
  469. ret = clk_enable(clk);
  470. if (ret) {
  471. dev_err(&pdev->dev, "failed to enable clock\n");
  472. goto err5;
  473. }
  474. musb->dev.parent = &pdev->dev;
  475. musb->dev.dma_mask = &am35x_dmamask;
  476. musb->dev.coherent_dma_mask = am35x_dmamask;
  477. glue->dev = &pdev->dev;
  478. glue->musb = musb;
  479. glue->phy_clk = phy_clk;
  480. glue->clk = clk;
  481. pdata->platform_ops = &am35x_ops;
  482. platform_set_drvdata(pdev, glue);
  483. ret = platform_device_add_resources(musb, pdev->resource,
  484. pdev->num_resources);
  485. if (ret) {
  486. dev_err(&pdev->dev, "failed to add resources\n");
  487. goto err6;
  488. }
  489. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  490. if (ret) {
  491. dev_err(&pdev->dev, "failed to add platform_data\n");
  492. goto err6;
  493. }
  494. ret = platform_device_add(musb);
  495. if (ret) {
  496. dev_err(&pdev->dev, "failed to register musb device\n");
  497. goto err6;
  498. }
  499. return 0;
  500. err6:
  501. clk_disable(clk);
  502. err5:
  503. clk_disable(phy_clk);
  504. err4:
  505. clk_put(clk);
  506. err3:
  507. clk_put(phy_clk);
  508. err2:
  509. platform_device_put(musb);
  510. err1:
  511. kfree(glue);
  512. err0:
  513. return ret;
  514. }
  515. static int __devexit am35x_remove(struct platform_device *pdev)
  516. {
  517. struct am35x_glue *glue = platform_get_drvdata(pdev);
  518. platform_device_del(glue->musb);
  519. platform_device_put(glue->musb);
  520. clk_disable(glue->clk);
  521. clk_disable(glue->phy_clk);
  522. clk_put(glue->clk);
  523. clk_put(glue->phy_clk);
  524. kfree(glue);
  525. return 0;
  526. }
  527. #ifdef CONFIG_PM
  528. static int am35x_suspend(struct device *dev)
  529. {
  530. struct am35x_glue *glue = dev_get_drvdata(dev);
  531. struct musb_hdrc_platform_data *plat = dev->platform_data;
  532. struct omap_musb_board_data *data = plat->board_data;
  533. /* Shutdown the on-chip PHY and its PLL. */
  534. if (data && data->set_phy_power)
  535. data->set_phy_power(data->dev, 0);
  536. clk_disable(glue->phy_clk);
  537. clk_disable(glue->clk);
  538. return 0;
  539. }
  540. static int am35x_resume(struct device *dev)
  541. {
  542. struct am35x_glue *glue = dev_get_drvdata(dev);
  543. struct musb_hdrc_platform_data *plat = dev->platform_data;
  544. struct omap_musb_board_data *data = plat->board_data;
  545. int ret;
  546. /* Start the on-chip PHY and its PLL. */
  547. if (data && data->set_phy_power)
  548. data->set_phy_power(data->dev, 1);
  549. ret = clk_enable(glue->phy_clk);
  550. if (ret) {
  551. dev_err(dev, "failed to enable PHY clock\n");
  552. return ret;
  553. }
  554. ret = clk_enable(glue->clk);
  555. if (ret) {
  556. dev_err(dev, "failed to enable clock\n");
  557. return ret;
  558. }
  559. return 0;
  560. }
  561. static struct dev_pm_ops am35x_pm_ops = {
  562. .suspend = am35x_suspend,
  563. .resume = am35x_resume,
  564. };
  565. #define DEV_PM_OPS &am35x_pm_ops
  566. #else
  567. #define DEV_PM_OPS NULL
  568. #endif
  569. static struct platform_driver am35x_driver = {
  570. .probe = am35x_probe,
  571. .remove = __devexit_p(am35x_remove),
  572. .driver = {
  573. .name = "musb-am35x",
  574. .pm = DEV_PM_OPS,
  575. },
  576. };
  577. MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
  578. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  579. MODULE_LICENSE("GPL v2");
  580. static int __init am35x_init(void)
  581. {
  582. return platform_driver_register(&am35x_driver);
  583. }
  584. module_init(am35x_init);
  585. static void __exit am35x_exit(void)
  586. {
  587. platform_driver_unregister(&am35x_driver);
  588. }
  589. module_exit(am35x_exit);
  590. #endif