dwc2_udc_otg_xfer_dma.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
  4. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  5. *
  6. * Copyright (C) 2009 for Samsung Electronics
  7. *
  8. * BSP Support for Samsung's UDC driver
  9. * available at:
  10. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11. *
  12. * State machine bugfixes:
  13. * Marek Szyprowski <m.szyprowski@samsung.com>
  14. *
  15. * Ported to u-boot:
  16. * Marek Szyprowski <m.szyprowski@samsung.com>
  17. * Lukasz Majewski <l.majewski@samsumg.com>
  18. */
  19. #include <common.h>
  20. #include <cpu_func.h>
  21. #include <log.h>
  22. #include <linux/bug.h>
  23. static u8 clear_feature_num;
  24. int clear_feature_flag;
  25. /* Bulk-Only Mass Storage Reset (class-specific request) */
  26. #define GET_MAX_LUN_REQUEST 0xFE
  27. #define BOT_RESET_REQUEST 0xFF
  28. static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
  29. {
  30. u32 ep_ctrl;
  31. writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
  32. writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  33. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  34. writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  35. &reg->in_endp[EP0_CON].diepctl);
  36. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  37. __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  38. dev->ep0state = WAIT_FOR_IN_COMPLETE;
  39. }
  40. static void dwc2_udc_pre_setup(void)
  41. {
  42. u32 ep_ctrl;
  43. debug_cond(DEBUG_IN_EP,
  44. "%s : Prepare Setup packets.\n", __func__);
  45. writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  46. &reg->out_endp[EP0_CON].doeptsiz);
  47. writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  48. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  49. writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  50. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  51. __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  52. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  53. __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  54. }
  55. static inline void dwc2_ep0_complete_out(void)
  56. {
  57. u32 ep_ctrl;
  58. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  59. __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  60. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  61. __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  62. debug_cond(DEBUG_IN_EP,
  63. "%s : Prepare Complete Out packet.\n", __func__);
  64. writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  65. &reg->out_endp[EP0_CON].doeptsiz);
  66. writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  67. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  68. writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  69. &reg->out_endp[EP0_CON].doepctl);
  70. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  71. __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  72. debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  73. __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  74. }
  75. static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
  76. {
  77. u32 *buf, ctrl;
  78. u32 length, pktcnt;
  79. u32 ep_num = ep_index(ep);
  80. buf = req->req.buf + req->req.actual;
  81. length = min_t(u32, req->req.length - req->req.actual,
  82. ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
  83. ep->len = length;
  84. ep->dma_buf = buf;
  85. if (ep_num == EP0_CON || length == 0)
  86. pktcnt = 1;
  87. else
  88. pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
  89. ctrl = readl(&reg->out_endp[ep_num].doepctl);
  90. invalidate_dcache_range((unsigned long) ep->dma_buf,
  91. (unsigned long) ep->dma_buf +
  92. ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
  93. writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->out_endp[ep_num].doepdma);
  94. writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
  95. &reg->out_endp[ep_num].doeptsiz);
  96. writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
  97. debug_cond(DEBUG_OUT_EP != 0,
  98. "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
  99. "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
  100. "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
  101. __func__, ep_num,
  102. readl(&reg->out_endp[ep_num].doepdma),
  103. readl(&reg->out_endp[ep_num].doeptsiz),
  104. readl(&reg->out_endp[ep_num].doepctl),
  105. buf, pktcnt, length);
  106. return 0;
  107. }
  108. static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
  109. {
  110. u32 *buf, ctrl = 0;
  111. u32 length, pktcnt;
  112. u32 ep_num = ep_index(ep);
  113. buf = req->req.buf + req->req.actual;
  114. length = req->req.length - req->req.actual;
  115. if (ep_num == EP0_CON)
  116. length = min(length, (u32)ep_maxpacket(ep));
  117. ep->len = length;
  118. ep->dma_buf = buf;
  119. flush_dcache_range((unsigned long) ep->dma_buf,
  120. (unsigned long) ep->dma_buf +
  121. ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
  122. if (length == 0)
  123. pktcnt = 1;
  124. else
  125. pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
  126. /* Flush the endpoint's Tx FIFO */
  127. writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
  128. writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
  129. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  130. ;
  131. writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->in_endp[ep_num].diepdma);
  132. writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
  133. &reg->in_endp[ep_num].dieptsiz);
  134. ctrl = readl(&reg->in_endp[ep_num].diepctl);
  135. /* Write the FIFO number to be used for this endpoint */
  136. ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
  137. ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
  138. /* Clear reserved (Next EP) bits */
  139. ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
  140. writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
  141. debug_cond(DEBUG_IN_EP,
  142. "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
  143. "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
  144. "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
  145. __func__, ep_num,
  146. readl(&reg->in_endp[ep_num].diepdma),
  147. readl(&reg->in_endp[ep_num].dieptsiz),
  148. readl(&reg->in_endp[ep_num].diepctl),
  149. buf, pktcnt, length);
  150. return length;
  151. }
  152. static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
  153. {
  154. struct dwc2_ep *ep = &dev->ep[ep_num];
  155. struct dwc2_request *req = NULL;
  156. u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
  157. if (list_empty(&ep->queue)) {
  158. debug_cond(DEBUG_OUT_EP != 0,
  159. "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
  160. __func__, ep_num);
  161. return;
  162. }
  163. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  164. ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
  165. if (ep_num == EP0_CON)
  166. xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
  167. else
  168. xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
  169. xfer_size = ep->len - xfer_size;
  170. /*
  171. * NOTE:
  172. *
  173. * Please be careful with proper buffer allocation for USB request,
  174. * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
  175. * with starting address, but also its size shall be a cache line
  176. * multiplication.
  177. *
  178. * This will prevent from corruption of data allocated immediatelly
  179. * before or after the buffer.
  180. *
  181. * For armv7, the cache_v7.c provides proper code to emit "ERROR"
  182. * message to warn users.
  183. */
  184. invalidate_dcache_range((unsigned long) ep->dma_buf,
  185. (unsigned long) ep->dma_buf +
  186. ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
  187. req->req.actual += min(xfer_size, req->req.length - req->req.actual);
  188. is_short = !!(xfer_size % ep->ep.maxpacket);
  189. debug_cond(DEBUG_OUT_EP != 0,
  190. "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
  191. "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
  192. __func__, ep_num, req->req.actual, req->req.length,
  193. is_short, ep_tsr, req->req.length - req->req.actual);
  194. if (is_short || req->req.actual == req->req.length) {
  195. if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
  196. debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
  197. dwc2_udc_ep0_zlp(dev);
  198. /* packet will be completed in complete_tx() */
  199. dev->ep0state = WAIT_FOR_IN_COMPLETE;
  200. } else {
  201. done(ep, req, 0);
  202. if (!list_empty(&ep->queue)) {
  203. req = list_entry(ep->queue.next,
  204. struct dwc2_request, queue);
  205. debug_cond(DEBUG_OUT_EP != 0,
  206. "%s: Next Rx request start...\n",
  207. __func__);
  208. setdma_rx(ep, req);
  209. }
  210. }
  211. } else
  212. setdma_rx(ep, req);
  213. }
  214. static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
  215. {
  216. struct dwc2_ep *ep = &dev->ep[ep_num];
  217. struct dwc2_request *req;
  218. u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
  219. u32 last;
  220. if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
  221. dev->ep0state = WAIT_FOR_OUT_COMPLETE;
  222. dwc2_ep0_complete_out();
  223. return;
  224. }
  225. if (list_empty(&ep->queue)) {
  226. debug_cond(DEBUG_IN_EP,
  227. "%s: TX DMA done : NULL REQ on IN EP-%d\n",
  228. __func__, ep_num);
  229. return;
  230. }
  231. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  232. ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
  233. xfer_size = ep->len;
  234. is_short = (xfer_size < ep->ep.maxpacket);
  235. req->req.actual += min(xfer_size, req->req.length - req->req.actual);
  236. debug_cond(DEBUG_IN_EP,
  237. "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
  238. "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
  239. __func__, ep_num, req->req.actual, req->req.length,
  240. is_short, ep_tsr, req->req.length - req->req.actual);
  241. if (ep_num == 0) {
  242. if (dev->ep0state == DATA_STATE_XMIT) {
  243. debug_cond(DEBUG_IN_EP,
  244. "%s: ep_num = %d, ep0stat =="
  245. "DATA_STATE_XMIT\n",
  246. __func__, ep_num);
  247. last = write_fifo_ep0(ep, req);
  248. if (last)
  249. dev->ep0state = WAIT_FOR_COMPLETE;
  250. } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
  251. debug_cond(DEBUG_IN_EP,
  252. "%s: ep_num = %d, completing request\n",
  253. __func__, ep_num);
  254. done(ep, req, 0);
  255. dev->ep0state = WAIT_FOR_SETUP;
  256. } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
  257. debug_cond(DEBUG_IN_EP,
  258. "%s: ep_num = %d, completing request\n",
  259. __func__, ep_num);
  260. done(ep, req, 0);
  261. dev->ep0state = WAIT_FOR_OUT_COMPLETE;
  262. dwc2_ep0_complete_out();
  263. } else {
  264. debug_cond(DEBUG_IN_EP,
  265. "%s: ep_num = %d, invalid ep state\n",
  266. __func__, ep_num);
  267. }
  268. return;
  269. }
  270. if (req->req.actual == req->req.length)
  271. done(ep, req, 0);
  272. if (!list_empty(&ep->queue)) {
  273. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  274. debug_cond(DEBUG_IN_EP,
  275. "%s: Next Tx request start...\n", __func__);
  276. setdma_tx(ep, req);
  277. }
  278. }
  279. static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
  280. {
  281. struct dwc2_ep *ep = &dev->ep[ep_num];
  282. struct dwc2_request *req;
  283. debug_cond(DEBUG_IN_EP,
  284. "%s: Check queue, ep_num = %d\n", __func__, ep_num);
  285. if (!list_empty(&ep->queue)) {
  286. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  287. debug_cond(DEBUG_IN_EP,
  288. "%s: Next Tx request(0x%p) start...\n",
  289. __func__, req);
  290. if (ep_is_in(ep))
  291. setdma_tx(ep, req);
  292. else
  293. setdma_rx(ep, req);
  294. } else {
  295. debug_cond(DEBUG_IN_EP,
  296. "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
  297. return;
  298. }
  299. }
  300. static void process_ep_in_intr(struct dwc2_udc *dev)
  301. {
  302. u32 ep_intr, ep_intr_status;
  303. u8 ep_num = 0;
  304. ep_intr = readl(&reg->daint);
  305. debug_cond(DEBUG_IN_EP,
  306. "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
  307. ep_intr &= DAINT_MASK;
  308. while (ep_intr) {
  309. if (ep_intr & DAINT_IN_EP_INT(1)) {
  310. ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
  311. debug_cond(DEBUG_IN_EP,
  312. "\tEP%d-IN : DIEPINT = 0x%x\n",
  313. ep_num, ep_intr_status);
  314. /* Interrupt Clear */
  315. writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
  316. if (ep_intr_status & TRANSFER_DONE) {
  317. complete_tx(dev, ep_num);
  318. if (ep_num == 0) {
  319. if (dev->ep0state ==
  320. WAIT_FOR_IN_COMPLETE)
  321. dev->ep0state = WAIT_FOR_SETUP;
  322. if (dev->ep0state == WAIT_FOR_SETUP)
  323. dwc2_udc_pre_setup();
  324. /* continue transfer after
  325. set_clear_halt for DMA mode */
  326. if (clear_feature_flag == 1) {
  327. dwc2_udc_check_tx_queue(dev,
  328. clear_feature_num);
  329. clear_feature_flag = 0;
  330. }
  331. }
  332. }
  333. }
  334. ep_num++;
  335. ep_intr >>= 1;
  336. }
  337. }
  338. static void process_ep_out_intr(struct dwc2_udc *dev)
  339. {
  340. u32 ep_intr, ep_intr_status;
  341. u8 ep_num = 0;
  342. ep_intr = readl(&reg->daint);
  343. debug_cond(DEBUG_OUT_EP != 0,
  344. "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
  345. __func__, ep_intr);
  346. ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
  347. while (ep_intr) {
  348. if (ep_intr & 0x1) {
  349. ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
  350. debug_cond(DEBUG_OUT_EP != 0,
  351. "\tEP%d-OUT : DOEPINT = 0x%x\n",
  352. ep_num, ep_intr_status);
  353. /* Interrupt Clear */
  354. writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
  355. if (ep_num == 0) {
  356. if (ep_intr_status & TRANSFER_DONE) {
  357. if (dev->ep0state !=
  358. WAIT_FOR_OUT_COMPLETE)
  359. complete_rx(dev, ep_num);
  360. else {
  361. dev->ep0state = WAIT_FOR_SETUP;
  362. dwc2_udc_pre_setup();
  363. }
  364. }
  365. if (ep_intr_status &
  366. CTRL_OUT_EP_SETUP_PHASE_DONE) {
  367. debug_cond(DEBUG_OUT_EP != 0,
  368. "SETUP packet arrived\n");
  369. dwc2_handle_ep0(dev);
  370. }
  371. } else {
  372. if (ep_intr_status & TRANSFER_DONE)
  373. complete_rx(dev, ep_num);
  374. }
  375. }
  376. ep_num++;
  377. ep_intr >>= 1;
  378. }
  379. }
  380. /*
  381. * usb client interrupt handler.
  382. */
  383. static int dwc2_udc_irq(int irq, void *_dev)
  384. {
  385. struct dwc2_udc *dev = _dev;
  386. u32 intr_status, gotgint;
  387. u32 usb_status, gintmsk;
  388. unsigned long flags = 0;
  389. spin_lock_irqsave(&dev->lock, flags);
  390. intr_status = readl(&reg->gintsts);
  391. gintmsk = readl(&reg->gintmsk);
  392. debug_cond(DEBUG_ISR,
  393. "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
  394. "DAINT : 0x%x, DAINTMSK : 0x%x\n",
  395. __func__, intr_status, state_names[dev->ep0state], gintmsk,
  396. readl(&reg->daint), readl(&reg->daintmsk));
  397. if (!intr_status) {
  398. spin_unlock_irqrestore(&dev->lock, flags);
  399. return IRQ_HANDLED;
  400. }
  401. if (intr_status & INT_ENUMDONE) {
  402. debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
  403. writel(INT_ENUMDONE, &reg->gintsts);
  404. usb_status = (readl(&reg->dsts) & 0x6);
  405. if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
  406. debug_cond(DEBUG_ISR,
  407. "\t\tFull Speed Detection\n");
  408. set_max_pktsize(dev, USB_SPEED_FULL);
  409. } else {
  410. debug_cond(DEBUG_ISR,
  411. "\t\tHigh Speed Detection : 0x%x\n",
  412. usb_status);
  413. set_max_pktsize(dev, USB_SPEED_HIGH);
  414. }
  415. }
  416. if (intr_status & INT_EARLY_SUSPEND) {
  417. debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
  418. writel(INT_EARLY_SUSPEND, &reg->gintsts);
  419. }
  420. if (intr_status & INT_SUSPEND) {
  421. usb_status = readl(&reg->dsts);
  422. debug_cond(DEBUG_ISR,
  423. "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
  424. writel(INT_SUSPEND, &reg->gintsts);
  425. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  426. && dev->driver) {
  427. if (dev->driver->suspend)
  428. dev->driver->suspend(&dev->gadget);
  429. }
  430. }
  431. if (intr_status & INT_OTG) {
  432. gotgint = readl(&reg->gotgint);
  433. debug_cond(DEBUG_ISR,
  434. "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
  435. if (gotgint & GOTGINT_SES_END_DET) {
  436. debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
  437. /* Let gadget detect disconnected state */
  438. if (dev->driver->disconnect) {
  439. spin_unlock_irqrestore(&dev->lock, flags);
  440. dev->driver->disconnect(&dev->gadget);
  441. spin_lock_irqsave(&dev->lock, flags);
  442. }
  443. }
  444. writel(gotgint, &reg->gotgint);
  445. }
  446. if (intr_status & INT_RESUME) {
  447. debug_cond(DEBUG_ISR, "\tResume interrupt\n");
  448. writel(INT_RESUME, &reg->gintsts);
  449. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  450. && dev->driver
  451. && dev->driver->resume) {
  452. dev->driver->resume(&dev->gadget);
  453. }
  454. }
  455. if (intr_status & INT_RESET) {
  456. usb_status = readl(&reg->gotgctl);
  457. debug_cond(DEBUG_ISR,
  458. "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
  459. writel(INT_RESET, &reg->gintsts);
  460. if ((usb_status & 0xc0000) == (0x3 << 18)) {
  461. if (reset_available) {
  462. debug_cond(DEBUG_ISR,
  463. "\t\tOTG core got reset (%d)!!\n",
  464. reset_available);
  465. reconfig_usbd(dev);
  466. dev->ep0state = WAIT_FOR_SETUP;
  467. reset_available = 0;
  468. dwc2_udc_pre_setup();
  469. } else
  470. reset_available = 1;
  471. } else {
  472. reset_available = 1;
  473. debug_cond(DEBUG_ISR,
  474. "\t\tRESET handling skipped\n");
  475. }
  476. }
  477. if (intr_status & INT_IN_EP)
  478. process_ep_in_intr(dev);
  479. if (intr_status & INT_OUT_EP)
  480. process_ep_out_intr(dev);
  481. spin_unlock_irqrestore(&dev->lock, flags);
  482. return IRQ_HANDLED;
  483. }
  484. /** Queue one request
  485. * Kickstart transfer if needed
  486. */
  487. static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
  488. gfp_t gfp_flags)
  489. {
  490. struct dwc2_request *req;
  491. struct dwc2_ep *ep;
  492. struct dwc2_udc *dev;
  493. unsigned long flags = 0;
  494. u32 ep_num, gintsts;
  495. req = container_of(_req, struct dwc2_request, req);
  496. if (unlikely(!_req || !_req->complete || !_req->buf
  497. || !list_empty(&req->queue))) {
  498. debug("%s: bad params\n", __func__);
  499. return -EINVAL;
  500. }
  501. ep = container_of(_ep, struct dwc2_ep, ep);
  502. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  503. debug("%s: bad ep: %s, %d, %p\n", __func__,
  504. ep->ep.name, !ep->desc, _ep);
  505. return -EINVAL;
  506. }
  507. ep_num = ep_index(ep);
  508. dev = ep->dev;
  509. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  510. debug("%s: bogus device state %p\n", __func__, dev->driver);
  511. return -ESHUTDOWN;
  512. }
  513. spin_lock_irqsave(&dev->lock, flags);
  514. _req->status = -EINPROGRESS;
  515. _req->actual = 0;
  516. /* kickstart this i/o queue? */
  517. debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
  518. "Q empty = %d, stopped = %d\n",
  519. __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
  520. _req, _req->length, _req->buf,
  521. list_empty(&ep->queue), ep->stopped);
  522. #ifdef DEBUG
  523. {
  524. int i, len = _req->length;
  525. printf("pkt = ");
  526. if (len > 64)
  527. len = 64;
  528. for (i = 0; i < len; i++) {
  529. printf("%02x", ((u8 *)_req->buf)[i]);
  530. if ((i & 7) == 7)
  531. printf(" ");
  532. }
  533. printf("\n");
  534. }
  535. #endif
  536. if (list_empty(&ep->queue) && !ep->stopped) {
  537. if (ep_num == 0) {
  538. /* EP0 */
  539. list_add_tail(&req->queue, &ep->queue);
  540. dwc2_ep0_kick(dev, ep);
  541. req = 0;
  542. } else if (ep_is_in(ep)) {
  543. gintsts = readl(&reg->gintsts);
  544. debug_cond(DEBUG_IN_EP,
  545. "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
  546. __func__, gintsts);
  547. setdma_tx(ep, req);
  548. } else {
  549. gintsts = readl(&reg->gintsts);
  550. debug_cond(DEBUG_OUT_EP != 0,
  551. "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
  552. __func__, gintsts);
  553. setdma_rx(ep, req);
  554. }
  555. }
  556. /* pio or dma irq handler advances the queue. */
  557. if (likely(req != 0))
  558. list_add_tail(&req->queue, &ep->queue);
  559. spin_unlock_irqrestore(&dev->lock, flags);
  560. return 0;
  561. }
  562. /****************************************************************/
  563. /* End Point 0 related functions */
  564. /****************************************************************/
  565. /* return: 0 = still running, 1 = completed, negative = errno */
  566. static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
  567. {
  568. u32 max;
  569. unsigned count;
  570. int is_last;
  571. max = ep_maxpacket(ep);
  572. debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
  573. count = setdma_tx(ep, req);
  574. /* last packet is usually short (or a zlp) */
  575. if (likely(count != max))
  576. is_last = 1;
  577. else {
  578. if (likely(req->req.length != req->req.actual + count)
  579. || req->req.zero)
  580. is_last = 0;
  581. else
  582. is_last = 1;
  583. }
  584. debug_cond(DEBUG_EP0 != 0,
  585. "%s: wrote %s %d bytes%s %d left %p\n", __func__,
  586. ep->ep.name, count,
  587. is_last ? "/L" : "",
  588. req->req.length - req->req.actual - count, req);
  589. /* requests complete when all IN data is in the FIFO */
  590. if (is_last) {
  591. ep->dev->ep0state = WAIT_FOR_SETUP;
  592. return 1;
  593. }
  594. return 0;
  595. }
  596. static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
  597. {
  598. invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
  599. ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
  600. debug_cond(DEBUG_EP0 != 0,
  601. "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
  602. max, ep_index(ep), cp);
  603. return max;
  604. }
  605. /**
  606. * udc_set_address - set the USB address for this device
  607. * @address:
  608. *
  609. * Called from control endpoint function
  610. * after it decodes a set address setup packet.
  611. */
  612. static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
  613. {
  614. u32 ctrl = readl(&reg->dcfg);
  615. writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
  616. dwc2_udc_ep0_zlp(dev);
  617. debug_cond(DEBUG_EP0 != 0,
  618. "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
  619. __func__, address, readl(&reg->dcfg));
  620. dev->usb_address = address;
  621. }
  622. static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
  623. {
  624. struct dwc2_udc *dev;
  625. u32 ep_ctrl = 0;
  626. dev = ep->dev;
  627. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  628. /* set the disable and stall bits */
  629. if (ep_ctrl & DEPCTL_EPENA)
  630. ep_ctrl |= DEPCTL_EPDIS;
  631. ep_ctrl |= DEPCTL_STALL;
  632. writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
  633. debug_cond(DEBUG_EP0 != 0,
  634. "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
  635. __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
  636. /*
  637. * The application can only set this bit, and the core clears it,
  638. * when a SETUP token is received for this endpoint
  639. */
  640. dev->ep0state = WAIT_FOR_SETUP;
  641. dwc2_udc_pre_setup();
  642. }
  643. static void dwc2_ep0_read(struct dwc2_udc *dev)
  644. {
  645. struct dwc2_request *req;
  646. struct dwc2_ep *ep = &dev->ep[0];
  647. if (!list_empty(&ep->queue)) {
  648. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  649. } else {
  650. debug("%s: ---> BUG\n", __func__);
  651. BUG();
  652. return;
  653. }
  654. debug_cond(DEBUG_EP0 != 0,
  655. "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
  656. __func__, req, req->req.length, req->req.actual);
  657. if (req->req.length == 0) {
  658. /* zlp for Set_configuration, Set_interface,
  659. * or Bulk-Only mass storge reset */
  660. ep->len = 0;
  661. dwc2_udc_ep0_zlp(dev);
  662. debug_cond(DEBUG_EP0 != 0,
  663. "%s: req.length = 0, bRequest = %d\n",
  664. __func__, usb_ctrl->bRequest);
  665. return;
  666. }
  667. setdma_rx(ep, req);
  668. }
  669. /*
  670. * DATA_STATE_XMIT
  671. */
  672. static int dwc2_ep0_write(struct dwc2_udc *dev)
  673. {
  674. struct dwc2_request *req;
  675. struct dwc2_ep *ep = &dev->ep[0];
  676. int ret, need_zlp = 0;
  677. if (list_empty(&ep->queue))
  678. req = 0;
  679. else
  680. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  681. if (!req) {
  682. debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
  683. return 0;
  684. }
  685. debug_cond(DEBUG_EP0 != 0,
  686. "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
  687. __func__, req, req->req.length, req->req.actual);
  688. if (req->req.length - req->req.actual == ep0_fifo_size) {
  689. /* Next write will end with the packet size, */
  690. /* so we need Zero-length-packet */
  691. need_zlp = 1;
  692. }
  693. ret = write_fifo_ep0(ep, req);
  694. if ((ret == 1) && !need_zlp) {
  695. /* Last packet */
  696. dev->ep0state = WAIT_FOR_COMPLETE;
  697. debug_cond(DEBUG_EP0 != 0,
  698. "%s: finished, waiting for status\n", __func__);
  699. } else {
  700. dev->ep0state = DATA_STATE_XMIT;
  701. debug_cond(DEBUG_EP0 != 0,
  702. "%s: not finished\n", __func__);
  703. }
  704. return 1;
  705. }
  706. static int dwc2_udc_get_status(struct dwc2_udc *dev,
  707. struct usb_ctrlrequest *crq)
  708. {
  709. u8 ep_num = crq->wIndex & 0x7F;
  710. u16 g_status = 0;
  711. u32 ep_ctrl;
  712. debug_cond(DEBUG_SETUP != 0,
  713. "%s: *** USB_REQ_GET_STATUS\n", __func__);
  714. printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
  715. switch (crq->bRequestType & USB_RECIP_MASK) {
  716. case USB_RECIP_INTERFACE:
  717. g_status = 0;
  718. debug_cond(DEBUG_SETUP != 0,
  719. "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
  720. g_status);
  721. break;
  722. case USB_RECIP_DEVICE:
  723. g_status = 0x1; /* Self powered */
  724. debug_cond(DEBUG_SETUP != 0,
  725. "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
  726. g_status);
  727. break;
  728. case USB_RECIP_ENDPOINT:
  729. if (crq->wLength > 2) {
  730. debug_cond(DEBUG_SETUP != 0,
  731. "\tGET_STATUS:Not support EP or wLength\n");
  732. return 1;
  733. }
  734. g_status = dev->ep[ep_num].stopped;
  735. debug_cond(DEBUG_SETUP != 0,
  736. "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
  737. g_status);
  738. break;
  739. default:
  740. return 1;
  741. }
  742. memcpy(usb_ctrl, &g_status, sizeof(g_status));
  743. flush_dcache_range((unsigned long) usb_ctrl,
  744. (unsigned long) usb_ctrl +
  745. ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
  746. writel(phys_to_bus(usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
  747. writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
  748. &reg->in_endp[EP0_CON].dieptsiz);
  749. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  750. writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  751. &reg->in_endp[EP0_CON].diepctl);
  752. dev->ep0state = WAIT_FOR_NULL_COMPLETE;
  753. return 0;
  754. }
  755. static void dwc2_udc_set_nak(struct dwc2_ep *ep)
  756. {
  757. u8 ep_num;
  758. u32 ep_ctrl = 0;
  759. ep_num = ep_index(ep);
  760. debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
  761. if (ep_is_in(ep)) {
  762. ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
  763. ep_ctrl |= DEPCTL_SNAK;
  764. writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
  765. debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
  766. __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
  767. } else {
  768. ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
  769. ep_ctrl |= DEPCTL_SNAK;
  770. writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
  771. debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
  772. __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
  773. }
  774. return;
  775. }
  776. static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
  777. {
  778. u8 ep_num;
  779. u32 ep_ctrl = 0;
  780. ep_num = ep_index(ep);
  781. debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
  782. if (ep_is_in(ep)) {
  783. ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
  784. /* set the disable and stall bits */
  785. if (ep_ctrl & DEPCTL_EPENA)
  786. ep_ctrl |= DEPCTL_EPDIS;
  787. ep_ctrl |= DEPCTL_STALL;
  788. writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
  789. debug("%s: set stall, DIEPCTL%d = 0x%x\n",
  790. __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
  791. } else {
  792. ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
  793. /* set the stall bit */
  794. ep_ctrl |= DEPCTL_STALL;
  795. writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
  796. debug("%s: set stall, DOEPCTL%d = 0x%x\n",
  797. __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
  798. }
  799. return;
  800. }
  801. static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
  802. {
  803. u8 ep_num;
  804. u32 ep_ctrl = 0;
  805. ep_num = ep_index(ep);
  806. debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
  807. if (ep_is_in(ep)) {
  808. ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
  809. /* clear stall bit */
  810. ep_ctrl &= ~DEPCTL_STALL;
  811. /*
  812. * USB Spec 9.4.5: For endpoints using data toggle, regardless
  813. * of whether an endpoint has the Halt feature set, a
  814. * ClearFeature(ENDPOINT_HALT) request always results in the
  815. * data toggle being reinitialized to DATA0.
  816. */
  817. if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
  818. || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
  819. ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
  820. }
  821. writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
  822. debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
  823. __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
  824. } else {
  825. ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
  826. /* clear stall bit */
  827. ep_ctrl &= ~DEPCTL_STALL;
  828. if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
  829. || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
  830. ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
  831. }
  832. writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
  833. debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
  834. __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
  835. }
  836. return;
  837. }
  838. static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
  839. {
  840. struct dwc2_ep *ep;
  841. struct dwc2_udc *dev;
  842. unsigned long flags = 0;
  843. u8 ep_num;
  844. ep = container_of(_ep, struct dwc2_ep, ep);
  845. ep_num = ep_index(ep);
  846. if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
  847. ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
  848. debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
  849. return -EINVAL;
  850. }
  851. /* Attempt to halt IN ep will fail if any transfer requests
  852. * are still queue */
  853. if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
  854. debug("%s: %s queue not empty, req = %p\n",
  855. __func__, ep->ep.name,
  856. list_entry(ep->queue.next, struct dwc2_request, queue));
  857. return -EAGAIN;
  858. }
  859. dev = ep->dev;
  860. debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
  861. spin_lock_irqsave(&dev->lock, flags);
  862. if (value == 0) {
  863. ep->stopped = 0;
  864. dwc2_udc_ep_clear_stall(ep);
  865. } else {
  866. if (ep_num == 0)
  867. dev->ep0state = WAIT_FOR_SETUP;
  868. ep->stopped = 1;
  869. dwc2_udc_ep_set_stall(ep);
  870. }
  871. spin_unlock_irqrestore(&dev->lock, flags);
  872. return 0;
  873. }
  874. static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
  875. {
  876. u8 ep_num;
  877. u32 ep_ctrl = 0, daintmsk = 0;
  878. ep_num = ep_index(ep);
  879. /* Read DEPCTLn register */
  880. if (ep_is_in(ep)) {
  881. ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
  882. daintmsk = 1 << ep_num;
  883. } else {
  884. ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
  885. daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
  886. }
  887. debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
  888. __func__, ep_num, ep_ctrl, ep_is_in(ep));
  889. /* If the EP is already active don't change the EP Control
  890. * register. */
  891. if (!(ep_ctrl & DEPCTL_USBACTEP)) {
  892. ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
  893. (ep->bmAttributes << DEPCTL_TYPE_BIT);
  894. ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
  895. (ep->ep.maxpacket << DEPCTL_MPS_BIT);
  896. ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
  897. if (ep_is_in(ep)) {
  898. writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
  899. debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
  900. __func__, ep_num, ep_num,
  901. readl(&reg->in_endp[ep_num].diepctl));
  902. } else {
  903. writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
  904. debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
  905. __func__, ep_num, ep_num,
  906. readl(&reg->out_endp[ep_num].doepctl));
  907. }
  908. }
  909. /* Unmask EP Interrtupt */
  910. writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
  911. debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
  912. }
  913. static int dwc2_udc_clear_feature(struct usb_ep *_ep)
  914. {
  915. struct dwc2_udc *dev;
  916. struct dwc2_ep *ep;
  917. u8 ep_num;
  918. ep = container_of(_ep, struct dwc2_ep, ep);
  919. ep_num = ep_index(ep);
  920. dev = ep->dev;
  921. debug_cond(DEBUG_SETUP != 0,
  922. "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
  923. __func__, ep_num, ep_is_in(ep), clear_feature_flag);
  924. if (usb_ctrl->wLength != 0) {
  925. debug_cond(DEBUG_SETUP != 0,
  926. "\tCLEAR_FEATURE: wLength is not zero.....\n");
  927. return 1;
  928. }
  929. switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
  930. case USB_RECIP_DEVICE:
  931. switch (usb_ctrl->wValue) {
  932. case USB_DEVICE_REMOTE_WAKEUP:
  933. debug_cond(DEBUG_SETUP != 0,
  934. "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
  935. break;
  936. case USB_DEVICE_TEST_MODE:
  937. debug_cond(DEBUG_SETUP != 0,
  938. "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
  939. /** @todo Add CLEAR_FEATURE for TEST modes. */
  940. break;
  941. }
  942. dwc2_udc_ep0_zlp(dev);
  943. break;
  944. case USB_RECIP_ENDPOINT:
  945. debug_cond(DEBUG_SETUP != 0,
  946. "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
  947. usb_ctrl->wValue);
  948. if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
  949. if (ep_num == 0) {
  950. dwc2_udc_ep0_set_stall(ep);
  951. return 0;
  952. }
  953. dwc2_udc_ep0_zlp(dev);
  954. dwc2_udc_ep_clear_stall(ep);
  955. dwc2_udc_ep_activate(ep);
  956. ep->stopped = 0;
  957. clear_feature_num = ep_num;
  958. clear_feature_flag = 1;
  959. }
  960. break;
  961. }
  962. return 0;
  963. }
  964. static int dwc2_udc_set_feature(struct usb_ep *_ep)
  965. {
  966. struct dwc2_udc *dev;
  967. struct dwc2_ep *ep;
  968. u8 ep_num;
  969. ep = container_of(_ep, struct dwc2_ep, ep);
  970. ep_num = ep_index(ep);
  971. dev = ep->dev;
  972. debug_cond(DEBUG_SETUP != 0,
  973. "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
  974. __func__, ep_num);
  975. if (usb_ctrl->wLength != 0) {
  976. debug_cond(DEBUG_SETUP != 0,
  977. "\tSET_FEATURE: wLength is not zero.....\n");
  978. return 1;
  979. }
  980. switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
  981. case USB_RECIP_DEVICE:
  982. switch (usb_ctrl->wValue) {
  983. case USB_DEVICE_REMOTE_WAKEUP:
  984. debug_cond(DEBUG_SETUP != 0,
  985. "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
  986. break;
  987. case USB_DEVICE_B_HNP_ENABLE:
  988. debug_cond(DEBUG_SETUP != 0,
  989. "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
  990. break;
  991. case USB_DEVICE_A_HNP_SUPPORT:
  992. /* RH port supports HNP */
  993. debug_cond(DEBUG_SETUP != 0,
  994. "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
  995. break;
  996. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  997. /* other RH port does */
  998. debug_cond(DEBUG_SETUP != 0,
  999. "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
  1000. break;
  1001. }
  1002. dwc2_udc_ep0_zlp(dev);
  1003. return 0;
  1004. case USB_RECIP_INTERFACE:
  1005. debug_cond(DEBUG_SETUP != 0,
  1006. "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
  1007. break;
  1008. case USB_RECIP_ENDPOINT:
  1009. debug_cond(DEBUG_SETUP != 0,
  1010. "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
  1011. if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
  1012. if (ep_num == 0) {
  1013. dwc2_udc_ep0_set_stall(ep);
  1014. return 0;
  1015. }
  1016. ep->stopped = 1;
  1017. dwc2_udc_ep_set_stall(ep);
  1018. }
  1019. dwc2_udc_ep0_zlp(dev);
  1020. return 0;
  1021. }
  1022. return 1;
  1023. }
  1024. /*
  1025. * WAIT_FOR_SETUP (OUT_PKT_RDY)
  1026. */
  1027. static void dwc2_ep0_setup(struct dwc2_udc *dev)
  1028. {
  1029. struct dwc2_ep *ep = &dev->ep[0];
  1030. int i;
  1031. u8 ep_num;
  1032. /* Nuke all previous transfers */
  1033. nuke(ep, -EPROTO);
  1034. /* read control req from fifo (8 bytes) */
  1035. dwc2_fifo_read(ep, usb_ctrl, 8);
  1036. debug_cond(DEBUG_SETUP != 0,
  1037. "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
  1038. "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
  1039. __func__, usb_ctrl->bRequestType,
  1040. (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
  1041. usb_ctrl->bRequest,
  1042. usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
  1043. #ifdef DEBUG
  1044. {
  1045. int i, len = sizeof(*usb_ctrl);
  1046. char *p = (char *)usb_ctrl;
  1047. printf("pkt = ");
  1048. for (i = 0; i < len; i++) {
  1049. printf("%02x", ((u8 *)p)[i]);
  1050. if ((i & 7) == 7)
  1051. printf(" ");
  1052. }
  1053. printf("\n");
  1054. }
  1055. #endif
  1056. if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
  1057. usb_ctrl->wLength != 1) {
  1058. debug_cond(DEBUG_SETUP != 0,
  1059. "\t%s:GET_MAX_LUN_REQUEST:invalid",
  1060. __func__);
  1061. debug_cond(DEBUG_SETUP != 0,
  1062. "wLength = %d, setup returned\n",
  1063. usb_ctrl->wLength);
  1064. dwc2_udc_ep0_set_stall(ep);
  1065. dev->ep0state = WAIT_FOR_SETUP;
  1066. return;
  1067. } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
  1068. usb_ctrl->wLength != 0) {
  1069. /* Bulk-Only *mass storge reset of class-specific request */
  1070. debug_cond(DEBUG_SETUP != 0,
  1071. "%s:BOT Rest:invalid wLength =%d, setup returned\n",
  1072. __func__, usb_ctrl->wLength);
  1073. dwc2_udc_ep0_set_stall(ep);
  1074. dev->ep0state = WAIT_FOR_SETUP;
  1075. return;
  1076. }
  1077. /* Set direction of EP0 */
  1078. if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
  1079. ep->bEndpointAddress |= USB_DIR_IN;
  1080. } else {
  1081. ep->bEndpointAddress &= ~USB_DIR_IN;
  1082. }
  1083. /* cope with automagic for some standard requests. */
  1084. dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
  1085. == USB_TYPE_STANDARD;
  1086. dev->req_pending = 1;
  1087. /* Handle some SETUP packets ourselves */
  1088. if (dev->req_std) {
  1089. switch (usb_ctrl->bRequest) {
  1090. case USB_REQ_SET_ADDRESS:
  1091. debug_cond(DEBUG_SETUP != 0,
  1092. "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
  1093. __func__, usb_ctrl->wValue);
  1094. if (usb_ctrl->bRequestType
  1095. != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
  1096. break;
  1097. udc_set_address(dev, usb_ctrl->wValue);
  1098. return;
  1099. case USB_REQ_SET_CONFIGURATION:
  1100. debug_cond(DEBUG_SETUP != 0,
  1101. "=====================================\n");
  1102. debug_cond(DEBUG_SETUP != 0,
  1103. "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
  1104. __func__, usb_ctrl->wValue);
  1105. if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
  1106. reset_available = 1;
  1107. break;
  1108. case USB_REQ_GET_DESCRIPTOR:
  1109. debug_cond(DEBUG_SETUP != 0,
  1110. "%s: *** USB_REQ_GET_DESCRIPTOR\n",
  1111. __func__);
  1112. break;
  1113. case USB_REQ_SET_INTERFACE:
  1114. debug_cond(DEBUG_SETUP != 0,
  1115. "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
  1116. __func__, usb_ctrl->wValue);
  1117. if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
  1118. reset_available = 1;
  1119. break;
  1120. case USB_REQ_GET_CONFIGURATION:
  1121. debug_cond(DEBUG_SETUP != 0,
  1122. "%s: *** USB_REQ_GET_CONFIGURATION\n",
  1123. __func__);
  1124. break;
  1125. case USB_REQ_GET_STATUS:
  1126. if (!dwc2_udc_get_status(dev, usb_ctrl))
  1127. return;
  1128. break;
  1129. case USB_REQ_CLEAR_FEATURE:
  1130. ep_num = usb_ctrl->wIndex & 0x7f;
  1131. if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
  1132. return;
  1133. break;
  1134. case USB_REQ_SET_FEATURE:
  1135. ep_num = usb_ctrl->wIndex & 0x7f;
  1136. if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
  1137. return;
  1138. break;
  1139. default:
  1140. debug_cond(DEBUG_SETUP != 0,
  1141. "%s: *** Default of usb_ctrl->bRequest=0x%x"
  1142. "happened.\n", __func__, usb_ctrl->bRequest);
  1143. break;
  1144. }
  1145. }
  1146. if (likely(dev->driver)) {
  1147. /* device-2-host (IN) or no data setup command,
  1148. * process immediately */
  1149. debug_cond(DEBUG_SETUP != 0,
  1150. "%s:usb_ctrlreq will be passed to fsg_setup()\n",
  1151. __func__);
  1152. spin_unlock(&dev->lock);
  1153. i = dev->driver->setup(&dev->gadget, usb_ctrl);
  1154. spin_lock(&dev->lock);
  1155. if (i < 0) {
  1156. /* setup processing failed, force stall */
  1157. dwc2_udc_ep0_set_stall(ep);
  1158. dev->ep0state = WAIT_FOR_SETUP;
  1159. debug_cond(DEBUG_SETUP != 0,
  1160. "\tdev->driver->setup failed (%d),"
  1161. " bRequest = %d\n",
  1162. i, usb_ctrl->bRequest);
  1163. } else if (dev->req_pending) {
  1164. dev->req_pending = 0;
  1165. debug_cond(DEBUG_SETUP != 0,
  1166. "\tdev->req_pending...\n");
  1167. }
  1168. debug_cond(DEBUG_SETUP != 0,
  1169. "\tep0state = %s\n", state_names[dev->ep0state]);
  1170. }
  1171. }
  1172. /*
  1173. * handle ep0 interrupt
  1174. */
  1175. static void dwc2_handle_ep0(struct dwc2_udc *dev)
  1176. {
  1177. if (dev->ep0state == WAIT_FOR_SETUP) {
  1178. debug_cond(DEBUG_OUT_EP != 0,
  1179. "%s: WAIT_FOR_SETUP\n", __func__);
  1180. dwc2_ep0_setup(dev);
  1181. } else {
  1182. debug_cond(DEBUG_OUT_EP != 0,
  1183. "%s: strange state!!(state = %s)\n",
  1184. __func__, state_names[dev->ep0state]);
  1185. }
  1186. }
  1187. static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
  1188. {
  1189. debug_cond(DEBUG_EP0 != 0,
  1190. "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
  1191. if (ep_is_in(ep)) {
  1192. dev->ep0state = DATA_STATE_XMIT;
  1193. dwc2_ep0_write(dev);
  1194. } else {
  1195. dev->ep0state = DATA_STATE_RECV;
  1196. dwc2_ep0_read(dev);
  1197. }
  1198. }