core.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11. * to uboot.
  12. *
  13. * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <malloc.h>
  18. #include <dwc3-uboot.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/devres.h>
  21. #include <linux/bug.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/err.h>
  24. #include <linux/ioport.h>
  25. #include <dm.h>
  26. #include <generic-phy.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "core.h"
  30. #include "gadget.h"
  31. #include "io.h"
  32. #include "linux-compat.h"
  33. static LIST_HEAD(dwc3_list);
  34. /* -------------------------------------------------------------------------- */
  35. static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  36. {
  37. u32 reg;
  38. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  39. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  40. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  41. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  42. }
  43. /**
  44. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  45. * @dwc: pointer to our context structure
  46. */
  47. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  48. {
  49. u32 reg;
  50. /* Before Resetting PHY, put Core in Reset */
  51. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  52. reg |= DWC3_GCTL_CORESOFTRESET;
  53. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  54. /* Assert USB3 PHY reset */
  55. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  56. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  57. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  58. /* Assert USB2 PHY reset */
  59. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  60. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  61. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  62. mdelay(100);
  63. /* Clear USB3 PHY reset */
  64. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  65. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  66. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  67. /* Clear USB2 PHY reset */
  68. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  69. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  70. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  71. mdelay(100);
  72. /* After PHYs are stable we can take Core out of reset state */
  73. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  74. reg &= ~DWC3_GCTL_CORESOFTRESET;
  75. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  76. return 0;
  77. }
  78. /**
  79. * dwc3_free_one_event_buffer - Frees one event buffer
  80. * @dwc: Pointer to our controller context structure
  81. * @evt: Pointer to event buffer to be freed
  82. */
  83. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  84. struct dwc3_event_buffer *evt)
  85. {
  86. dma_free_coherent(evt->buf);
  87. }
  88. /**
  89. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  90. * @dwc: Pointer to our controller context structure
  91. * @length: size of the event buffer
  92. *
  93. * Returns a pointer to the allocated event buffer structure on success
  94. * otherwise ERR_PTR(errno).
  95. */
  96. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  97. unsigned length)
  98. {
  99. struct dwc3_event_buffer *evt;
  100. evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
  101. GFP_KERNEL);
  102. if (!evt)
  103. return ERR_PTR(-ENOMEM);
  104. evt->dwc = dwc;
  105. evt->length = length;
  106. evt->buf = dma_alloc_coherent(length,
  107. (unsigned long *)&evt->dma);
  108. if (!evt->buf)
  109. return ERR_PTR(-ENOMEM);
  110. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  111. return evt;
  112. }
  113. /**
  114. * dwc3_free_event_buffers - frees all allocated event buffers
  115. * @dwc: Pointer to our controller context structure
  116. */
  117. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  118. {
  119. struct dwc3_event_buffer *evt;
  120. int i;
  121. for (i = 0; i < dwc->num_event_buffers; i++) {
  122. evt = dwc->ev_buffs[i];
  123. if (evt)
  124. dwc3_free_one_event_buffer(dwc, evt);
  125. }
  126. }
  127. /**
  128. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  129. * @dwc: pointer to our controller context structure
  130. * @length: size of event buffer
  131. *
  132. * Returns 0 on success otherwise negative errno. In the error case, dwc
  133. * may contain some buffers allocated but not all which were requested.
  134. */
  135. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  136. {
  137. int num;
  138. int i;
  139. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  140. dwc->num_event_buffers = num;
  141. dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
  142. sizeof(*dwc->ev_buffs) * num);
  143. if (!dwc->ev_buffs)
  144. return -ENOMEM;
  145. for (i = 0; i < num; i++) {
  146. struct dwc3_event_buffer *evt;
  147. evt = dwc3_alloc_one_event_buffer(dwc, length);
  148. if (IS_ERR(evt)) {
  149. dev_err(dwc->dev, "can't allocate event buffer\n");
  150. return PTR_ERR(evt);
  151. }
  152. dwc->ev_buffs[i] = evt;
  153. }
  154. return 0;
  155. }
  156. /**
  157. * dwc3_event_buffers_setup - setup our allocated event buffers
  158. * @dwc: pointer to our controller context structure
  159. *
  160. * Returns 0 on success otherwise negative errno.
  161. */
  162. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  163. {
  164. struct dwc3_event_buffer *evt;
  165. int n;
  166. for (n = 0; n < dwc->num_event_buffers; n++) {
  167. evt = dwc->ev_buffs[n];
  168. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  169. evt->buf, (unsigned long long) evt->dma,
  170. evt->length);
  171. evt->lpos = 0;
  172. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  173. lower_32_bits(evt->dma));
  174. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  175. upper_32_bits(evt->dma));
  176. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  177. DWC3_GEVNTSIZ_SIZE(evt->length));
  178. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  179. }
  180. return 0;
  181. }
  182. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  183. {
  184. struct dwc3_event_buffer *evt;
  185. int n;
  186. for (n = 0; n < dwc->num_event_buffers; n++) {
  187. evt = dwc->ev_buffs[n];
  188. evt->lpos = 0;
  189. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  190. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  191. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
  192. | DWC3_GEVNTSIZ_SIZE(0));
  193. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  194. }
  195. }
  196. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  197. {
  198. if (!dwc->has_hibernation)
  199. return 0;
  200. if (!dwc->nr_scratch)
  201. return 0;
  202. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  203. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  204. if (!dwc->scratchbuf)
  205. return -ENOMEM;
  206. return 0;
  207. }
  208. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  209. {
  210. dma_addr_t scratch_addr;
  211. u32 param;
  212. int ret;
  213. if (!dwc->has_hibernation)
  214. return 0;
  215. if (!dwc->nr_scratch)
  216. return 0;
  217. scratch_addr = dma_map_single(dwc->scratchbuf,
  218. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  219. DMA_BIDIRECTIONAL);
  220. if (dma_mapping_error(dwc->dev, scratch_addr)) {
  221. dev_err(dwc->dev, "failed to map scratch buffer\n");
  222. ret = -EFAULT;
  223. goto err0;
  224. }
  225. dwc->scratch_addr = scratch_addr;
  226. param = lower_32_bits(scratch_addr);
  227. ret = dwc3_send_gadget_generic_command(dwc,
  228. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  229. if (ret < 0)
  230. goto err1;
  231. param = upper_32_bits(scratch_addr);
  232. ret = dwc3_send_gadget_generic_command(dwc,
  233. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  234. if (ret < 0)
  235. goto err1;
  236. return 0;
  237. err1:
  238. dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  239. DMA_BIDIRECTIONAL);
  240. err0:
  241. return ret;
  242. }
  243. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  244. {
  245. if (!dwc->has_hibernation)
  246. return;
  247. if (!dwc->nr_scratch)
  248. return;
  249. dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
  250. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  251. kfree(dwc->scratchbuf);
  252. }
  253. static void dwc3_core_num_eps(struct dwc3 *dwc)
  254. {
  255. struct dwc3_hwparams *parms = &dwc->hwparams;
  256. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  257. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  258. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  259. dwc->num_in_eps, dwc->num_out_eps);
  260. }
  261. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  262. {
  263. struct dwc3_hwparams *parms = &dwc->hwparams;
  264. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  265. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  266. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  267. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  268. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  269. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  270. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  271. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  272. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  273. }
  274. /**
  275. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  276. * @dwc: Pointer to our controller context structure
  277. */
  278. static void dwc3_phy_setup(struct dwc3 *dwc)
  279. {
  280. u32 reg;
  281. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  282. /*
  283. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  284. * to '0' during coreConsultant configuration. So default value
  285. * will be '0' when the core is reset. Application needs to set it
  286. * to '1' after the core initialization is completed.
  287. */
  288. if (dwc->revision > DWC3_REVISION_194A)
  289. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  290. if (dwc->u2ss_inp3_quirk)
  291. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  292. if (dwc->req_p1p2p3_quirk)
  293. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  294. if (dwc->del_p1p2p3_quirk)
  295. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  296. if (dwc->del_phy_power_chg_quirk)
  297. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  298. if (dwc->lfps_filter_quirk)
  299. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  300. if (dwc->rx_detect_poll_quirk)
  301. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  302. if (dwc->tx_de_emphasis_quirk)
  303. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  304. if (dwc->dis_u3_susphy_quirk)
  305. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  306. if (dwc->dis_del_phy_power_chg_quirk)
  307. reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  308. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  309. mdelay(100);
  310. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  311. /*
  312. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  313. * '0' during coreConsultant configuration. So default value will
  314. * be '0' when the core is reset. Application needs to set it to
  315. * '1' after the core initialization is completed.
  316. */
  317. if (dwc->revision > DWC3_REVISION_194A)
  318. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  319. if (dwc->dis_u2_susphy_quirk)
  320. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  321. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  322. mdelay(100);
  323. }
  324. /**
  325. * dwc3_core_init - Low-level initialization of DWC3 Core
  326. * @dwc: Pointer to our controller context structure
  327. *
  328. * Returns 0 on success otherwise negative errno.
  329. */
  330. static int dwc3_core_init(struct dwc3 *dwc)
  331. {
  332. unsigned long timeout;
  333. u32 hwparams4 = dwc->hwparams.hwparams4;
  334. u32 reg;
  335. int ret;
  336. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  337. /* This should read as U3 followed by revision number */
  338. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  339. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  340. ret = -ENODEV;
  341. goto err0;
  342. }
  343. dwc->revision = reg;
  344. /* Handle USB2.0-only core configuration */
  345. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  346. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  347. if (dwc->maximum_speed == USB_SPEED_SUPER)
  348. dwc->maximum_speed = USB_SPEED_HIGH;
  349. }
  350. /* issue device SoftReset too */
  351. timeout = 5000;
  352. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  353. while (timeout--) {
  354. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  355. if (!(reg & DWC3_DCTL_CSFTRST))
  356. break;
  357. };
  358. if (!timeout) {
  359. dev_err(dwc->dev, "Reset Timed Out\n");
  360. ret = -ETIMEDOUT;
  361. goto err0;
  362. }
  363. dwc3_phy_setup(dwc);
  364. ret = dwc3_core_soft_reset(dwc);
  365. if (ret)
  366. goto err0;
  367. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  368. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  369. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  370. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  371. /**
  372. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  373. * issue which would cause xHCI compliance tests to fail.
  374. *
  375. * Because of that we cannot enable clock gating on such
  376. * configurations.
  377. *
  378. * Refers to:
  379. *
  380. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  381. * SOF/ITP Mode Used
  382. */
  383. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  384. dwc->dr_mode == USB_DR_MODE_OTG) &&
  385. (dwc->revision >= DWC3_REVISION_210A &&
  386. dwc->revision <= DWC3_REVISION_250A))
  387. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  388. else
  389. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  390. break;
  391. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  392. /* enable hibernation here */
  393. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  394. /*
  395. * REVISIT Enabling this bit so that host-mode hibernation
  396. * will work. Device-mode hibernation is not yet implemented.
  397. */
  398. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  399. break;
  400. default:
  401. dev_dbg(dwc->dev, "No power optimization available\n");
  402. }
  403. /* check if current dwc3 is on simulation board */
  404. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  405. dev_dbg(dwc->dev, "it is on FPGA board\n");
  406. dwc->is_fpga = true;
  407. }
  408. if(dwc->disable_scramble_quirk && !dwc->is_fpga)
  409. WARN(true,
  410. "disable_scramble cannot be used on non-FPGA builds\n");
  411. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  412. reg |= DWC3_GCTL_DISSCRAMBLE;
  413. else
  414. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  415. if (dwc->u2exit_lfps_quirk)
  416. reg |= DWC3_GCTL_U2EXIT_LFPS;
  417. /*
  418. * WORKAROUND: DWC3 revisions <1.90a have a bug
  419. * where the device can fail to connect at SuperSpeed
  420. * and falls back to high-speed mode which causes
  421. * the device to enter a Connect/Disconnect loop
  422. */
  423. if (dwc->revision < DWC3_REVISION_190A)
  424. reg |= DWC3_GCTL_U2RSTECN;
  425. dwc3_core_num_eps(dwc);
  426. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  427. ret = dwc3_alloc_scratch_buffers(dwc);
  428. if (ret)
  429. goto err0;
  430. ret = dwc3_setup_scratch_buffers(dwc);
  431. if (ret)
  432. goto err1;
  433. return 0;
  434. err1:
  435. dwc3_free_scratch_buffers(dwc);
  436. err0:
  437. return ret;
  438. }
  439. static void dwc3_core_exit(struct dwc3 *dwc)
  440. {
  441. dwc3_free_scratch_buffers(dwc);
  442. }
  443. static int dwc3_core_init_mode(struct dwc3 *dwc)
  444. {
  445. int ret;
  446. switch (dwc->dr_mode) {
  447. case USB_DR_MODE_PERIPHERAL:
  448. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  449. ret = dwc3_gadget_init(dwc);
  450. if (ret) {
  451. dev_err(dev, "failed to initialize gadget\n");
  452. return ret;
  453. }
  454. break;
  455. case USB_DR_MODE_HOST:
  456. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  457. ret = dwc3_host_init(dwc);
  458. if (ret) {
  459. dev_err(dev, "failed to initialize host\n");
  460. return ret;
  461. }
  462. break;
  463. case USB_DR_MODE_OTG:
  464. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  465. ret = dwc3_host_init(dwc);
  466. if (ret) {
  467. dev_err(dev, "failed to initialize host\n");
  468. return ret;
  469. }
  470. ret = dwc3_gadget_init(dwc);
  471. if (ret) {
  472. dev_err(dev, "failed to initialize gadget\n");
  473. return ret;
  474. }
  475. break;
  476. default:
  477. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  478. return -EINVAL;
  479. }
  480. return 0;
  481. }
  482. static void dwc3_gadget_run(struct dwc3 *dwc)
  483. {
  484. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
  485. mdelay(100);
  486. }
  487. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  488. {
  489. switch (dwc->dr_mode) {
  490. case USB_DR_MODE_PERIPHERAL:
  491. dwc3_gadget_exit(dwc);
  492. break;
  493. case USB_DR_MODE_HOST:
  494. dwc3_host_exit(dwc);
  495. break;
  496. case USB_DR_MODE_OTG:
  497. dwc3_host_exit(dwc);
  498. dwc3_gadget_exit(dwc);
  499. break;
  500. default:
  501. /* do nothing */
  502. break;
  503. }
  504. /*
  505. * switch back to peripheral mode
  506. * This enables the phy to enter idle and then, if enabled, suspend.
  507. */
  508. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  509. dwc3_gadget_run(dwc);
  510. }
  511. static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
  512. struct dwc3 *dwc)
  513. {
  514. enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
  515. u32 reg;
  516. /* Set dwc3 usb2 phy config */
  517. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  518. switch (hsphy_mode) {
  519. case USBPHY_INTERFACE_MODE_UTMI:
  520. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  521. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  522. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  523. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  524. break;
  525. case USBPHY_INTERFACE_MODE_UTMIW:
  526. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  527. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  528. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  529. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  530. break;
  531. default:
  532. break;
  533. }
  534. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  535. }
  536. #define DWC3_ALIGN_MASK (16 - 1)
  537. /**
  538. * dwc3_uboot_init - dwc3 core uboot initialization code
  539. * @dwc3_dev: struct dwc3_device containing initialization data
  540. *
  541. * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
  542. * kernel driver). Pointer to dwc3_device should be passed containing
  543. * base address and other initialization data. Returns '0' on success and
  544. * a negative value on failure.
  545. *
  546. * Generally called from board_usb_init() implemented in board file.
  547. */
  548. int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
  549. {
  550. struct dwc3 *dwc;
  551. struct device *dev = NULL;
  552. u8 lpm_nyet_threshold;
  553. u8 tx_de_emphasis;
  554. u8 hird_threshold;
  555. int ret;
  556. void *mem;
  557. mem = devm_kzalloc((struct udevice *)dev,
  558. sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  559. if (!mem)
  560. return -ENOMEM;
  561. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  562. dwc->mem = mem;
  563. dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
  564. DWC3_GLOBALS_REGS_START);
  565. /* default to highest possible threshold */
  566. lpm_nyet_threshold = 0xff;
  567. /* default to -3.5dB de-emphasis */
  568. tx_de_emphasis = 1;
  569. /*
  570. * default to assert utmi_sleep_n and use maximum allowed HIRD
  571. * threshold value of 0b1100
  572. */
  573. hird_threshold = 12;
  574. dwc->maximum_speed = dwc3_dev->maximum_speed;
  575. dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
  576. if (dwc3_dev->lpm_nyet_threshold)
  577. lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
  578. dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
  579. if (dwc3_dev->hird_threshold)
  580. hird_threshold = dwc3_dev->hird_threshold;
  581. dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
  582. dwc->dr_mode = dwc3_dev->dr_mode;
  583. dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
  584. dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
  585. dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
  586. dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
  587. dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
  588. dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
  589. dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
  590. dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
  591. dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
  592. dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
  593. dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
  594. dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
  595. if (dwc3_dev->tx_de_emphasis)
  596. tx_de_emphasis = dwc3_dev->tx_de_emphasis;
  597. /* default to superspeed if no maximum_speed passed */
  598. if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
  599. dwc->maximum_speed = USB_SPEED_SUPER;
  600. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  601. dwc->tx_de_emphasis = tx_de_emphasis;
  602. dwc->hird_threshold = hird_threshold
  603. | (dwc->is_utmi_l1_suspend << 4);
  604. dwc->index = dwc3_dev->index;
  605. dwc3_cache_hwparams(dwc);
  606. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  607. if (ret) {
  608. dev_err(dwc->dev, "failed to allocate event buffers\n");
  609. return -ENOMEM;
  610. }
  611. if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  612. dwc->dr_mode = USB_DR_MODE_HOST;
  613. else if (!IS_ENABLED(CONFIG_USB_HOST))
  614. dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
  615. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  616. dwc->dr_mode = USB_DR_MODE_OTG;
  617. ret = dwc3_core_init(dwc);
  618. if (ret) {
  619. dev_err(dev, "failed to initialize core\n");
  620. goto err0;
  621. }
  622. dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
  623. ret = dwc3_event_buffers_setup(dwc);
  624. if (ret) {
  625. dev_err(dwc->dev, "failed to setup event buffers\n");
  626. goto err1;
  627. }
  628. ret = dwc3_core_init_mode(dwc);
  629. if (ret)
  630. goto err2;
  631. list_add_tail(&dwc->list, &dwc3_list);
  632. return 0;
  633. err2:
  634. dwc3_event_buffers_cleanup(dwc);
  635. err1:
  636. dwc3_core_exit(dwc);
  637. err0:
  638. dwc3_free_event_buffers(dwc);
  639. return ret;
  640. }
  641. /**
  642. * dwc3_uboot_exit - dwc3 core uboot cleanup code
  643. * @index: index of this controller
  644. *
  645. * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
  646. * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
  647. * should be passed and should match with the index passed in
  648. * dwc3_device during init.
  649. *
  650. * Generally called from board file.
  651. */
  652. void dwc3_uboot_exit(int index)
  653. {
  654. struct dwc3 *dwc;
  655. list_for_each_entry(dwc, &dwc3_list, list) {
  656. if (dwc->index != index)
  657. continue;
  658. dwc3_core_exit_mode(dwc);
  659. dwc3_event_buffers_cleanup(dwc);
  660. dwc3_free_event_buffers(dwc);
  661. dwc3_core_exit(dwc);
  662. list_del(&dwc->list);
  663. kfree(dwc->mem);
  664. break;
  665. }
  666. }
  667. /**
  668. * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
  669. * @index: index of this controller
  670. *
  671. * Invokes dwc3 gadget interrupts.
  672. *
  673. * Generally called from board file.
  674. */
  675. void dwc3_uboot_handle_interrupt(int index)
  676. {
  677. struct dwc3 *dwc = NULL;
  678. list_for_each_entry(dwc, &dwc3_list, list) {
  679. if (dwc->index != index)
  680. continue;
  681. dwc3_gadget_uboot_handle_interrupt(dwc);
  682. break;
  683. }
  684. }
  685. MODULE_ALIAS("platform:dwc3");
  686. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  687. MODULE_LICENSE("GPL v2");
  688. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  689. #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
  690. int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
  691. {
  692. int ret;
  693. ret = generic_phy_get_bulk(dev, phys);
  694. if (ret)
  695. return ret;
  696. ret = generic_phy_init_bulk(phys);
  697. if (ret)
  698. return ret;
  699. ret = generic_phy_power_on_bulk(phys);
  700. if (ret)
  701. generic_phy_exit_bulk(phys);
  702. return ret;
  703. }
  704. int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
  705. {
  706. int ret;
  707. ret = generic_phy_power_off_bulk(phys);
  708. ret |= generic_phy_exit_bulk(phys);
  709. return ret;
  710. }
  711. #endif
  712. #if CONFIG_IS_ENABLED(DM_USB)
  713. void dwc3_of_parse(struct dwc3 *dwc)
  714. {
  715. const u8 *tmp;
  716. struct udevice *dev = dwc->dev;
  717. u8 lpm_nyet_threshold;
  718. u8 tx_de_emphasis;
  719. u8 hird_threshold;
  720. /* default to highest possible threshold */
  721. lpm_nyet_threshold = 0xff;
  722. /* default to -3.5dB de-emphasis */
  723. tx_de_emphasis = 1;
  724. /*
  725. * default to assert utmi_sleep_n and use maximum allowed HIRD
  726. * threshold value of 0b1100
  727. */
  728. hird_threshold = 12;
  729. dwc->has_lpm_erratum = dev_read_bool(dev,
  730. "snps,has-lpm-erratum");
  731. tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
  732. if (tmp)
  733. lpm_nyet_threshold = *tmp;
  734. dwc->is_utmi_l1_suspend = dev_read_bool(dev,
  735. "snps,is-utmi-l1-suspend");
  736. tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
  737. if (tmp)
  738. hird_threshold = *tmp;
  739. dwc->disable_scramble_quirk = dev_read_bool(dev,
  740. "snps,disable_scramble_quirk");
  741. dwc->u2exit_lfps_quirk = dev_read_bool(dev,
  742. "snps,u2exit_lfps_quirk");
  743. dwc->u2ss_inp3_quirk = dev_read_bool(dev,
  744. "snps,u2ss_inp3_quirk");
  745. dwc->req_p1p2p3_quirk = dev_read_bool(dev,
  746. "snps,req_p1p2p3_quirk");
  747. dwc->del_p1p2p3_quirk = dev_read_bool(dev,
  748. "snps,del_p1p2p3_quirk");
  749. dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
  750. "snps,del_phy_power_chg_quirk");
  751. dwc->lfps_filter_quirk = dev_read_bool(dev,
  752. "snps,lfps_filter_quirk");
  753. dwc->rx_detect_poll_quirk = dev_read_bool(dev,
  754. "snps,rx_detect_poll_quirk");
  755. dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
  756. "snps,dis_u3_susphy_quirk");
  757. dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
  758. "snps,dis_u2_susphy_quirk");
  759. dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
  760. "snps,dis-del-phy-power-chg-quirk");
  761. dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
  762. "snps,tx_de_emphasis_quirk");
  763. tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
  764. if (tmp)
  765. tx_de_emphasis = *tmp;
  766. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  767. dwc->tx_de_emphasis = tx_de_emphasis;
  768. dwc->hird_threshold = hird_threshold
  769. | (dwc->is_utmi_l1_suspend << 4);
  770. }
  771. int dwc3_init(struct dwc3 *dwc)
  772. {
  773. int ret;
  774. dwc3_cache_hwparams(dwc);
  775. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  776. if (ret) {
  777. dev_err(dwc->dev, "failed to allocate event buffers\n");
  778. return -ENOMEM;
  779. }
  780. ret = dwc3_core_init(dwc);
  781. if (ret) {
  782. dev_err(dev, "failed to initialize core\n");
  783. goto core_fail;
  784. }
  785. ret = dwc3_event_buffers_setup(dwc);
  786. if (ret) {
  787. dev_err(dwc->dev, "failed to setup event buffers\n");
  788. goto event_fail;
  789. }
  790. ret = dwc3_core_init_mode(dwc);
  791. if (ret)
  792. goto mode_fail;
  793. return 0;
  794. mode_fail:
  795. dwc3_event_buffers_cleanup(dwc);
  796. event_fail:
  797. dwc3_core_exit(dwc);
  798. core_fail:
  799. dwc3_free_event_buffers(dwc);
  800. return ret;
  801. }
  802. void dwc3_remove(struct dwc3 *dwc)
  803. {
  804. dwc3_core_exit_mode(dwc);
  805. dwc3_event_buffers_cleanup(dwc);
  806. dwc3_free_event_buffers(dwc);
  807. dwc3_core_exit(dwc);
  808. kfree(dwc->mem);
  809. }
  810. #endif