renesas_rpc_spi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas RCar Gen3 RPC QSPI driver
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <dm/of_access.h>
  12. #include <dt-structs.h>
  13. #include <errno.h>
  14. #include <linux/bug.h>
  15. #include <linux/errno.h>
  16. #include <spi.h>
  17. #include <wait_bit.h>
  18. #define RPC_CMNCR 0x0000 /* R/W */
  19. #define RPC_CMNCR_MD BIT(31)
  20. #define RPC_CMNCR_SFDE BIT(24)
  21. #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  22. #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  23. #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  24. #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  25. #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
  26. RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
  27. #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
  28. #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
  29. #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
  30. #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
  31. RPC_CMNCR_IO3FV(3))
  32. #define RPC_CMNCR_CPHAT BIT(6)
  33. #define RPC_CMNCR_CPHAR BIT(5)
  34. #define RPC_CMNCR_SSLP BIT(4)
  35. #define RPC_CMNCR_CPOL BIT(3)
  36. #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
  37. #define RPC_SSLDR 0x0004 /* R/W */
  38. #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
  39. #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
  40. #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
  41. #define RPC_DRCR 0x000C /* R/W */
  42. #define RPC_DRCR_SSLN BIT(24)
  43. #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
  44. #define RPC_DRCR_RCF BIT(9)
  45. #define RPC_DRCR_RBE BIT(8)
  46. #define RPC_DRCR_SSLE BIT(0)
  47. #define RPC_DRCMR 0x0010 /* R/W */
  48. #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
  49. #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
  50. #define RPC_DREAR 0x0014 /* R/W */
  51. #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
  52. #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
  53. #define RPC_DROPR 0x0018 /* R/W */
  54. #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
  55. #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
  56. #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
  57. #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
  58. #define RPC_DRENR 0x001C /* R/W */
  59. #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
  60. #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
  61. #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
  62. #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
  63. #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
  64. #define RPC_DRENR_DME BIT(15)
  65. #define RPC_DRENR_CDE BIT(14)
  66. #define RPC_DRENR_OCDE BIT(12)
  67. #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
  68. #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
  69. #define RPC_SMCR 0x0020 /* R/W */
  70. #define RPC_SMCR_SSLKP BIT(8)
  71. #define RPC_SMCR_SPIRE BIT(2)
  72. #define RPC_SMCR_SPIWE BIT(1)
  73. #define RPC_SMCR_SPIE BIT(0)
  74. #define RPC_SMCMR 0x0024 /* R/W */
  75. #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
  76. #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
  77. #define RPC_SMADR 0x0028 /* R/W */
  78. #define RPC_SMOPR 0x002C /* R/W */
  79. #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
  80. #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
  81. #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
  82. #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
  83. #define RPC_SMENR 0x0030 /* R/W */
  84. #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
  85. #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
  86. #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
  87. #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
  88. #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
  89. #define RPC_SMENR_DME BIT(15)
  90. #define RPC_SMENR_CDE BIT(14)
  91. #define RPC_SMENR_OCDE BIT(12)
  92. #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
  93. #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
  94. #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
  95. #define RPC_SMRDR0 0x0038 /* R */
  96. #define RPC_SMRDR1 0x003C /* R */
  97. #define RPC_SMWDR0 0x0040 /* R/W */
  98. #define RPC_SMWDR1 0x0044 /* R/W */
  99. #define RPC_CMNSR 0x0048 /* R */
  100. #define RPC_CMNSR_SSLF BIT(1)
  101. #define RPC_CMNSR_TEND BIT(0)
  102. #define RPC_DRDMCR 0x0058 /* R/W */
  103. #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
  104. #define RPC_DRDRENR 0x005C /* R/W */
  105. #define RPC_DRDRENR_HYPE (0x5 << 12)
  106. #define RPC_DRDRENR_ADDRE BIT(8)
  107. #define RPC_DRDRENR_OPDRE BIT(4)
  108. #define RPC_DRDRENR_DRDRE BIT(0)
  109. #define RPC_SMDMCR 0x0060 /* R/W */
  110. #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
  111. #define RPC_SMDRENR 0x0064 /* R/W */
  112. #define RPC_SMDRENR_HYPE (0x5 << 12)
  113. #define RPC_SMDRENR_ADDRE BIT(8)
  114. #define RPC_SMDRENR_OPDRE BIT(4)
  115. #define RPC_SMDRENR_SPIDRE BIT(0)
  116. #define RPC_PHYCNT 0x007C /* R/W */
  117. #define RPC_PHYCNT_CAL BIT(31)
  118. #define PRC_PHYCNT_OCTA_AA BIT(22)
  119. #define PRC_PHYCNT_OCTA_SA BIT(23)
  120. #define PRC_PHYCNT_EXDS BIT(21)
  121. #define RPC_PHYCNT_OCT BIT(20)
  122. #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
  123. #define RPC_PHYCNT_WBUF2 BIT(4)
  124. #define RPC_PHYCNT_WBUF BIT(2)
  125. #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
  126. #define RPC_PHYINT 0x0088 /* R/W */
  127. #define RPC_PHYINT_RSTEN BIT(18)
  128. #define RPC_PHYINT_WPEN BIT(17)
  129. #define RPC_PHYINT_INTEN BIT(16)
  130. #define RPC_PHYINT_RST BIT(2)
  131. #define RPC_PHYINT_WP BIT(1)
  132. #define RPC_PHYINT_INT BIT(0)
  133. #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
  134. #define RPC_WBUF_SIZE 0x100
  135. DECLARE_GLOBAL_DATA_PTR;
  136. struct rpc_spi_platdata {
  137. fdt_addr_t regs;
  138. fdt_addr_t extr;
  139. s32 freq; /* Default clock freq, -1 for none */
  140. };
  141. struct rpc_spi_priv {
  142. fdt_addr_t regs;
  143. fdt_addr_t extr;
  144. struct clk clk;
  145. u8 cmdcopy[8];
  146. u32 cmdlen;
  147. bool cmdstarted;
  148. };
  149. static int rpc_spi_wait_sslf(struct udevice *dev)
  150. {
  151. struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
  152. return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF,
  153. false, 1000, false);
  154. }
  155. static int rpc_spi_wait_tend(struct udevice *dev)
  156. {
  157. struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
  158. return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND,
  159. true, 1000, false);
  160. }
  161. static void rpc_spi_flush_read_cache(struct udevice *dev)
  162. {
  163. struct udevice *bus = dev->parent;
  164. struct rpc_spi_priv *priv = dev_get_priv(bus);
  165. /* Flush read cache */
  166. writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) |
  167. RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE,
  168. priv->regs + RPC_DRCR);
  169. readl(priv->regs + RPC_DRCR);
  170. }
  171. static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
  172. {
  173. struct udevice *bus = dev->parent;
  174. struct rpc_spi_priv *priv = dev_get_priv(bus);
  175. /*
  176. * NOTE: The 0x260 are undocumented bits, but they must be set.
  177. * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
  178. * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
  179. * RPC_PHYCNT_STRTIM shall be 6.
  180. */
  181. writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
  182. priv->regs + RPC_PHYCNT);
  183. writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
  184. RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
  185. priv->regs + RPC_CMNCR);
  186. writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) |
  187. RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR);
  188. rpc_spi_flush_read_cache(dev);
  189. return 0;
  190. }
  191. static int rpc_spi_release_bus(struct udevice *dev)
  192. {
  193. struct udevice *bus = dev->parent;
  194. struct rpc_spi_priv *priv = dev_get_priv(bus);
  195. /* NOTE: The 0x260 are undocumented bits, but they must be set. */
  196. writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
  197. rpc_spi_flush_read_cache(dev);
  198. return 0;
  199. }
  200. static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
  201. const void *dout, void *din, unsigned long flags)
  202. {
  203. struct udevice *bus = dev->parent;
  204. struct rpc_spi_priv *priv = dev_get_priv(bus);
  205. u32 wlen = dout ? (bitlen / 8) : 0;
  206. u32 rlen = din ? (bitlen / 8) : 0;
  207. u32 wloop = DIV_ROUND_UP(wlen, 4);
  208. u32 smenr, smcr, offset;
  209. int ret = 0;
  210. if (!priv->cmdstarted) {
  211. if (!wlen || rlen)
  212. BUG();
  213. memcpy(priv->cmdcopy, dout, wlen);
  214. priv->cmdlen = wlen;
  215. /* Command transfer start */
  216. priv->cmdstarted = true;
  217. if (!(flags & SPI_XFER_END))
  218. return 0;
  219. }
  220. offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
  221. (priv->cmdcopy[3] << 0);
  222. smenr = 0;
  223. if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
  224. if (wlen && flags == SPI_XFER_END)
  225. smenr = RPC_SMENR_SPIDE(0xf);
  226. rpc_spi_claim_bus(dev, true);
  227. writel(0, priv->regs + RPC_SMCR);
  228. if (priv->cmdlen >= 1) { /* Command(1) */
  229. writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
  230. priv->regs + RPC_SMCMR);
  231. smenr |= RPC_SMENR_CDE;
  232. } else {
  233. writel(0, priv->regs + RPC_SMCMR);
  234. }
  235. if (priv->cmdlen >= 4) { /* Address(3) */
  236. writel(offset, priv->regs + RPC_SMADR);
  237. smenr |= RPC_SMENR_ADE(7);
  238. } else {
  239. writel(0, priv->regs + RPC_SMADR);
  240. }
  241. if (priv->cmdlen >= 5) { /* Dummy(n) */
  242. writel(8 * (priv->cmdlen - 4) - 1,
  243. priv->regs + RPC_SMDMCR);
  244. smenr |= RPC_SMENR_DME;
  245. } else {
  246. writel(0, priv->regs + RPC_SMDMCR);
  247. }
  248. writel(0, priv->regs + RPC_SMOPR);
  249. writel(0, priv->regs + RPC_SMDRENR);
  250. if (wlen && flags == SPI_XFER_END) {
  251. u32 *datout = (u32 *)dout;
  252. while (wloop--) {
  253. smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
  254. if (wloop >= 1)
  255. smcr |= RPC_SMCR_SSLKP;
  256. writel(smenr, priv->regs + RPC_SMENR);
  257. writel(*datout, priv->regs + RPC_SMWDR0);
  258. writel(smcr, priv->regs + RPC_SMCR);
  259. ret = rpc_spi_wait_tend(dev);
  260. if (ret)
  261. goto err;
  262. datout++;
  263. smenr = RPC_SMENR_SPIDE(0xf);
  264. }
  265. ret = rpc_spi_wait_sslf(dev);
  266. } else {
  267. writel(smenr, priv->regs + RPC_SMENR);
  268. writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
  269. ret = rpc_spi_wait_tend(dev);
  270. }
  271. } else { /* Read data only, using DRx ext access */
  272. rpc_spi_claim_bus(dev, false);
  273. if (priv->cmdlen >= 1) { /* Command(1) */
  274. writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
  275. priv->regs + RPC_DRCMR);
  276. smenr |= RPC_DRENR_CDE;
  277. } else {
  278. writel(0, priv->regs + RPC_DRCMR);
  279. }
  280. if (priv->cmdlen >= 4) /* Address(3) */
  281. smenr |= RPC_DRENR_ADE(7);
  282. if (priv->cmdlen >= 5) { /* Dummy(n) */
  283. writel(8 * (priv->cmdlen - 4) - 1,
  284. priv->regs + RPC_DRDMCR);
  285. smenr |= RPC_DRENR_DME;
  286. } else {
  287. writel(0, priv->regs + RPC_DRDMCR);
  288. }
  289. writel(0, priv->regs + RPC_DROPR);
  290. writel(smenr, priv->regs + RPC_DRENR);
  291. if (rlen)
  292. memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
  293. else
  294. readl(priv->extr); /* Dummy read */
  295. }
  296. err:
  297. priv->cmdstarted = false;
  298. rpc_spi_release_bus(dev);
  299. return ret;
  300. }
  301. static int rpc_spi_set_speed(struct udevice *bus, uint speed)
  302. {
  303. /* This is a SPI NOR controller, do nothing. */
  304. return 0;
  305. }
  306. static int rpc_spi_set_mode(struct udevice *bus, uint mode)
  307. {
  308. /* This is a SPI NOR controller, do nothing. */
  309. return 0;
  310. }
  311. static int rpc_spi_bind(struct udevice *parent)
  312. {
  313. const void *fdt = gd->fdt_blob;
  314. ofnode node;
  315. int ret, off;
  316. /*
  317. * Check if there are any SPI NOR child nodes, if so, bind as
  318. * this controller will be operated in SPI mode.
  319. */
  320. dev_for_each_subnode(node, parent) {
  321. off = ofnode_to_offset(node);
  322. ret = fdt_node_check_compatible(fdt, off, "spi-flash");
  323. if (!ret)
  324. return 0;
  325. ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
  326. if (!ret)
  327. return 0;
  328. }
  329. return -ENODEV;
  330. }
  331. static int rpc_spi_probe(struct udevice *dev)
  332. {
  333. struct rpc_spi_platdata *plat = dev_get_platdata(dev);
  334. struct rpc_spi_priv *priv = dev_get_priv(dev);
  335. priv->regs = plat->regs;
  336. priv->extr = plat->extr;
  337. #if CONFIG_IS_ENABLED(CLK)
  338. clk_enable(&priv->clk);
  339. #endif
  340. return 0;
  341. }
  342. static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
  343. {
  344. struct rpc_spi_platdata *plat = dev_get_platdata(bus);
  345. plat->regs = dev_read_addr_index(bus, 0);
  346. plat->extr = dev_read_addr_index(bus, 1);
  347. #if CONFIG_IS_ENABLED(CLK)
  348. struct rpc_spi_priv *priv = dev_get_priv(bus);
  349. int ret;
  350. ret = clk_get_by_index(bus, 0, &priv->clk);
  351. if (ret < 0) {
  352. printf("%s: Could not get clock for %s: %d\n",
  353. __func__, bus->name, ret);
  354. return ret;
  355. }
  356. #endif
  357. plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
  358. return 0;
  359. }
  360. static const struct dm_spi_ops rpc_spi_ops = {
  361. .xfer = rpc_spi_xfer,
  362. .set_speed = rpc_spi_set_speed,
  363. .set_mode = rpc_spi_set_mode,
  364. };
  365. static const struct udevice_id rpc_spi_ids[] = {
  366. { .compatible = "renesas,rpc-r8a7795" },
  367. { .compatible = "renesas,rpc-r8a7796" },
  368. { .compatible = "renesas,rpc-r8a77965" },
  369. { .compatible = "renesas,rpc-r8a77970" },
  370. { .compatible = "renesas,rpc-r8a77995" },
  371. { .compatible = "renesas,rpc-r7s72100" },
  372. { }
  373. };
  374. U_BOOT_DRIVER(rpc_spi) = {
  375. .name = "rpc_spi",
  376. .id = UCLASS_SPI,
  377. .of_match = rpc_spi_ids,
  378. .ops = &rpc_spi_ops,
  379. .ofdata_to_platdata = rpc_spi_ofdata_to_platdata,
  380. .platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata),
  381. .priv_auto_alloc_size = sizeof(struct rpc_spi_priv),
  382. .bind = rpc_spi_bind,
  383. .probe = rpc_spi_probe,
  384. };