pfc.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Pin Control driver for SuperH Pin Function Controller.
  4. *
  5. * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
  6. *
  7. * Copyright (C) 2008 Magnus Damm
  8. * Copyright (C) 2009 - 2012 Paul Mundt
  9. * Copyright (C) 2017 Marek Vasut
  10. */
  11. #define DRV_NAME "sh-pfc"
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <dm/device_compat.h>
  16. #include <dm/devres.h>
  17. #include <dm/pinctrl.h>
  18. #include <linux/bug.h>
  19. #include <linux/io.h>
  20. #include <linux/sizes.h>
  21. #include "sh_pfc.h"
  22. enum sh_pfc_model {
  23. SH_PFC_R8A7790 = 0,
  24. SH_PFC_R8A7791,
  25. SH_PFC_R8A7792,
  26. SH_PFC_R8A7793,
  27. SH_PFC_R8A7794,
  28. SH_PFC_R8A7795,
  29. SH_PFC_R8A7796,
  30. SH_PFC_R8A77965,
  31. SH_PFC_R8A77970,
  32. SH_PFC_R8A77980,
  33. SH_PFC_R8A77990,
  34. SH_PFC_R8A77995,
  35. };
  36. struct sh_pfc_pin_config {
  37. u32 type;
  38. };
  39. struct sh_pfc_pinctrl {
  40. struct sh_pfc *pfc;
  41. struct sh_pfc_pin_config *configs;
  42. const char *func_prop_name;
  43. const char *groups_prop_name;
  44. const char *pins_prop_name;
  45. };
  46. struct sh_pfc_pin_range {
  47. u16 start;
  48. u16 end;
  49. };
  50. struct sh_pfc_pinctrl_priv {
  51. struct sh_pfc pfc;
  52. struct sh_pfc_pinctrl pmx;
  53. };
  54. int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  55. {
  56. unsigned int offset;
  57. unsigned int i;
  58. for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  59. const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  60. if (pin <= range->end)
  61. return pin >= range->start
  62. ? offset + pin - range->start : -1;
  63. offset += range->end - range->start + 1;
  64. }
  65. return -EINVAL;
  66. }
  67. static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  68. {
  69. if (enum_id < r->begin)
  70. return 0;
  71. if (enum_id > r->end)
  72. return 0;
  73. return 1;
  74. }
  75. u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  76. {
  77. switch (reg_width) {
  78. case 8:
  79. return readb(mapped_reg);
  80. case 16:
  81. return readw(mapped_reg);
  82. case 32:
  83. return readl(mapped_reg);
  84. }
  85. BUG();
  86. return 0;
  87. }
  88. void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
  89. u32 data)
  90. {
  91. switch (reg_width) {
  92. case 8:
  93. writeb(data, mapped_reg);
  94. return;
  95. case 16:
  96. writew(data, mapped_reg);
  97. return;
  98. case 32:
  99. writel(data, mapped_reg);
  100. return;
  101. }
  102. BUG();
  103. }
  104. u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
  105. {
  106. return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
  107. }
  108. void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
  109. {
  110. void __iomem *unlock_reg =
  111. (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
  112. if (pfc->info->unlock_reg)
  113. sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
  114. sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
  115. }
  116. static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
  117. const struct pinmux_cfg_reg *crp,
  118. unsigned int in_pos,
  119. void __iomem **mapped_regp, u32 *maskp,
  120. unsigned int *posp)
  121. {
  122. unsigned int k;
  123. *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
  124. if (crp->field_width) {
  125. *maskp = (1 << crp->field_width) - 1;
  126. *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
  127. } else {
  128. *maskp = (1 << crp->var_field_width[in_pos]) - 1;
  129. *posp = crp->reg_width;
  130. for (k = 0; k <= in_pos; k++)
  131. *posp -= crp->var_field_width[k];
  132. }
  133. }
  134. static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
  135. const struct pinmux_cfg_reg *crp,
  136. unsigned int field, u32 value)
  137. {
  138. void __iomem *mapped_reg;
  139. void __iomem *unlock_reg =
  140. (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
  141. unsigned int pos;
  142. u32 mask, data;
  143. sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
  144. dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
  145. "r_width = %u, f_width = %u\n",
  146. crp->reg, value, field, crp->reg_width, crp->field_width);
  147. mask = ~(mask << pos);
  148. value = value << pos;
  149. data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
  150. data &= mask;
  151. data |= value;
  152. if (pfc->info->unlock_reg)
  153. sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
  154. sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
  155. }
  156. static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
  157. const struct pinmux_cfg_reg **crp,
  158. unsigned int *fieldp, u32 *valuep)
  159. {
  160. unsigned int k = 0;
  161. while (1) {
  162. const struct pinmux_cfg_reg *config_reg =
  163. pfc->info->cfg_regs + k;
  164. unsigned int r_width = config_reg->reg_width;
  165. unsigned int f_width = config_reg->field_width;
  166. unsigned int curr_width;
  167. unsigned int bit_pos;
  168. unsigned int pos = 0;
  169. unsigned int m = 0;
  170. if (!r_width)
  171. break;
  172. for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
  173. u32 ncomb;
  174. u32 n;
  175. if (f_width)
  176. curr_width = f_width;
  177. else
  178. curr_width = config_reg->var_field_width[m];
  179. ncomb = 1 << curr_width;
  180. for (n = 0; n < ncomb; n++) {
  181. if (config_reg->enum_ids[pos + n] == enum_id) {
  182. *crp = config_reg;
  183. *fieldp = m;
  184. *valuep = n;
  185. return 0;
  186. }
  187. }
  188. pos += ncomb;
  189. m++;
  190. }
  191. k++;
  192. }
  193. return -EINVAL;
  194. }
  195. static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
  196. u16 *enum_idp)
  197. {
  198. const u16 *data = pfc->info->pinmux_data;
  199. unsigned int k;
  200. if (pos) {
  201. *enum_idp = data[pos + 1];
  202. return pos + 1;
  203. }
  204. for (k = 0; k < pfc->info->pinmux_data_size; k++) {
  205. if (data[k] == mark) {
  206. *enum_idp = data[k + 1];
  207. return k + 1;
  208. }
  209. }
  210. dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
  211. mark);
  212. return -EINVAL;
  213. }
  214. int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
  215. {
  216. const struct pinmux_range *range;
  217. int pos = 0;
  218. switch (pinmux_type) {
  219. case PINMUX_TYPE_GPIO:
  220. case PINMUX_TYPE_FUNCTION:
  221. range = NULL;
  222. break;
  223. case PINMUX_TYPE_OUTPUT:
  224. range = &pfc->info->output;
  225. break;
  226. case PINMUX_TYPE_INPUT:
  227. range = &pfc->info->input;
  228. break;
  229. default:
  230. return -EINVAL;
  231. }
  232. /* Iterate over all the configuration fields we need to update. */
  233. while (1) {
  234. const struct pinmux_cfg_reg *cr;
  235. unsigned int field;
  236. u16 enum_id;
  237. u32 value;
  238. int in_range;
  239. int ret;
  240. pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
  241. if (pos < 0)
  242. return pos;
  243. if (!enum_id)
  244. break;
  245. /* Check if the configuration field selects a function. If it
  246. * doesn't, skip the field if it's not applicable to the
  247. * requested pinmux type.
  248. */
  249. in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
  250. if (!in_range) {
  251. if (pinmux_type == PINMUX_TYPE_FUNCTION) {
  252. /* Functions are allowed to modify all
  253. * fields.
  254. */
  255. in_range = 1;
  256. } else if (pinmux_type != PINMUX_TYPE_GPIO) {
  257. /* Input/output types can only modify fields
  258. * that correspond to their respective ranges.
  259. */
  260. in_range = sh_pfc_enum_in_range(enum_id, range);
  261. /*
  262. * special case pass through for fixed
  263. * input-only or output-only pins without
  264. * function enum register association.
  265. */
  266. if (in_range && enum_id == range->force)
  267. continue;
  268. }
  269. /* GPIOs are only allowed to modify function fields. */
  270. }
  271. if (!in_range)
  272. continue;
  273. ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
  274. if (ret < 0)
  275. return ret;
  276. sh_pfc_write_config_reg(pfc, cr, field, value);
  277. }
  278. return 0;
  279. }
  280. const struct pinmux_bias_reg *
  281. sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
  282. unsigned int *bit)
  283. {
  284. unsigned int i, j;
  285. for (i = 0; pfc->info->bias_regs[i].puen; i++) {
  286. for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
  287. if (pfc->info->bias_regs[i].pins[j] == pin) {
  288. *bit = j;
  289. return &pfc->info->bias_regs[i];
  290. }
  291. }
  292. }
  293. WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
  294. return NULL;
  295. }
  296. static int sh_pfc_init_ranges(struct sh_pfc *pfc)
  297. {
  298. struct sh_pfc_pin_range *range;
  299. unsigned int nr_ranges;
  300. unsigned int i;
  301. if (pfc->info->pins[0].pin == (u16)-1) {
  302. /* Pin number -1 denotes that the SoC doesn't report pin numbers
  303. * in its pin arrays yet. Consider the pin numbers range as
  304. * continuous and allocate a single range.
  305. */
  306. pfc->nr_ranges = 1;
  307. pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
  308. if (pfc->ranges == NULL)
  309. return -ENOMEM;
  310. pfc->ranges->start = 0;
  311. pfc->ranges->end = pfc->info->nr_pins - 1;
  312. pfc->nr_gpio_pins = pfc->info->nr_pins;
  313. return 0;
  314. }
  315. /* Count, allocate and fill the ranges. The PFC SoC data pins array must
  316. * be sorted by pin numbers, and pins without a GPIO port must come
  317. * last.
  318. */
  319. for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
  320. if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
  321. nr_ranges++;
  322. }
  323. pfc->nr_ranges = nr_ranges;
  324. pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
  325. if (pfc->ranges == NULL)
  326. return -ENOMEM;
  327. range = pfc->ranges;
  328. range->start = pfc->info->pins[0].pin;
  329. for (i = 1; i < pfc->info->nr_pins; ++i) {
  330. if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
  331. continue;
  332. range->end = pfc->info->pins[i-1].pin;
  333. if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
  334. pfc->nr_gpio_pins = range->end + 1;
  335. range++;
  336. range->start = pfc->info->pins[i].pin;
  337. }
  338. range->end = pfc->info->pins[i-1].pin;
  339. if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
  340. pfc->nr_gpio_pins = range->end + 1;
  341. return 0;
  342. }
  343. static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
  344. {
  345. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  346. return priv->pfc.info->nr_pins;
  347. }
  348. static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
  349. unsigned selector)
  350. {
  351. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  352. return priv->pfc.info->pins[selector].name;
  353. }
  354. static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
  355. {
  356. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  357. return priv->pfc.info->nr_groups;
  358. }
  359. static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
  360. unsigned selector)
  361. {
  362. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  363. return priv->pfc.info->groups[selector].name;
  364. }
  365. static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
  366. {
  367. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  368. return priv->pfc.info->nr_functions;
  369. }
  370. static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
  371. unsigned selector)
  372. {
  373. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  374. return priv->pfc.info->functions[selector].name;
  375. }
  376. static int sh_pfc_gpio_request_enable(struct udevice *dev,
  377. unsigned pin_selector)
  378. {
  379. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  380. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  381. struct sh_pfc *pfc = &priv->pfc;
  382. struct sh_pfc_pin_config *cfg;
  383. const struct sh_pfc_pin *pin = NULL;
  384. int i, ret, idx;
  385. for (i = 0; i < pfc->info->nr_pins; i++) {
  386. if (priv->pfc.info->pins[i].pin != pin_selector)
  387. continue;
  388. pin = &priv->pfc.info->pins[i];
  389. break;
  390. }
  391. if (!pin)
  392. return -EINVAL;
  393. idx = sh_pfc_get_pin_index(pfc, pin->pin);
  394. cfg = &pmx->configs[idx];
  395. if (cfg->type != PINMUX_TYPE_NONE)
  396. return -EBUSY;
  397. ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
  398. if (ret)
  399. return ret;
  400. cfg->type = PINMUX_TYPE_GPIO;
  401. return 0;
  402. }
  403. static int sh_pfc_gpio_disable_free(struct udevice *dev,
  404. unsigned pin_selector)
  405. {
  406. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  407. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  408. struct sh_pfc *pfc = &priv->pfc;
  409. struct sh_pfc_pin_config *cfg;
  410. const struct sh_pfc_pin *pin = NULL;
  411. int i, idx;
  412. for (i = 0; i < pfc->info->nr_pins; i++) {
  413. if (priv->pfc.info->pins[i].pin != pin_selector)
  414. continue;
  415. pin = &priv->pfc.info->pins[i];
  416. break;
  417. }
  418. if (!pin)
  419. return -EINVAL;
  420. idx = sh_pfc_get_pin_index(pfc, pin->pin);
  421. cfg = &pmx->configs[idx];
  422. cfg->type = PINMUX_TYPE_NONE;
  423. return 0;
  424. }
  425. static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
  426. unsigned func_selector)
  427. {
  428. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  429. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  430. struct sh_pfc *pfc = &priv->pfc;
  431. const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
  432. int idx = sh_pfc_get_pin_index(pfc, pin->pin);
  433. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  434. if (cfg->type != PINMUX_TYPE_NONE)
  435. return -EBUSY;
  436. return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
  437. }
  438. static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
  439. unsigned func_selector)
  440. {
  441. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  442. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  443. struct sh_pfc *pfc = &priv->pfc;
  444. const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
  445. unsigned int i;
  446. int ret = 0;
  447. for (i = 0; i < grp->nr_pins; ++i) {
  448. int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
  449. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  450. if (cfg->type != PINMUX_TYPE_NONE) {
  451. ret = -EBUSY;
  452. goto done;
  453. }
  454. }
  455. for (i = 0; i < grp->nr_pins; ++i) {
  456. ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
  457. if (ret < 0)
  458. break;
  459. }
  460. done:
  461. return ret;
  462. }
  463. #if CONFIG_IS_ENABLED(PINCONF)
  464. static const struct pinconf_param sh_pfc_pinconf_params[] = {
  465. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  466. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  467. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  468. { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
  469. { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
  470. };
  471. static void __iomem *
  472. sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
  473. unsigned int *offset, unsigned int *size)
  474. {
  475. const struct pinmux_drive_reg_field *field;
  476. const struct pinmux_drive_reg *reg;
  477. unsigned int i;
  478. for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
  479. for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
  480. field = &reg->fields[i];
  481. if (field->size && field->pin == pin) {
  482. *offset = field->offset;
  483. *size = field->size;
  484. return (void __iomem *)(uintptr_t)reg->reg;
  485. }
  486. }
  487. }
  488. return NULL;
  489. }
  490. static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
  491. unsigned int pin, u16 strength)
  492. {
  493. unsigned int offset;
  494. unsigned int size;
  495. unsigned int step;
  496. void __iomem *reg;
  497. void __iomem *unlock_reg =
  498. (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
  499. u32 val;
  500. reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
  501. if (!reg)
  502. return -EINVAL;
  503. step = size == 2 ? 6 : 3;
  504. if (strength < step || strength > 24)
  505. return -EINVAL;
  506. /* Convert the value from mA based on a full drive strength value of
  507. * 24mA. We can make the full value configurable later if needed.
  508. */
  509. strength = strength / step - 1;
  510. val = sh_pfc_read_raw_reg(reg, 32);
  511. val &= ~GENMASK(offset + 4 - 1, offset);
  512. val |= strength << offset;
  513. if (unlock_reg)
  514. sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
  515. sh_pfc_write_raw_reg(reg, 32, val);
  516. return 0;
  517. }
  518. /* Check whether the requested parameter is supported for a pin. */
  519. static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
  520. unsigned int param)
  521. {
  522. int idx = sh_pfc_get_pin_index(pfc, _pin);
  523. const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  524. switch (param) {
  525. case PIN_CONFIG_BIAS_DISABLE:
  526. return pin->configs &
  527. (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
  528. case PIN_CONFIG_BIAS_PULL_UP:
  529. return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
  530. case PIN_CONFIG_BIAS_PULL_DOWN:
  531. return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
  532. case PIN_CONFIG_DRIVE_STRENGTH:
  533. return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
  534. case PIN_CONFIG_POWER_SOURCE:
  535. return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
  536. default:
  537. return false;
  538. }
  539. }
  540. static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
  541. unsigned int param, unsigned int arg)
  542. {
  543. struct sh_pfc *pfc = pmx->pfc;
  544. void __iomem *pocctrl;
  545. void __iomem *unlock_reg =
  546. (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
  547. u32 addr, val;
  548. int bit, ret;
  549. if (!sh_pfc_pinconf_validate(pfc, _pin, param))
  550. return -ENOTSUPP;
  551. switch (param) {
  552. case PIN_CONFIG_BIAS_PULL_UP:
  553. case PIN_CONFIG_BIAS_PULL_DOWN:
  554. case PIN_CONFIG_BIAS_DISABLE:
  555. if (!pfc->info->ops || !pfc->info->ops->set_bias)
  556. return -ENOTSUPP;
  557. pfc->info->ops->set_bias(pfc, _pin, param);
  558. break;
  559. case PIN_CONFIG_DRIVE_STRENGTH:
  560. ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
  561. if (ret < 0)
  562. return ret;
  563. break;
  564. case PIN_CONFIG_POWER_SOURCE:
  565. if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
  566. return -ENOTSUPP;
  567. bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
  568. if (bit < 0) {
  569. printf("invalid pin %#x", _pin);
  570. return bit;
  571. }
  572. if (arg != 1800 && arg != 3300)
  573. return -EINVAL;
  574. pocctrl = (void __iomem *)(uintptr_t)addr;
  575. val = sh_pfc_read_raw_reg(pocctrl, 32);
  576. if (arg == 3300)
  577. val |= BIT(bit);
  578. else
  579. val &= ~BIT(bit);
  580. if (unlock_reg)
  581. sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
  582. sh_pfc_write_raw_reg(pocctrl, 32, val);
  583. break;
  584. default:
  585. return -ENOTSUPP;
  586. }
  587. return 0;
  588. }
  589. static int sh_pfc_pinconf_pin_set(struct udevice *dev,
  590. unsigned int pin_selector,
  591. unsigned int param, unsigned int arg)
  592. {
  593. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  594. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  595. struct sh_pfc *pfc = &priv->pfc;
  596. const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
  597. sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
  598. return 0;
  599. }
  600. static int sh_pfc_pinconf_group_set(struct udevice *dev,
  601. unsigned int group_selector,
  602. unsigned int param, unsigned int arg)
  603. {
  604. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  605. struct sh_pfc_pinctrl *pmx = &priv->pmx;
  606. struct sh_pfc *pfc = &priv->pfc;
  607. const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
  608. unsigned int i;
  609. for (i = 0; i < grp->nr_pins; i++)
  610. sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
  611. return 0;
  612. }
  613. #endif
  614. static struct pinctrl_ops sh_pfc_pinctrl_ops = {
  615. .get_pins_count = sh_pfc_pinctrl_get_pins_count,
  616. .get_pin_name = sh_pfc_pinctrl_get_pin_name,
  617. .get_groups_count = sh_pfc_pinctrl_get_groups_count,
  618. .get_group_name = sh_pfc_pinctrl_get_group_name,
  619. .get_functions_count = sh_pfc_pinctrl_get_functions_count,
  620. .get_function_name = sh_pfc_pinctrl_get_function_name,
  621. #if CONFIG_IS_ENABLED(PINCONF)
  622. .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
  623. .pinconf_params = sh_pfc_pinconf_params,
  624. .pinconf_set = sh_pfc_pinconf_pin_set,
  625. .pinconf_group_set = sh_pfc_pinconf_group_set,
  626. #endif
  627. .pinmux_set = sh_pfc_pinctrl_pin_set,
  628. .pinmux_group_set = sh_pfc_pinctrl_group_set,
  629. .set_state = pinctrl_generic_set_state,
  630. .gpio_request_enable = sh_pfc_gpio_request_enable,
  631. .gpio_disable_free = sh_pfc_gpio_disable_free,
  632. };
  633. static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
  634. {
  635. unsigned int i;
  636. /* Allocate and initialize the pins and configs arrays. */
  637. pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
  638. GFP_KERNEL);
  639. if (unlikely(!pmx->configs))
  640. return -ENOMEM;
  641. for (i = 0; i < pfc->info->nr_pins; ++i) {
  642. struct sh_pfc_pin_config *cfg = &pmx->configs[i];
  643. cfg->type = PINMUX_TYPE_NONE;
  644. }
  645. return 0;
  646. }
  647. static int sh_pfc_pinctrl_probe(struct udevice *dev)
  648. {
  649. struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
  650. enum sh_pfc_model model = dev_get_driver_data(dev);
  651. fdt_addr_t base;
  652. base = devfdt_get_addr(dev);
  653. if (base == FDT_ADDR_T_NONE)
  654. return -EINVAL;
  655. priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
  656. if (!priv->pfc.regs)
  657. return -ENOMEM;
  658. #ifdef CONFIG_PINCTRL_PFC_R8A7790
  659. if (model == SH_PFC_R8A7790)
  660. priv->pfc.info = &r8a7790_pinmux_info;
  661. #endif
  662. #ifdef CONFIG_PINCTRL_PFC_R8A7791
  663. if (model == SH_PFC_R8A7791)
  664. priv->pfc.info = &r8a7791_pinmux_info;
  665. #endif
  666. #ifdef CONFIG_PINCTRL_PFC_R8A7792
  667. if (model == SH_PFC_R8A7792)
  668. priv->pfc.info = &r8a7792_pinmux_info;
  669. #endif
  670. #ifdef CONFIG_PINCTRL_PFC_R8A7793
  671. if (model == SH_PFC_R8A7793)
  672. priv->pfc.info = &r8a7793_pinmux_info;
  673. #endif
  674. #ifdef CONFIG_PINCTRL_PFC_R8A7794
  675. if (model == SH_PFC_R8A7794)
  676. priv->pfc.info = &r8a7794_pinmux_info;
  677. #endif
  678. #ifdef CONFIG_PINCTRL_PFC_R8A7795
  679. if (model == SH_PFC_R8A7795)
  680. priv->pfc.info = &r8a7795_pinmux_info;
  681. #endif
  682. #ifdef CONFIG_PINCTRL_PFC_R8A7796
  683. if (model == SH_PFC_R8A7796)
  684. priv->pfc.info = &r8a7796_pinmux_info;
  685. #endif
  686. #ifdef CONFIG_PINCTRL_PFC_R8A77965
  687. if (model == SH_PFC_R8A77965)
  688. priv->pfc.info = &r8a77965_pinmux_info;
  689. #endif
  690. #ifdef CONFIG_PINCTRL_PFC_R8A77970
  691. if (model == SH_PFC_R8A77970)
  692. priv->pfc.info = &r8a77970_pinmux_info;
  693. #endif
  694. #ifdef CONFIG_PINCTRL_PFC_R8A77980
  695. if (model == SH_PFC_R8A77980)
  696. priv->pfc.info = &r8a77980_pinmux_info;
  697. #endif
  698. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  699. if (model == SH_PFC_R8A77990)
  700. priv->pfc.info = &r8a77990_pinmux_info;
  701. #endif
  702. #ifdef CONFIG_PINCTRL_PFC_R8A77995
  703. if (model == SH_PFC_R8A77995)
  704. priv->pfc.info = &r8a77995_pinmux_info;
  705. #endif
  706. priv->pmx.pfc = &priv->pfc;
  707. sh_pfc_init_ranges(&priv->pfc);
  708. sh_pfc_map_pins(&priv->pfc, &priv->pmx);
  709. return 0;
  710. }
  711. static const struct udevice_id sh_pfc_pinctrl_ids[] = {
  712. #ifdef CONFIG_PINCTRL_PFC_R8A7790
  713. {
  714. .compatible = "renesas,pfc-r8a7790",
  715. .data = SH_PFC_R8A7790,
  716. },
  717. #endif
  718. #ifdef CONFIG_PINCTRL_PFC_R8A7791
  719. {
  720. .compatible = "renesas,pfc-r8a7791",
  721. .data = SH_PFC_R8A7791,
  722. },
  723. #endif
  724. #ifdef CONFIG_PINCTRL_PFC_R8A7792
  725. {
  726. .compatible = "renesas,pfc-r8a7792",
  727. .data = SH_PFC_R8A7792,
  728. },
  729. #endif
  730. #ifdef CONFIG_PINCTRL_PFC_R8A7793
  731. {
  732. .compatible = "renesas,pfc-r8a7793",
  733. .data = SH_PFC_R8A7793,
  734. },
  735. #endif
  736. #ifdef CONFIG_PINCTRL_PFC_R8A7794
  737. {
  738. .compatible = "renesas,pfc-r8a7794",
  739. .data = SH_PFC_R8A7794,
  740. },
  741. #endif
  742. #ifdef CONFIG_PINCTRL_PFC_R8A7795
  743. {
  744. .compatible = "renesas,pfc-r8a7795",
  745. .data = SH_PFC_R8A7795,
  746. },
  747. #endif
  748. #ifdef CONFIG_PINCTRL_PFC_R8A7796
  749. {
  750. .compatible = "renesas,pfc-r8a7796",
  751. .data = SH_PFC_R8A7796,
  752. },
  753. #endif
  754. #ifdef CONFIG_PINCTRL_PFC_R8A77965
  755. {
  756. .compatible = "renesas,pfc-r8a77965",
  757. .data = SH_PFC_R8A77965,
  758. },
  759. #endif
  760. #ifdef CONFIG_PINCTRL_PFC_R8A77970
  761. {
  762. .compatible = "renesas,pfc-r8a77970",
  763. .data = SH_PFC_R8A77970,
  764. },
  765. #endif
  766. #ifdef CONFIG_PINCTRL_PFC_R8A77980
  767. {
  768. .compatible = "renesas,pfc-r8a77980",
  769. .data = SH_PFC_R8A77980,
  770. },
  771. #endif
  772. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  773. {
  774. .compatible = "renesas,pfc-r8a77990",
  775. .data = SH_PFC_R8A77990,
  776. },
  777. #endif
  778. #ifdef CONFIG_PINCTRL_PFC_R8A77995
  779. {
  780. .compatible = "renesas,pfc-r8a77995",
  781. .data = SH_PFC_R8A77995,
  782. },
  783. #endif
  784. { },
  785. };
  786. U_BOOT_DRIVER(pinctrl_sh_pfc) = {
  787. .name = "sh_pfc_pinctrl",
  788. .id = UCLASS_PINCTRL,
  789. .of_match = sh_pfc_pinctrl_ids,
  790. .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
  791. .ops = &sh_pfc_pinctrl_ops,
  792. .probe = sh_pfc_pinctrl_probe,
  793. };