mvpp2.c 150 KB

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  1. /*
  2. * Driver for Marvell PPv2 network controller for Armada 375 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Marcin Wojtas <mw@semihalf.com>
  7. *
  8. * U-Boot version:
  9. * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <asm/cache.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/device_compat.h>
  21. #include <dm/devres.h>
  22. #include <dm/lists.h>
  23. #include <net.h>
  24. #include <netdev.h>
  25. #include <config.h>
  26. #include <malloc.h>
  27. #include <asm/io.h>
  28. #include <linux/bug.h>
  29. #include <linux/err.h>
  30. #include <linux/errno.h>
  31. #include <phy.h>
  32. #include <miiphy.h>
  33. #include <watchdog.h>
  34. #include <asm/arch/cpu.h>
  35. #include <asm/arch/soc.h>
  36. #include <linux/compat.h>
  37. #include <linux/libfdt.h>
  38. #include <linux/mbus.h>
  39. #include <asm-generic/gpio.h>
  40. #include <fdt_support.h>
  41. #include <linux/mdio.h>
  42. DECLARE_GLOBAL_DATA_PTR;
  43. #define __verify_pcpu_ptr(ptr) \
  44. do { \
  45. const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  46. (void)__vpp_verify; \
  47. } while (0)
  48. #define VERIFY_PERCPU_PTR(__p) \
  49. ({ \
  50. __verify_pcpu_ptr(__p); \
  51. (typeof(*(__p)) __kernel __force *)(__p); \
  52. })
  53. #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
  54. #define smp_processor_id() 0
  55. #define num_present_cpus() 1
  56. #define for_each_present_cpu(cpu) \
  57. for ((cpu) = 0; (cpu) < 1; (cpu)++)
  58. #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
  59. #define CONFIG_NR_CPUS 1
  60. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  61. #define WRAP (2 + ETH_HLEN + 4 + 32)
  62. #define MTU 1500
  63. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  64. /* RX Fifo Registers */
  65. #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
  66. #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
  67. #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
  68. #define MVPP2_RX_FIFO_INIT_REG 0x64
  69. /* RX DMA Top Registers */
  70. #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
  71. #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
  72. #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
  73. #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
  74. #define MVPP2_POOL_BUF_SIZE_OFFSET 5
  75. #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
  76. #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
  77. #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
  78. #define MVPP2_RXQ_POOL_SHORT_OFFS 20
  79. #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
  80. #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
  81. #define MVPP2_RXQ_POOL_LONG_OFFS 24
  82. #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
  83. #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
  84. #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
  85. #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
  86. #define MVPP2_RXQ_DISABLE_MASK BIT(31)
  87. /* Parser Registers */
  88. #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
  89. #define MVPP2_PRS_PORT_LU_MAX 0xf
  90. #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
  91. #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
  92. #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
  93. #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
  94. #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
  95. #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
  96. #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
  97. #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
  98. #define MVPP2_PRS_TCAM_IDX_REG 0x1100
  99. #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
  100. #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
  101. #define MVPP2_PRS_SRAM_IDX_REG 0x1200
  102. #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
  103. #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
  104. #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
  105. /* Classifier Registers */
  106. #define MVPP2_CLS_MODE_REG 0x1800
  107. #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
  108. #define MVPP2_CLS_PORT_WAY_REG 0x1810
  109. #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
  110. #define MVPP2_CLS_LKP_INDEX_REG 0x1814
  111. #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
  112. #define MVPP2_CLS_LKP_TBL_REG 0x1818
  113. #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
  114. #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
  115. #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
  116. #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
  117. #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
  118. #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
  119. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
  120. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
  121. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
  122. #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
  123. #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
  124. #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
  125. /* Descriptor Manager Top Registers */
  126. #define MVPP2_RXQ_NUM_REG 0x2040
  127. #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
  128. #define MVPP22_DESC_ADDR_OFFS 8
  129. #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
  130. #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
  131. #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
  132. #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
  133. #define MVPP2_RXQ_NUM_NEW_OFFSET 16
  134. #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
  135. #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
  136. #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
  137. #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
  138. #define MVPP2_RXQ_THRESH_REG 0x204c
  139. #define MVPP2_OCCUPIED_THRESH_OFFSET 0
  140. #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
  141. #define MVPP2_RXQ_INDEX_REG 0x2050
  142. #define MVPP2_TXQ_NUM_REG 0x2080
  143. #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
  144. #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
  145. #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
  146. #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
  147. #define MVPP2_TXQ_THRESH_REG 0x2094
  148. #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
  149. #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
  150. #define MVPP2_TXQ_INDEX_REG 0x2098
  151. #define MVPP2_TXQ_PREF_BUF_REG 0x209c
  152. #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
  153. #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
  154. #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
  155. #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
  156. #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
  157. #define MVPP2_TXQ_PENDING_REG 0x20a0
  158. #define MVPP2_TXQ_PENDING_MASK 0x3fff
  159. #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
  160. #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
  161. #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
  162. #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
  163. #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
  164. #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
  165. #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
  166. #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
  167. #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
  168. #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
  169. #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
  170. #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
  171. #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
  172. #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
  173. #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
  174. #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
  175. #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
  176. /* MBUS bridge registers */
  177. #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
  178. #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
  179. #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
  180. #define MVPP2_BASE_ADDR_ENABLE 0x4060
  181. /* AXI Bridge Registers */
  182. #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
  183. #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
  184. #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
  185. #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
  186. #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
  187. #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
  188. #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
  189. #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
  190. #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
  191. #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
  192. #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
  193. #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
  194. /* Values for AXI Bridge registers */
  195. #define MVPP22_AXI_ATTR_CACHE_OFFS 0
  196. #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
  197. #define MVPP22_AXI_CODE_CACHE_OFFS 0
  198. #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
  199. #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
  200. #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
  201. #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
  202. #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
  203. #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
  204. /* Interrupt Cause and Mask registers */
  205. #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
  206. #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
  207. #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
  208. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  209. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  210. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
  211. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  212. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  213. #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
  214. #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
  215. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
  216. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
  217. #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
  218. #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
  219. #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
  220. #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
  221. #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  222. #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
  223. #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
  224. #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
  225. #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
  226. #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
  227. #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
  228. #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
  229. #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
  230. #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
  231. #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  232. #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
  233. #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
  234. #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
  235. /* Buffer Manager registers */
  236. #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
  237. #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
  238. #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
  239. #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
  240. #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
  241. #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
  242. #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
  243. #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
  244. #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
  245. #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
  246. #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
  247. #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
  248. #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
  249. #define MVPP2_BM_START_MASK BIT(0)
  250. #define MVPP2_BM_STOP_MASK BIT(1)
  251. #define MVPP2_BM_STATE_MASK BIT(4)
  252. #define MVPP2_BM_LOW_THRESH_OFFS 8
  253. #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
  254. #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
  255. MVPP2_BM_LOW_THRESH_OFFS)
  256. #define MVPP2_BM_HIGH_THRESH_OFFS 16
  257. #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
  258. #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
  259. MVPP2_BM_HIGH_THRESH_OFFS)
  260. #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
  261. #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
  262. #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
  263. #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
  264. #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
  265. #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
  266. #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
  267. #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
  268. #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
  269. #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
  270. #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
  271. #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
  272. #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
  273. #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
  274. #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
  275. #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
  276. #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
  277. #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
  278. #define MVPP2_BM_VIRT_RLS_REG 0x64c0
  279. #define MVPP21_BM_MC_RLS_REG 0x64c4
  280. #define MVPP2_BM_MC_ID_MASK 0xfff
  281. #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
  282. #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
  283. #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
  284. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
  285. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
  286. #define MVPP22_BM_MC_RLS_REG 0x64d4
  287. #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
  288. #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
  289. /* TX Scheduler registers */
  290. #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
  291. #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
  292. #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
  293. #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
  294. #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
  295. #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
  296. #define MVPP2_TXP_SCHED_MTU_REG 0x801c
  297. #define MVPP2_TXP_MTU_MAX 0x7FFFF
  298. #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
  299. #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
  300. #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
  301. #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
  302. #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
  303. #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
  304. #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
  305. #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
  306. #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
  307. #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
  308. #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
  309. #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  310. #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
  311. #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
  312. /* TX general registers */
  313. #define MVPP2_TX_SNOOP_REG 0x8800
  314. #define MVPP2_TX_PORT_FLUSH_REG 0x8810
  315. #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
  316. /* LMS registers */
  317. #define MVPP2_SRC_ADDR_MIDDLE 0x24
  318. #define MVPP2_SRC_ADDR_HIGH 0x28
  319. #define MVPP2_PHY_AN_CFG0_REG 0x34
  320. #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
  321. #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
  322. #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
  323. /* Per-port registers */
  324. #define MVPP2_GMAC_CTRL_0_REG 0x0
  325. #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
  326. #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
  327. #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
  328. #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  329. #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
  330. #define MVPP2_GMAC_CTRL_1_REG 0x4
  331. #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
  332. #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
  333. #define MVPP2_GMAC_PCS_LB_EN_BIT 6
  334. #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
  335. #define MVPP2_GMAC_SA_LOW_OFFS 7
  336. #define MVPP2_GMAC_CTRL_2_REG 0x8
  337. #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
  338. #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
  339. #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
  340. #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
  341. #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
  342. #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
  343. #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
  344. #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
  345. #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
  346. #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
  347. #define MVPP2_GMAC_EN_PCS_AN BIT(2)
  348. #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
  349. #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
  350. #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
  351. #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
  352. #define MVPP2_GMAC_FC_ADV_EN BIT(9)
  353. #define MVPP2_GMAC_EN_FC_AN BIT(11)
  354. #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  355. #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
  356. #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
  357. #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
  358. #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
  359. #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
  360. #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
  361. MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
  362. #define MVPP2_GMAC_CTRL_4_REG 0x90
  363. #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
  364. #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
  365. #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
  366. #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
  367. /*
  368. * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
  369. * relative to port->base.
  370. */
  371. /* Port Mac Control0 */
  372. #define MVPP22_XLG_CTRL0_REG 0x100
  373. #define MVPP22_XLG_PORT_EN BIT(0)
  374. #define MVPP22_XLG_MAC_RESETN BIT(1)
  375. #define MVPP22_XLG_RX_FC_EN BIT(7)
  376. #define MVPP22_XLG_MIBCNT_DIS BIT(13)
  377. /* Port Mac Control1 */
  378. #define MVPP22_XLG_CTRL1_REG 0x104
  379. #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
  380. #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
  381. /* Port Interrupt Mask */
  382. #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
  383. #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
  384. /* Port Mac Control3 */
  385. #define MVPP22_XLG_CTRL3_REG 0x11c
  386. #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
  387. #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
  388. #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
  389. /* Port Mac Control4 */
  390. #define MVPP22_XLG_CTRL4_REG 0x184
  391. #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
  392. #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
  393. #define MVPP22_XLG_MODE_DMA_1G BIT(12)
  394. #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
  395. /* XPCS registers */
  396. /* Global Configuration 0 */
  397. #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
  398. #define MVPP22_XPCS_PCSRESET BIT(0)
  399. #define MVPP22_XPCS_PCSMODE_OFFS 3
  400. #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
  401. MVPP22_XPCS_PCSMODE_OFFS)
  402. #define MVPP22_XPCS_LANEACTIVE_OFFS 5
  403. #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
  404. MVPP22_XPCS_LANEACTIVE_OFFS)
  405. /* MPCS registers */
  406. #define PCS40G_COMMON_CONTROL 0x14
  407. #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
  408. #define PCS_CLOCK_RESET 0x14c
  409. #define TX_SD_CLK_RESET_MASK BIT(0)
  410. #define RX_SD_CLK_RESET_MASK BIT(1)
  411. #define MAC_CLK_RESET_MASK BIT(2)
  412. #define CLK_DIVISION_RATIO_OFFS 4
  413. #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
  414. #define CLK_DIV_PHASE_SET_MASK BIT(11)
  415. /* System Soft Reset 1 */
  416. #define GOP_SOFT_RESET_1_REG 0x108
  417. #define NETC_GOP_SOFT_RESET_OFFS 6
  418. #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
  419. NETC_GOP_SOFT_RESET_OFFS)
  420. /* Ports Control 0 */
  421. #define NETCOMP_PORTS_CONTROL_0_REG 0x110
  422. #define NETC_BUS_WIDTH_SELECT_OFFS 1
  423. #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
  424. NETC_BUS_WIDTH_SELECT_OFFS)
  425. #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
  426. #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
  427. NETC_GIG_RX_DATA_SAMPLE_OFFS)
  428. #define NETC_CLK_DIV_PHASE_OFFS 31
  429. #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
  430. /* Ports Control 1 */
  431. #define NETCOMP_PORTS_CONTROL_1_REG 0x114
  432. #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
  433. #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
  434. NETC_PORTS_ACTIVE_OFFSET(p))
  435. #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
  436. #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
  437. NETC_PORT_GIG_RF_RESET_OFFS(p))
  438. #define NETCOMP_CONTROL_0_REG 0x120
  439. #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
  440. #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
  441. NETC_GBE_PORT0_SGMII_MODE_OFFS)
  442. #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
  443. #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
  444. NETC_GBE_PORT1_SGMII_MODE_OFFS)
  445. #define NETC_GBE_PORT1_MII_MODE_OFFS 2
  446. #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
  447. NETC_GBE_PORT1_MII_MODE_OFFS)
  448. #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
  449. #define MVPP22_SMI_POLLING_EN BIT(10)
  450. #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
  451. (0x4 * (port)))
  452. #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  453. /* Descriptor ring Macros */
  454. #define MVPP2_QUEUE_NEXT_DESC(q, index) \
  455. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  456. /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
  457. #define MVPP22_SMI 0x1200
  458. /* Additional PPv2.2 offsets */
  459. #define MVPP22_MPCS 0x007000
  460. #define MVPP22_XPCS 0x007400
  461. #define MVPP22_PORT_BASE 0x007e00
  462. #define MVPP22_PORT_OFFSET 0x001000
  463. #define MVPP22_RFU1 0x318000
  464. /* Maximum number of ports */
  465. #define MVPP22_GOP_MAC_NUM 4
  466. /* Sets the field located at the specified in data */
  467. #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
  468. #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
  469. #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
  470. /* Net Complex */
  471. enum mv_netc_topology {
  472. MV_NETC_GE_MAC2_SGMII = BIT(0),
  473. MV_NETC_GE_MAC3_SGMII = BIT(1),
  474. MV_NETC_GE_MAC3_RGMII = BIT(2),
  475. };
  476. enum mv_netc_phase {
  477. MV_NETC_FIRST_PHASE,
  478. MV_NETC_SECOND_PHASE,
  479. };
  480. enum mv_netc_sgmii_xmi_mode {
  481. MV_NETC_GBE_SGMII,
  482. MV_NETC_GBE_XMII,
  483. };
  484. enum mv_netc_mii_mode {
  485. MV_NETC_GBE_RGMII,
  486. MV_NETC_GBE_MII,
  487. };
  488. enum mv_netc_lanes {
  489. MV_NETC_LANE_23,
  490. MV_NETC_LANE_45,
  491. };
  492. /* Various constants */
  493. /* Coalescing */
  494. #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
  495. #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
  496. #define MVPP2_RX_COAL_PKTS 32
  497. #define MVPP2_RX_COAL_USEC 100
  498. /* The two bytes Marvell header. Either contains a special value used
  499. * by Marvell switches when a specific hardware mode is enabled (not
  500. * supported by this driver) or is filled automatically by zeroes on
  501. * the RX side. Those two bytes being at the front of the Ethernet
  502. * header, they allow to have the IP header aligned on a 4 bytes
  503. * boundary automatically: the hardware skips those two bytes on its
  504. * own.
  505. */
  506. #define MVPP2_MH_SIZE 2
  507. #define MVPP2_ETH_TYPE_LEN 2
  508. #define MVPP2_PPPOE_HDR_SIZE 8
  509. #define MVPP2_VLAN_TAG_LEN 4
  510. /* Lbtd 802.3 type */
  511. #define MVPP2_IP_LBDT_TYPE 0xfffa
  512. #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
  513. #define MVPP2_TX_CSUM_MAX_SIZE 9800
  514. /* Timeout constants */
  515. #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
  516. #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
  517. #define MVPP2_TX_MTU_MAX 0x7ffff
  518. /* Maximum number of T-CONTs of PON port */
  519. #define MVPP2_MAX_TCONT 16
  520. /* Maximum number of supported ports */
  521. #define MVPP2_MAX_PORTS 4
  522. /* Maximum number of TXQs used by single port */
  523. #define MVPP2_MAX_TXQ 8
  524. /* Default number of TXQs in use */
  525. #define MVPP2_DEFAULT_TXQ 1
  526. /* Default number of RXQs in use */
  527. #define MVPP2_DEFAULT_RXQ 1
  528. #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
  529. /* Max number of Rx descriptors */
  530. #define MVPP2_MAX_RXD 16
  531. /* Max number of Tx descriptors */
  532. #define MVPP2_MAX_TXD 16
  533. /* Amount of Tx descriptors that can be reserved at once by CPU */
  534. #define MVPP2_CPU_DESC_CHUNK 16
  535. /* Max number of Tx descriptors in each aggregated queue */
  536. #define MVPP2_AGGR_TXQ_SIZE 16
  537. /* Descriptor aligned size */
  538. #define MVPP2_DESC_ALIGNED_SIZE 32
  539. /* Descriptor alignment mask */
  540. #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
  541. /* RX FIFO constants */
  542. #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
  543. #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
  544. #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
  545. #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
  546. #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
  547. #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
  548. #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
  549. #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
  550. #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
  551. /* TX general registers */
  552. #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
  553. #define MVPP22_TX_FIFO_SIZE_MASK 0xf
  554. /* TX FIFO constants */
  555. #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
  556. #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
  557. /* RX buffer constants */
  558. #define MVPP2_SKB_SHINFO_SIZE \
  559. 0
  560. #define MVPP2_RX_PKT_SIZE(mtu) \
  561. ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
  562. ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
  563. #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
  564. #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
  565. #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
  566. ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
  567. #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
  568. /* IPv6 max L3 address size */
  569. #define MVPP2_MAX_L3_ADDR_SIZE 16
  570. /* Port flags */
  571. #define MVPP2_F_LOOPBACK BIT(0)
  572. /* Marvell tag types */
  573. enum mvpp2_tag_type {
  574. MVPP2_TAG_TYPE_NONE = 0,
  575. MVPP2_TAG_TYPE_MH = 1,
  576. MVPP2_TAG_TYPE_DSA = 2,
  577. MVPP2_TAG_TYPE_EDSA = 3,
  578. MVPP2_TAG_TYPE_VLAN = 4,
  579. MVPP2_TAG_TYPE_LAST = 5
  580. };
  581. /* Parser constants */
  582. #define MVPP2_PRS_TCAM_SRAM_SIZE 256
  583. #define MVPP2_PRS_TCAM_WORDS 6
  584. #define MVPP2_PRS_SRAM_WORDS 4
  585. #define MVPP2_PRS_FLOW_ID_SIZE 64
  586. #define MVPP2_PRS_FLOW_ID_MASK 0x3f
  587. #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
  588. #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
  589. #define MVPP2_PRS_IPV4_HEAD 0x40
  590. #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
  591. #define MVPP2_PRS_IPV4_MC 0xe0
  592. #define MVPP2_PRS_IPV4_MC_MASK 0xf0
  593. #define MVPP2_PRS_IPV4_BC_MASK 0xff
  594. #define MVPP2_PRS_IPV4_IHL 0x5
  595. #define MVPP2_PRS_IPV4_IHL_MASK 0xf
  596. #define MVPP2_PRS_IPV6_MC 0xff
  597. #define MVPP2_PRS_IPV6_MC_MASK 0xff
  598. #define MVPP2_PRS_IPV6_HOP_MASK 0xff
  599. #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
  600. #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
  601. #define MVPP2_PRS_DBL_VLANS_MAX 100
  602. /* Tcam structure:
  603. * - lookup ID - 4 bits
  604. * - port ID - 1 byte
  605. * - additional information - 1 byte
  606. * - header data - 8 bytes
  607. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
  608. */
  609. #define MVPP2_PRS_AI_BITS 8
  610. #define MVPP2_PRS_PORT_MASK 0xff
  611. #define MVPP2_PRS_LU_MASK 0xf
  612. #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
  613. (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
  614. #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
  615. (((offs) * 2) - ((offs) % 2) + 2)
  616. #define MVPP2_PRS_TCAM_AI_BYTE 16
  617. #define MVPP2_PRS_TCAM_PORT_BYTE 17
  618. #define MVPP2_PRS_TCAM_LU_BYTE 20
  619. #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
  620. #define MVPP2_PRS_TCAM_INV_WORD 5
  621. /* Tcam entries ID */
  622. #define MVPP2_PE_DROP_ALL 0
  623. #define MVPP2_PE_FIRST_FREE_TID 1
  624. #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
  625. #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
  626. #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
  627. #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
  628. #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
  629. #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
  630. #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
  631. #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
  632. #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
  633. #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
  634. #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
  635. #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
  636. #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
  637. #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
  638. #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
  639. #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
  640. #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
  641. #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
  642. #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
  643. #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
  644. #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
  645. #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
  646. #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
  647. #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
  648. #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  649. /* Sram structure
  650. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
  651. */
  652. #define MVPP2_PRS_SRAM_RI_OFFS 0
  653. #define MVPP2_PRS_SRAM_RI_WORD 0
  654. #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
  655. #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
  656. #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
  657. #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
  658. #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
  659. #define MVPP2_PRS_SRAM_UDF_OFFS 73
  660. #define MVPP2_PRS_SRAM_UDF_BITS 8
  661. #define MVPP2_PRS_SRAM_UDF_MASK 0xff
  662. #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
  663. #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
  664. #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
  665. #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
  666. #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
  667. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
  668. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
  669. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
  670. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
  671. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
  672. #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
  673. #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
  674. #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
  675. #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
  676. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
  677. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
  678. #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
  679. #define MVPP2_PRS_SRAM_AI_OFFS 90
  680. #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
  681. #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
  682. #define MVPP2_PRS_SRAM_AI_MASK 0xff
  683. #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
  684. #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
  685. #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
  686. #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
  687. /* Sram result info bits assignment */
  688. #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
  689. #define MVPP2_PRS_RI_DSA_MASK 0x2
  690. #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
  691. #define MVPP2_PRS_RI_VLAN_NONE 0x0
  692. #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
  693. #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
  694. #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
  695. #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
  696. #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
  697. #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
  698. #define MVPP2_PRS_RI_L2_UCAST 0x0
  699. #define MVPP2_PRS_RI_L2_MCAST BIT(9)
  700. #define MVPP2_PRS_RI_L2_BCAST BIT(10)
  701. #define MVPP2_PRS_RI_PPPOE_MASK 0x800
  702. #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
  703. #define MVPP2_PRS_RI_L3_UN 0x0
  704. #define MVPP2_PRS_RI_L3_IP4 BIT(12)
  705. #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
  706. #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
  707. #define MVPP2_PRS_RI_L3_IP6 BIT(14)
  708. #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
  709. #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
  710. #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
  711. #define MVPP2_PRS_RI_L3_UCAST 0x0
  712. #define MVPP2_PRS_RI_L3_MCAST BIT(15)
  713. #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
  714. #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
  715. #define MVPP2_PRS_RI_UDF3_MASK 0x300000
  716. #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
  717. #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
  718. #define MVPP2_PRS_RI_L4_TCP BIT(22)
  719. #define MVPP2_PRS_RI_L4_UDP BIT(23)
  720. #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
  721. #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
  722. #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
  723. #define MVPP2_PRS_RI_DROP_MASK 0x80000000
  724. /* Sram additional info bits assignment */
  725. #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
  726. #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
  727. #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
  728. #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
  729. #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
  730. #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
  731. #define MVPP2_PRS_SINGLE_VLAN_AI 0
  732. #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
  733. /* DSA/EDSA type */
  734. #define MVPP2_PRS_TAGGED true
  735. #define MVPP2_PRS_UNTAGGED false
  736. #define MVPP2_PRS_EDSA true
  737. #define MVPP2_PRS_DSA false
  738. /* MAC entries, shadow udf */
  739. enum mvpp2_prs_udf {
  740. MVPP2_PRS_UDF_MAC_DEF,
  741. MVPP2_PRS_UDF_MAC_RANGE,
  742. MVPP2_PRS_UDF_L2_DEF,
  743. MVPP2_PRS_UDF_L2_DEF_COPY,
  744. MVPP2_PRS_UDF_L2_USER,
  745. };
  746. /* Lookup ID */
  747. enum mvpp2_prs_lookup {
  748. MVPP2_PRS_LU_MH,
  749. MVPP2_PRS_LU_MAC,
  750. MVPP2_PRS_LU_DSA,
  751. MVPP2_PRS_LU_VLAN,
  752. MVPP2_PRS_LU_L2,
  753. MVPP2_PRS_LU_PPPOE,
  754. MVPP2_PRS_LU_IP4,
  755. MVPP2_PRS_LU_IP6,
  756. MVPP2_PRS_LU_FLOWS,
  757. MVPP2_PRS_LU_LAST,
  758. };
  759. /* L3 cast enum */
  760. enum mvpp2_prs_l3_cast {
  761. MVPP2_PRS_L3_UNI_CAST,
  762. MVPP2_PRS_L3_MULTI_CAST,
  763. MVPP2_PRS_L3_BROAD_CAST
  764. };
  765. /* Classifier constants */
  766. #define MVPP2_CLS_FLOWS_TBL_SIZE 512
  767. #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
  768. #define MVPP2_CLS_LKP_TBL_SIZE 64
  769. /* BM constants */
  770. #define MVPP2_BM_POOLS_NUM 1
  771. #define MVPP2_BM_LONG_BUF_NUM 16
  772. #define MVPP2_BM_SHORT_BUF_NUM 16
  773. #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
  774. #define MVPP2_BM_POOL_PTR_ALIGN 128
  775. #define MVPP2_BM_SWF_LONG_POOL(port) 0
  776. /* BM cookie (32 bits) definition */
  777. #define MVPP2_BM_COOKIE_POOL_OFFS 8
  778. #define MVPP2_BM_COOKIE_CPU_OFFS 24
  779. /* BM short pool packet size
  780. * These value assure that for SWF the total number
  781. * of bytes allocated for each buffer will be 512
  782. */
  783. #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
  784. enum mvpp2_bm_type {
  785. MVPP2_BM_FREE,
  786. MVPP2_BM_SWF_LONG,
  787. MVPP2_BM_SWF_SHORT
  788. };
  789. /* Definitions */
  790. /* Shared Packet Processor resources */
  791. struct mvpp2 {
  792. /* Shared registers' base addresses */
  793. void __iomem *base;
  794. void __iomem *lms_base;
  795. void __iomem *iface_base;
  796. void __iomem *mpcs_base;
  797. void __iomem *xpcs_base;
  798. void __iomem *rfu1_base;
  799. u32 netc_config;
  800. /* List of pointers to port structures */
  801. struct mvpp2_port **port_list;
  802. /* Aggregated TXQs */
  803. struct mvpp2_tx_queue *aggr_txqs;
  804. /* BM pools */
  805. struct mvpp2_bm_pool *bm_pools;
  806. /* PRS shadow table */
  807. struct mvpp2_prs_shadow *prs_shadow;
  808. /* PRS auxiliary table for double vlan entries control */
  809. bool *prs_double_vlans;
  810. /* Tclk value */
  811. u32 tclk;
  812. /* HW version */
  813. enum { MVPP21, MVPP22 } hw_version;
  814. /* Maximum number of RXQs per port */
  815. unsigned int max_port_rxqs;
  816. int probe_done;
  817. u8 num_ports;
  818. };
  819. struct mvpp2_pcpu_stats {
  820. u64 rx_packets;
  821. u64 rx_bytes;
  822. u64 tx_packets;
  823. u64 tx_bytes;
  824. };
  825. struct mvpp2_port {
  826. u8 id;
  827. /* Index of the port from the "group of ports" complex point
  828. * of view
  829. */
  830. int gop_id;
  831. int irq;
  832. struct mvpp2 *priv;
  833. /* Per-port registers' base address */
  834. void __iomem *base;
  835. struct mvpp2_rx_queue **rxqs;
  836. struct mvpp2_tx_queue **txqs;
  837. int pkt_size;
  838. u32 pending_cause_rx;
  839. /* Per-CPU port control */
  840. struct mvpp2_port_pcpu __percpu *pcpu;
  841. /* Flags */
  842. unsigned long flags;
  843. u16 tx_ring_size;
  844. u16 rx_ring_size;
  845. struct mvpp2_pcpu_stats __percpu *stats;
  846. struct phy_device *phy_dev;
  847. phy_interface_t phy_interface;
  848. int phyaddr;
  849. struct udevice *mdio_dev;
  850. struct mii_dev *bus;
  851. #if CONFIG_IS_ENABLED(DM_GPIO)
  852. struct gpio_desc phy_reset_gpio;
  853. struct gpio_desc phy_tx_disable_gpio;
  854. #endif
  855. int init;
  856. unsigned int link;
  857. unsigned int duplex;
  858. unsigned int speed;
  859. unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
  860. struct mvpp2_bm_pool *pool_long;
  861. struct mvpp2_bm_pool *pool_short;
  862. /* Index of first port's physical RXQ */
  863. u8 first_rxq;
  864. u8 dev_addr[ETH_ALEN];
  865. };
  866. /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
  867. * layout of the transmit and reception DMA descriptors, and their
  868. * layout is therefore defined by the hardware design
  869. */
  870. #define MVPP2_TXD_L3_OFF_SHIFT 0
  871. #define MVPP2_TXD_IP_HLEN_SHIFT 8
  872. #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
  873. #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
  874. #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
  875. #define MVPP2_TXD_PADDING_DISABLE BIT(23)
  876. #define MVPP2_TXD_L4_UDP BIT(24)
  877. #define MVPP2_TXD_L3_IP6 BIT(26)
  878. #define MVPP2_TXD_L_DESC BIT(28)
  879. #define MVPP2_TXD_F_DESC BIT(29)
  880. #define MVPP2_RXD_ERR_SUMMARY BIT(15)
  881. #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
  882. #define MVPP2_RXD_ERR_CRC 0x0
  883. #define MVPP2_RXD_ERR_OVERRUN BIT(13)
  884. #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
  885. #define MVPP2_RXD_BM_POOL_ID_OFFS 16
  886. #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
  887. #define MVPP2_RXD_HWF_SYNC BIT(21)
  888. #define MVPP2_RXD_L4_CSUM_OK BIT(22)
  889. #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
  890. #define MVPP2_RXD_L4_TCP BIT(25)
  891. #define MVPP2_RXD_L4_UDP BIT(26)
  892. #define MVPP2_RXD_L3_IP4 BIT(28)
  893. #define MVPP2_RXD_L3_IP6 BIT(30)
  894. #define MVPP2_RXD_BUF_HDR BIT(31)
  895. /* HW TX descriptor for PPv2.1 */
  896. struct mvpp21_tx_desc {
  897. u32 command; /* Options used by HW for packet transmitting.*/
  898. u8 packet_offset; /* the offset from the buffer beginning */
  899. u8 phys_txq; /* destination queue ID */
  900. u16 data_size; /* data size of transmitted packet in bytes */
  901. u32 buf_dma_addr; /* physical addr of transmitted buffer */
  902. u32 buf_cookie; /* cookie for access to TX buffer in tx path */
  903. u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
  904. u32 reserved2; /* reserved (for future use) */
  905. };
  906. /* HW RX descriptor for PPv2.1 */
  907. struct mvpp21_rx_desc {
  908. u32 status; /* info about received packet */
  909. u16 reserved1; /* parser_info (for future use, PnC) */
  910. u16 data_size; /* size of received packet in bytes */
  911. u32 buf_dma_addr; /* physical address of the buffer */
  912. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  913. u16 reserved2; /* gem_port_id (for future use, PON) */
  914. u16 reserved3; /* csum_l4 (for future use, PnC) */
  915. u8 reserved4; /* bm_qset (for future use, BM) */
  916. u8 reserved5;
  917. u16 reserved6; /* classify_info (for future use, PnC) */
  918. u32 reserved7; /* flow_id (for future use, PnC) */
  919. u32 reserved8;
  920. };
  921. /* HW TX descriptor for PPv2.2 */
  922. struct mvpp22_tx_desc {
  923. u32 command;
  924. u8 packet_offset;
  925. u8 phys_txq;
  926. u16 data_size;
  927. u64 reserved1;
  928. u64 buf_dma_addr_ptp;
  929. u64 buf_cookie_misc;
  930. };
  931. /* HW RX descriptor for PPv2.2 */
  932. struct mvpp22_rx_desc {
  933. u32 status;
  934. u16 reserved1;
  935. u16 data_size;
  936. u32 reserved2;
  937. u32 reserved3;
  938. u64 buf_dma_addr_key_hash;
  939. u64 buf_cookie_misc;
  940. };
  941. /* Opaque type used by the driver to manipulate the HW TX and RX
  942. * descriptors
  943. */
  944. struct mvpp2_tx_desc {
  945. union {
  946. struct mvpp21_tx_desc pp21;
  947. struct mvpp22_tx_desc pp22;
  948. };
  949. };
  950. struct mvpp2_rx_desc {
  951. union {
  952. struct mvpp21_rx_desc pp21;
  953. struct mvpp22_rx_desc pp22;
  954. };
  955. };
  956. /* Per-CPU Tx queue control */
  957. struct mvpp2_txq_pcpu {
  958. int cpu;
  959. /* Number of Tx DMA descriptors in the descriptor ring */
  960. int size;
  961. /* Number of currently used Tx DMA descriptor in the
  962. * descriptor ring
  963. */
  964. int count;
  965. /* Number of Tx DMA descriptors reserved for each CPU */
  966. int reserved_num;
  967. /* Index of last TX DMA descriptor that was inserted */
  968. int txq_put_index;
  969. /* Index of the TX DMA descriptor to be cleaned up */
  970. int txq_get_index;
  971. };
  972. struct mvpp2_tx_queue {
  973. /* Physical number of this Tx queue */
  974. u8 id;
  975. /* Logical number of this Tx queue */
  976. u8 log_id;
  977. /* Number of Tx DMA descriptors in the descriptor ring */
  978. int size;
  979. /* Number of currently used Tx DMA descriptor in the descriptor ring */
  980. int count;
  981. /* Per-CPU control of physical Tx queues */
  982. struct mvpp2_txq_pcpu __percpu *pcpu;
  983. u32 done_pkts_coal;
  984. /* Virtual address of thex Tx DMA descriptors array */
  985. struct mvpp2_tx_desc *descs;
  986. /* DMA address of the Tx DMA descriptors array */
  987. dma_addr_t descs_dma;
  988. /* Index of the last Tx DMA descriptor */
  989. int last_desc;
  990. /* Index of the next Tx DMA descriptor to process */
  991. int next_desc_to_proc;
  992. };
  993. struct mvpp2_rx_queue {
  994. /* RX queue number, in the range 0-31 for physical RXQs */
  995. u8 id;
  996. /* Num of rx descriptors in the rx descriptor ring */
  997. int size;
  998. u32 pkts_coal;
  999. u32 time_coal;
  1000. /* Virtual address of the RX DMA descriptors array */
  1001. struct mvpp2_rx_desc *descs;
  1002. /* DMA address of the RX DMA descriptors array */
  1003. dma_addr_t descs_dma;
  1004. /* Index of the last RX DMA descriptor */
  1005. int last_desc;
  1006. /* Index of the next RX DMA descriptor to process */
  1007. int next_desc_to_proc;
  1008. /* ID of port to which physical RXQ is mapped */
  1009. int port;
  1010. /* Port's logic RXQ number to which physical RXQ is mapped */
  1011. int logic_rxq;
  1012. };
  1013. union mvpp2_prs_tcam_entry {
  1014. u32 word[MVPP2_PRS_TCAM_WORDS];
  1015. u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
  1016. };
  1017. union mvpp2_prs_sram_entry {
  1018. u32 word[MVPP2_PRS_SRAM_WORDS];
  1019. u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
  1020. };
  1021. struct mvpp2_prs_entry {
  1022. u32 index;
  1023. union mvpp2_prs_tcam_entry tcam;
  1024. union mvpp2_prs_sram_entry sram;
  1025. };
  1026. struct mvpp2_prs_shadow {
  1027. bool valid;
  1028. bool finish;
  1029. /* Lookup ID */
  1030. int lu;
  1031. /* User defined offset */
  1032. int udf;
  1033. /* Result info */
  1034. u32 ri;
  1035. u32 ri_mask;
  1036. };
  1037. struct mvpp2_cls_flow_entry {
  1038. u32 index;
  1039. u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
  1040. };
  1041. struct mvpp2_cls_lookup_entry {
  1042. u32 lkpid;
  1043. u32 way;
  1044. u32 data;
  1045. };
  1046. struct mvpp2_bm_pool {
  1047. /* Pool number in the range 0-7 */
  1048. int id;
  1049. enum mvpp2_bm_type type;
  1050. /* Buffer Pointers Pool External (BPPE) size */
  1051. int size;
  1052. /* Number of buffers for this pool */
  1053. int buf_num;
  1054. /* Pool buffer size */
  1055. int buf_size;
  1056. /* Packet size */
  1057. int pkt_size;
  1058. /* BPPE virtual base address */
  1059. unsigned long *virt_addr;
  1060. /* BPPE DMA base address */
  1061. dma_addr_t dma_addr;
  1062. /* Ports using BM pool */
  1063. u32 port_map;
  1064. };
  1065. /* Static declaractions */
  1066. /* Number of RXQs used by single port */
  1067. static int rxq_number = MVPP2_DEFAULT_RXQ;
  1068. /* Number of TXQs used by single port */
  1069. static int txq_number = MVPP2_DEFAULT_TXQ;
  1070. static int base_id;
  1071. #define MVPP2_DRIVER_NAME "mvpp2"
  1072. #define MVPP2_DRIVER_VERSION "1.0"
  1073. /*
  1074. * U-Boot internal data, mostly uncached buffers for descriptors and data
  1075. */
  1076. struct buffer_location {
  1077. struct mvpp2_tx_desc *aggr_tx_descs;
  1078. struct mvpp2_tx_desc *tx_descs;
  1079. struct mvpp2_rx_desc *rx_descs;
  1080. unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
  1081. unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
  1082. int first_rxq;
  1083. };
  1084. /*
  1085. * All 4 interfaces use the same global buffer, since only one interface
  1086. * can be enabled at once
  1087. */
  1088. static struct buffer_location buffer_loc;
  1089. /*
  1090. * Page table entries are set to 1MB, or multiples of 1MB
  1091. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  1092. */
  1093. #define BD_SPACE (1 << 20)
  1094. /* Utility/helper methods */
  1095. static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  1096. {
  1097. writel(data, priv->base + offset);
  1098. }
  1099. static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  1100. {
  1101. return readl(priv->base + offset);
  1102. }
  1103. static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
  1104. struct mvpp2_tx_desc *tx_desc,
  1105. dma_addr_t dma_addr)
  1106. {
  1107. if (port->priv->hw_version == MVPP21) {
  1108. tx_desc->pp21.buf_dma_addr = dma_addr;
  1109. } else {
  1110. u64 val = (u64)dma_addr;
  1111. tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
  1112. tx_desc->pp22.buf_dma_addr_ptp |= val;
  1113. }
  1114. }
  1115. static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  1116. struct mvpp2_tx_desc *tx_desc,
  1117. size_t size)
  1118. {
  1119. if (port->priv->hw_version == MVPP21)
  1120. tx_desc->pp21.data_size = size;
  1121. else
  1122. tx_desc->pp22.data_size = size;
  1123. }
  1124. static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
  1125. struct mvpp2_tx_desc *tx_desc,
  1126. unsigned int txq)
  1127. {
  1128. if (port->priv->hw_version == MVPP21)
  1129. tx_desc->pp21.phys_txq = txq;
  1130. else
  1131. tx_desc->pp22.phys_txq = txq;
  1132. }
  1133. static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
  1134. struct mvpp2_tx_desc *tx_desc,
  1135. unsigned int command)
  1136. {
  1137. if (port->priv->hw_version == MVPP21)
  1138. tx_desc->pp21.command = command;
  1139. else
  1140. tx_desc->pp22.command = command;
  1141. }
  1142. static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
  1143. struct mvpp2_tx_desc *tx_desc,
  1144. unsigned int offset)
  1145. {
  1146. if (port->priv->hw_version == MVPP21)
  1147. tx_desc->pp21.packet_offset = offset;
  1148. else
  1149. tx_desc->pp22.packet_offset = offset;
  1150. }
  1151. static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
  1152. struct mvpp2_rx_desc *rx_desc)
  1153. {
  1154. if (port->priv->hw_version == MVPP21)
  1155. return rx_desc->pp21.buf_dma_addr;
  1156. else
  1157. return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
  1158. }
  1159. static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
  1160. struct mvpp2_rx_desc *rx_desc)
  1161. {
  1162. if (port->priv->hw_version == MVPP21)
  1163. return rx_desc->pp21.buf_cookie;
  1164. else
  1165. return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
  1166. }
  1167. static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
  1168. struct mvpp2_rx_desc *rx_desc)
  1169. {
  1170. if (port->priv->hw_version == MVPP21)
  1171. return rx_desc->pp21.data_size;
  1172. else
  1173. return rx_desc->pp22.data_size;
  1174. }
  1175. static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
  1176. struct mvpp2_rx_desc *rx_desc)
  1177. {
  1178. if (port->priv->hw_version == MVPP21)
  1179. return rx_desc->pp21.status;
  1180. else
  1181. return rx_desc->pp22.status;
  1182. }
  1183. static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
  1184. {
  1185. txq_pcpu->txq_get_index++;
  1186. if (txq_pcpu->txq_get_index == txq_pcpu->size)
  1187. txq_pcpu->txq_get_index = 0;
  1188. }
  1189. /* Get number of physical egress port */
  1190. static inline int mvpp2_egress_port(struct mvpp2_port *port)
  1191. {
  1192. return MVPP2_MAX_TCONT + port->id;
  1193. }
  1194. /* Get number of physical TXQ */
  1195. static inline int mvpp2_txq_phys(int port, int txq)
  1196. {
  1197. return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
  1198. }
  1199. /* Parser configuration routines */
  1200. /* Update parser tcam and sram hw entries */
  1201. static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1202. {
  1203. int i;
  1204. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1205. return -EINVAL;
  1206. /* Clear entry invalidation bit */
  1207. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
  1208. /* Write tcam index - indirect access */
  1209. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1210. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1211. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
  1212. /* Write sram index - indirect access */
  1213. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1214. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1215. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
  1216. return 0;
  1217. }
  1218. /* Read tcam entry from hw */
  1219. static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1220. {
  1221. int i;
  1222. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1223. return -EINVAL;
  1224. /* Write tcam index - indirect access */
  1225. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1226. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
  1227. MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
  1228. if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
  1229. return MVPP2_PRS_TCAM_ENTRY_INVALID;
  1230. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1231. pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
  1232. /* Write sram index - indirect access */
  1233. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1234. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1235. pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
  1236. return 0;
  1237. }
  1238. /* Invalidate tcam hw entry */
  1239. static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
  1240. {
  1241. /* Write index - indirect access */
  1242. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1243. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
  1244. MVPP2_PRS_TCAM_INV_MASK);
  1245. }
  1246. /* Enable shadow table entry and set its lookup ID */
  1247. static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
  1248. {
  1249. priv->prs_shadow[index].valid = true;
  1250. priv->prs_shadow[index].lu = lu;
  1251. }
  1252. /* Update ri fields in shadow table entry */
  1253. static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
  1254. unsigned int ri, unsigned int ri_mask)
  1255. {
  1256. priv->prs_shadow[index].ri_mask = ri_mask;
  1257. priv->prs_shadow[index].ri = ri;
  1258. }
  1259. /* Update lookup field in tcam sw entry */
  1260. static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
  1261. {
  1262. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
  1263. pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
  1264. pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
  1265. }
  1266. /* Update mask for single port in tcam sw entry */
  1267. static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
  1268. unsigned int port, bool add)
  1269. {
  1270. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1271. if (add)
  1272. pe->tcam.byte[enable_off] &= ~(1 << port);
  1273. else
  1274. pe->tcam.byte[enable_off] |= 1 << port;
  1275. }
  1276. /* Update port map in tcam sw entry */
  1277. static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
  1278. unsigned int ports)
  1279. {
  1280. unsigned char port_mask = MVPP2_PRS_PORT_MASK;
  1281. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1282. pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
  1283. pe->tcam.byte[enable_off] &= ~port_mask;
  1284. pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
  1285. }
  1286. /* Obtain port map from tcam sw entry */
  1287. static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
  1288. {
  1289. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1290. return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
  1291. }
  1292. /* Set byte of data and its enable bits in tcam sw entry */
  1293. static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
  1294. unsigned int offs, unsigned char byte,
  1295. unsigned char enable)
  1296. {
  1297. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
  1298. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
  1299. }
  1300. /* Get byte of data and its enable bits from tcam sw entry */
  1301. static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
  1302. unsigned int offs, unsigned char *byte,
  1303. unsigned char *enable)
  1304. {
  1305. *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
  1306. *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
  1307. }
  1308. /* Set ethertype in tcam sw entry */
  1309. static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
  1310. unsigned short ethertype)
  1311. {
  1312. mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
  1313. mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
  1314. }
  1315. /* Set bits in sram sw entry */
  1316. static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
  1317. int val)
  1318. {
  1319. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
  1320. }
  1321. /* Clear bits in sram sw entry */
  1322. static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
  1323. int val)
  1324. {
  1325. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
  1326. }
  1327. /* Update ri bits in sram sw entry */
  1328. static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
  1329. unsigned int bits, unsigned int mask)
  1330. {
  1331. unsigned int i;
  1332. for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
  1333. int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
  1334. if (!(mask & BIT(i)))
  1335. continue;
  1336. if (bits & BIT(i))
  1337. mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
  1338. else
  1339. mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
  1340. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
  1341. }
  1342. }
  1343. /* Update ai bits in sram sw entry */
  1344. static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
  1345. unsigned int bits, unsigned int mask)
  1346. {
  1347. unsigned int i;
  1348. int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
  1349. for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
  1350. if (!(mask & BIT(i)))
  1351. continue;
  1352. if (bits & BIT(i))
  1353. mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
  1354. else
  1355. mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
  1356. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
  1357. }
  1358. }
  1359. /* Read ai bits from sram sw entry */
  1360. static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
  1361. {
  1362. u8 bits;
  1363. int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
  1364. int ai_en_off = ai_off + 1;
  1365. int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
  1366. bits = (pe->sram.byte[ai_off] >> ai_shift) |
  1367. (pe->sram.byte[ai_en_off] << (8 - ai_shift));
  1368. return bits;
  1369. }
  1370. /* In sram sw entry set lookup ID field of the tcam key to be used in the next
  1371. * lookup interation
  1372. */
  1373. static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
  1374. unsigned int lu)
  1375. {
  1376. int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
  1377. mvpp2_prs_sram_bits_clear(pe, sram_next_off,
  1378. MVPP2_PRS_SRAM_NEXT_LU_MASK);
  1379. mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
  1380. }
  1381. /* In the sram sw entry set sign and value of the next lookup offset
  1382. * and the offset value generated to the classifier
  1383. */
  1384. static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
  1385. unsigned int op)
  1386. {
  1387. /* Set sign */
  1388. if (shift < 0) {
  1389. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1390. shift = 0 - shift;
  1391. } else {
  1392. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1393. }
  1394. /* Set value */
  1395. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
  1396. (unsigned char)shift;
  1397. /* Reset and set operation */
  1398. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
  1399. MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
  1400. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
  1401. /* Set base offset as current */
  1402. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1403. }
  1404. /* In the sram sw entry set sign and value of the user defined offset
  1405. * generated to the classifier
  1406. */
  1407. static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
  1408. unsigned int type, int offset,
  1409. unsigned int op)
  1410. {
  1411. /* Set sign */
  1412. if (offset < 0) {
  1413. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1414. offset = 0 - offset;
  1415. } else {
  1416. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1417. }
  1418. /* Set value */
  1419. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
  1420. MVPP2_PRS_SRAM_UDF_MASK);
  1421. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
  1422. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1423. MVPP2_PRS_SRAM_UDF_BITS)] &=
  1424. ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1425. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1426. MVPP2_PRS_SRAM_UDF_BITS)] |=
  1427. (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1428. /* Set offset type */
  1429. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
  1430. MVPP2_PRS_SRAM_UDF_TYPE_MASK);
  1431. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
  1432. /* Set offset operation */
  1433. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
  1434. MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
  1435. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
  1436. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1437. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
  1438. ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
  1439. (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1440. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1441. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
  1442. (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1443. /* Set base offset as current */
  1444. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1445. }
  1446. /* Find parser flow entry */
  1447. static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
  1448. {
  1449. struct mvpp2_prs_entry *pe;
  1450. int tid;
  1451. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1452. if (!pe)
  1453. return NULL;
  1454. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1455. /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
  1456. for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
  1457. u8 bits;
  1458. if (!priv->prs_shadow[tid].valid ||
  1459. priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
  1460. continue;
  1461. pe->index = tid;
  1462. mvpp2_prs_hw_read(priv, pe);
  1463. bits = mvpp2_prs_sram_ai_get(pe);
  1464. /* Sram store classification lookup ID in AI bits [5:0] */
  1465. if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
  1466. return pe;
  1467. }
  1468. kfree(pe);
  1469. return NULL;
  1470. }
  1471. /* Return first free tcam index, seeking from start to end */
  1472. static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
  1473. unsigned char end)
  1474. {
  1475. int tid;
  1476. if (start > end)
  1477. swap(start, end);
  1478. if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
  1479. end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
  1480. for (tid = start; tid <= end; tid++) {
  1481. if (!priv->prs_shadow[tid].valid)
  1482. return tid;
  1483. }
  1484. return -EINVAL;
  1485. }
  1486. /* Enable/disable dropping all mac da's */
  1487. static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
  1488. {
  1489. struct mvpp2_prs_entry pe;
  1490. if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
  1491. /* Entry exist - update port only */
  1492. pe.index = MVPP2_PE_DROP_ALL;
  1493. mvpp2_prs_hw_read(priv, &pe);
  1494. } else {
  1495. /* Entry doesn't exist - create new */
  1496. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1497. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1498. pe.index = MVPP2_PE_DROP_ALL;
  1499. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1500. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1501. MVPP2_PRS_RI_DROP_MASK);
  1502. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1503. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1504. /* Update shadow table */
  1505. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1506. /* Mask all ports */
  1507. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1508. }
  1509. /* Update port mask */
  1510. mvpp2_prs_tcam_port_set(&pe, port, add);
  1511. mvpp2_prs_hw_write(priv, &pe);
  1512. }
  1513. /* Set port to promiscuous mode */
  1514. static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
  1515. {
  1516. struct mvpp2_prs_entry pe;
  1517. /* Promiscuous mode - Accept unknown packets */
  1518. if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
  1519. /* Entry exist - update port only */
  1520. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1521. mvpp2_prs_hw_read(priv, &pe);
  1522. } else {
  1523. /* Entry doesn't exist - create new */
  1524. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1525. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1526. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1527. /* Continue - set next lookup */
  1528. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1529. /* Set result info bits */
  1530. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
  1531. MVPP2_PRS_RI_L2_CAST_MASK);
  1532. /* Shift to ethertype */
  1533. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1534. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1535. /* Mask all ports */
  1536. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1537. /* Update shadow table */
  1538. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1539. }
  1540. /* Update port mask */
  1541. mvpp2_prs_tcam_port_set(&pe, port, add);
  1542. mvpp2_prs_hw_write(priv, &pe);
  1543. }
  1544. /* Accept multicast */
  1545. static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
  1546. bool add)
  1547. {
  1548. struct mvpp2_prs_entry pe;
  1549. unsigned char da_mc;
  1550. /* Ethernet multicast address first byte is
  1551. * 0x01 for IPv4 and 0x33 for IPv6
  1552. */
  1553. da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
  1554. if (priv->prs_shadow[index].valid) {
  1555. /* Entry exist - update port only */
  1556. pe.index = index;
  1557. mvpp2_prs_hw_read(priv, &pe);
  1558. } else {
  1559. /* Entry doesn't exist - create new */
  1560. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1561. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1562. pe.index = index;
  1563. /* Continue - set next lookup */
  1564. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1565. /* Set result info bits */
  1566. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
  1567. MVPP2_PRS_RI_L2_CAST_MASK);
  1568. /* Update tcam entry data first byte */
  1569. mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
  1570. /* Shift to ethertype */
  1571. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1572. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1573. /* Mask all ports */
  1574. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1575. /* Update shadow table */
  1576. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1577. }
  1578. /* Update port mask */
  1579. mvpp2_prs_tcam_port_set(&pe, port, add);
  1580. mvpp2_prs_hw_write(priv, &pe);
  1581. }
  1582. /* Parser per-port initialization */
  1583. static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
  1584. int lu_max, int offset)
  1585. {
  1586. u32 val;
  1587. /* Set lookup ID */
  1588. val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
  1589. val &= ~MVPP2_PRS_PORT_LU_MASK(port);
  1590. val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
  1591. mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
  1592. /* Set maximum number of loops for packet received from port */
  1593. val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
  1594. val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
  1595. val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
  1596. mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
  1597. /* Set initial offset for packet header extraction for the first
  1598. * searching loop
  1599. */
  1600. val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
  1601. val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
  1602. val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
  1603. mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
  1604. }
  1605. /* Default flow entries initialization for all ports */
  1606. static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
  1607. {
  1608. struct mvpp2_prs_entry pe;
  1609. int port;
  1610. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  1611. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1612. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1613. pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
  1614. /* Mask all ports */
  1615. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1616. /* Set flow ID*/
  1617. mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
  1618. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1619. /* Update shadow table and hw entry */
  1620. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
  1621. mvpp2_prs_hw_write(priv, &pe);
  1622. }
  1623. }
  1624. /* Set default entry for Marvell Header field */
  1625. static void mvpp2_prs_mh_init(struct mvpp2 *priv)
  1626. {
  1627. struct mvpp2_prs_entry pe;
  1628. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1629. pe.index = MVPP2_PE_MH_DEFAULT;
  1630. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
  1631. mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
  1632. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1633. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1634. /* Unmask all ports */
  1635. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1636. /* Update shadow table and hw entry */
  1637. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
  1638. mvpp2_prs_hw_write(priv, &pe);
  1639. }
  1640. /* Set default entires (place holder) for promiscuous, non-promiscuous and
  1641. * multicast MAC addresses
  1642. */
  1643. static void mvpp2_prs_mac_init(struct mvpp2 *priv)
  1644. {
  1645. struct mvpp2_prs_entry pe;
  1646. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1647. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1648. pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
  1649. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1650. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1651. MVPP2_PRS_RI_DROP_MASK);
  1652. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1653. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1654. /* Unmask all ports */
  1655. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1656. /* Update shadow table and hw entry */
  1657. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1658. mvpp2_prs_hw_write(priv, &pe);
  1659. /* place holders only - no ports */
  1660. mvpp2_prs_mac_drop_all_set(priv, 0, false);
  1661. mvpp2_prs_mac_promisc_set(priv, 0, false);
  1662. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
  1663. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
  1664. }
  1665. /* Match basic ethertypes */
  1666. static int mvpp2_prs_etype_init(struct mvpp2 *priv)
  1667. {
  1668. struct mvpp2_prs_entry pe;
  1669. int tid;
  1670. /* Ethertype: PPPoE */
  1671. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1672. MVPP2_PE_LAST_FREE_TID);
  1673. if (tid < 0)
  1674. return tid;
  1675. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1676. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1677. pe.index = tid;
  1678. mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
  1679. mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
  1680. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1681. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
  1682. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
  1683. MVPP2_PRS_RI_PPPOE_MASK);
  1684. /* Update shadow table and hw entry */
  1685. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1686. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1687. priv->prs_shadow[pe.index].finish = false;
  1688. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
  1689. MVPP2_PRS_RI_PPPOE_MASK);
  1690. mvpp2_prs_hw_write(priv, &pe);
  1691. /* Ethertype: ARP */
  1692. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1693. MVPP2_PE_LAST_FREE_TID);
  1694. if (tid < 0)
  1695. return tid;
  1696. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1697. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1698. pe.index = tid;
  1699. mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
  1700. /* Generate flow in the next iteration*/
  1701. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1702. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1703. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
  1704. MVPP2_PRS_RI_L3_PROTO_MASK);
  1705. /* Set L3 offset */
  1706. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1707. MVPP2_ETH_TYPE_LEN,
  1708. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1709. /* Update shadow table and hw entry */
  1710. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1711. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1712. priv->prs_shadow[pe.index].finish = true;
  1713. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
  1714. MVPP2_PRS_RI_L3_PROTO_MASK);
  1715. mvpp2_prs_hw_write(priv, &pe);
  1716. /* Ethertype: LBTD */
  1717. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1718. MVPP2_PE_LAST_FREE_TID);
  1719. if (tid < 0)
  1720. return tid;
  1721. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1722. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1723. pe.index = tid;
  1724. mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
  1725. /* Generate flow in the next iteration*/
  1726. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1727. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1728. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1729. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1730. MVPP2_PRS_RI_CPU_CODE_MASK |
  1731. MVPP2_PRS_RI_UDF3_MASK);
  1732. /* Set L3 offset */
  1733. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1734. MVPP2_ETH_TYPE_LEN,
  1735. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1736. /* Update shadow table and hw entry */
  1737. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1738. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1739. priv->prs_shadow[pe.index].finish = true;
  1740. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1741. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1742. MVPP2_PRS_RI_CPU_CODE_MASK |
  1743. MVPP2_PRS_RI_UDF3_MASK);
  1744. mvpp2_prs_hw_write(priv, &pe);
  1745. /* Ethertype: IPv4 without options */
  1746. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1747. MVPP2_PE_LAST_FREE_TID);
  1748. if (tid < 0)
  1749. return tid;
  1750. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1751. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1752. pe.index = tid;
  1753. mvpp2_prs_match_etype(&pe, 0, PROT_IP);
  1754. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1755. MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
  1756. MVPP2_PRS_IPV4_HEAD_MASK |
  1757. MVPP2_PRS_IPV4_IHL_MASK);
  1758. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
  1759. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
  1760. MVPP2_PRS_RI_L3_PROTO_MASK);
  1761. /* Skip eth_type + 4 bytes of IP header */
  1762. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
  1763. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1764. /* Set L3 offset */
  1765. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1766. MVPP2_ETH_TYPE_LEN,
  1767. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1768. /* Update shadow table and hw entry */
  1769. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1770. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1771. priv->prs_shadow[pe.index].finish = false;
  1772. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
  1773. MVPP2_PRS_RI_L3_PROTO_MASK);
  1774. mvpp2_prs_hw_write(priv, &pe);
  1775. /* Ethertype: IPv4 with options */
  1776. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1777. MVPP2_PE_LAST_FREE_TID);
  1778. if (tid < 0)
  1779. return tid;
  1780. pe.index = tid;
  1781. /* Clear tcam data before updating */
  1782. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1783. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1784. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1785. MVPP2_PRS_IPV4_HEAD,
  1786. MVPP2_PRS_IPV4_HEAD_MASK);
  1787. /* Clear ri before updating */
  1788. pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
  1789. pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
  1790. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
  1791. MVPP2_PRS_RI_L3_PROTO_MASK);
  1792. /* Update shadow table and hw entry */
  1793. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1794. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1795. priv->prs_shadow[pe.index].finish = false;
  1796. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
  1797. MVPP2_PRS_RI_L3_PROTO_MASK);
  1798. mvpp2_prs_hw_write(priv, &pe);
  1799. /* Ethertype: IPv6 without options */
  1800. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1801. MVPP2_PE_LAST_FREE_TID);
  1802. if (tid < 0)
  1803. return tid;
  1804. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1805. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1806. pe.index = tid;
  1807. mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
  1808. /* Skip DIP of IPV6 header */
  1809. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
  1810. MVPP2_MAX_L3_ADDR_SIZE,
  1811. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1812. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
  1813. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
  1814. MVPP2_PRS_RI_L3_PROTO_MASK);
  1815. /* Set L3 offset */
  1816. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1817. MVPP2_ETH_TYPE_LEN,
  1818. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1819. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1820. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1821. priv->prs_shadow[pe.index].finish = false;
  1822. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
  1823. MVPP2_PRS_RI_L3_PROTO_MASK);
  1824. mvpp2_prs_hw_write(priv, &pe);
  1825. /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
  1826. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1827. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1828. pe.index = MVPP2_PE_ETH_TYPE_UN;
  1829. /* Unmask all ports */
  1830. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1831. /* Generate flow in the next iteration*/
  1832. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1833. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1834. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
  1835. MVPP2_PRS_RI_L3_PROTO_MASK);
  1836. /* Set L3 offset even it's unknown L3 */
  1837. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1838. MVPP2_ETH_TYPE_LEN,
  1839. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1840. /* Update shadow table and hw entry */
  1841. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1842. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1843. priv->prs_shadow[pe.index].finish = true;
  1844. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
  1845. MVPP2_PRS_RI_L3_PROTO_MASK);
  1846. mvpp2_prs_hw_write(priv, &pe);
  1847. return 0;
  1848. }
  1849. /* Parser default initialization */
  1850. static int mvpp2_prs_default_init(struct udevice *dev,
  1851. struct mvpp2 *priv)
  1852. {
  1853. int err, index, i;
  1854. /* Enable tcam table */
  1855. mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
  1856. /* Clear all tcam and sram entries */
  1857. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
  1858. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1859. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1860. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
  1861. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
  1862. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1863. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
  1864. }
  1865. /* Invalidate all tcam entries */
  1866. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
  1867. mvpp2_prs_hw_inv(priv, index);
  1868. priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
  1869. sizeof(struct mvpp2_prs_shadow),
  1870. GFP_KERNEL);
  1871. if (!priv->prs_shadow)
  1872. return -ENOMEM;
  1873. /* Always start from lookup = 0 */
  1874. for (index = 0; index < MVPP2_MAX_PORTS; index++)
  1875. mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
  1876. MVPP2_PRS_PORT_LU_MAX, 0);
  1877. mvpp2_prs_def_flow_init(priv);
  1878. mvpp2_prs_mh_init(priv);
  1879. mvpp2_prs_mac_init(priv);
  1880. err = mvpp2_prs_etype_init(priv);
  1881. if (err)
  1882. return err;
  1883. return 0;
  1884. }
  1885. /* Compare MAC DA with tcam entry data */
  1886. static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
  1887. const u8 *da, unsigned char *mask)
  1888. {
  1889. unsigned char tcam_byte, tcam_mask;
  1890. int index;
  1891. for (index = 0; index < ETH_ALEN; index++) {
  1892. mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
  1893. if (tcam_mask != mask[index])
  1894. return false;
  1895. if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
  1896. return false;
  1897. }
  1898. return true;
  1899. }
  1900. /* Find tcam entry with matched pair <MAC DA, port> */
  1901. static struct mvpp2_prs_entry *
  1902. mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
  1903. unsigned char *mask, int udf_type)
  1904. {
  1905. struct mvpp2_prs_entry *pe;
  1906. int tid;
  1907. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1908. if (!pe)
  1909. return NULL;
  1910. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1911. /* Go through the all entires with MVPP2_PRS_LU_MAC */
  1912. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1913. tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
  1914. unsigned int entry_pmap;
  1915. if (!priv->prs_shadow[tid].valid ||
  1916. (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
  1917. (priv->prs_shadow[tid].udf != udf_type))
  1918. continue;
  1919. pe->index = tid;
  1920. mvpp2_prs_hw_read(priv, pe);
  1921. entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
  1922. if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
  1923. entry_pmap == pmap)
  1924. return pe;
  1925. }
  1926. kfree(pe);
  1927. return NULL;
  1928. }
  1929. /* Update parser's mac da entry */
  1930. static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
  1931. const u8 *da, bool add)
  1932. {
  1933. struct mvpp2_prs_entry *pe;
  1934. unsigned int pmap, len, ri;
  1935. unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  1936. int tid;
  1937. /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
  1938. pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
  1939. MVPP2_PRS_UDF_MAC_DEF);
  1940. /* No such entry */
  1941. if (!pe) {
  1942. if (!add)
  1943. return 0;
  1944. /* Create new TCAM entry */
  1945. /* Find first range mac entry*/
  1946. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1947. tid <= MVPP2_PE_LAST_FREE_TID; tid++)
  1948. if (priv->prs_shadow[tid].valid &&
  1949. (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
  1950. (priv->prs_shadow[tid].udf ==
  1951. MVPP2_PRS_UDF_MAC_RANGE))
  1952. break;
  1953. /* Go through the all entries from first to last */
  1954. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1955. tid - 1);
  1956. if (tid < 0)
  1957. return tid;
  1958. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1959. if (!pe)
  1960. return -1;
  1961. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1962. pe->index = tid;
  1963. /* Mask all ports */
  1964. mvpp2_prs_tcam_port_map_set(pe, 0);
  1965. }
  1966. /* Update port mask */
  1967. mvpp2_prs_tcam_port_set(pe, port, add);
  1968. /* Invalidate the entry if no ports are left enabled */
  1969. pmap = mvpp2_prs_tcam_port_map_get(pe);
  1970. if (pmap == 0) {
  1971. if (add) {
  1972. kfree(pe);
  1973. return -1;
  1974. }
  1975. mvpp2_prs_hw_inv(priv, pe->index);
  1976. priv->prs_shadow[pe->index].valid = false;
  1977. kfree(pe);
  1978. return 0;
  1979. }
  1980. /* Continue - set next lookup */
  1981. mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
  1982. /* Set match on DA */
  1983. len = ETH_ALEN;
  1984. while (len--)
  1985. mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
  1986. /* Set result info bits */
  1987. ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
  1988. mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1989. MVPP2_PRS_RI_MAC_ME_MASK);
  1990. mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1991. MVPP2_PRS_RI_MAC_ME_MASK);
  1992. /* Shift to ethertype */
  1993. mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
  1994. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1995. /* Update shadow table and hw entry */
  1996. priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
  1997. mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
  1998. mvpp2_prs_hw_write(priv, pe);
  1999. kfree(pe);
  2000. return 0;
  2001. }
  2002. static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
  2003. {
  2004. int err;
  2005. /* Remove old parser entry */
  2006. err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
  2007. false);
  2008. if (err)
  2009. return err;
  2010. /* Add new parser entry */
  2011. err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
  2012. if (err)
  2013. return err;
  2014. /* Set addr in the device */
  2015. memcpy(port->dev_addr, da, ETH_ALEN);
  2016. return 0;
  2017. }
  2018. /* Set prs flow for the port */
  2019. static int mvpp2_prs_def_flow(struct mvpp2_port *port)
  2020. {
  2021. struct mvpp2_prs_entry *pe;
  2022. int tid;
  2023. pe = mvpp2_prs_flow_find(port->priv, port->id);
  2024. /* Such entry not exist */
  2025. if (!pe) {
  2026. /* Go through the all entires from last to first */
  2027. tid = mvpp2_prs_tcam_first_free(port->priv,
  2028. MVPP2_PE_LAST_FREE_TID,
  2029. MVPP2_PE_FIRST_FREE_TID);
  2030. if (tid < 0)
  2031. return tid;
  2032. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  2033. if (!pe)
  2034. return -ENOMEM;
  2035. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  2036. pe->index = tid;
  2037. /* Set flow ID*/
  2038. mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
  2039. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  2040. /* Update shadow table */
  2041. mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
  2042. }
  2043. mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
  2044. mvpp2_prs_hw_write(port->priv, pe);
  2045. kfree(pe);
  2046. return 0;
  2047. }
  2048. /* Classifier configuration routines */
  2049. /* Update classification flow table registers */
  2050. static void mvpp2_cls_flow_write(struct mvpp2 *priv,
  2051. struct mvpp2_cls_flow_entry *fe)
  2052. {
  2053. mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
  2054. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
  2055. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
  2056. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
  2057. }
  2058. /* Update classification lookup table register */
  2059. static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
  2060. struct mvpp2_cls_lookup_entry *le)
  2061. {
  2062. u32 val;
  2063. val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
  2064. mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
  2065. mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
  2066. }
  2067. /* Classifier default initialization */
  2068. static void mvpp2_cls_init(struct mvpp2 *priv)
  2069. {
  2070. struct mvpp2_cls_lookup_entry le;
  2071. struct mvpp2_cls_flow_entry fe;
  2072. int index;
  2073. /* Enable classifier */
  2074. mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
  2075. /* Clear classifier flow table */
  2076. memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
  2077. for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
  2078. fe.index = index;
  2079. mvpp2_cls_flow_write(priv, &fe);
  2080. }
  2081. /* Clear classifier lookup table */
  2082. le.data = 0;
  2083. for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
  2084. le.lkpid = index;
  2085. le.way = 0;
  2086. mvpp2_cls_lookup_write(priv, &le);
  2087. le.way = 1;
  2088. mvpp2_cls_lookup_write(priv, &le);
  2089. }
  2090. }
  2091. static void mvpp2_cls_port_config(struct mvpp2_port *port)
  2092. {
  2093. struct mvpp2_cls_lookup_entry le;
  2094. u32 val;
  2095. /* Set way for the port */
  2096. val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
  2097. val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
  2098. mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
  2099. /* Pick the entry to be accessed in lookup ID decoding table
  2100. * according to the way and lkpid.
  2101. */
  2102. le.lkpid = port->id;
  2103. le.way = 0;
  2104. le.data = 0;
  2105. /* Set initial CPU queue for receiving packets */
  2106. le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
  2107. le.data |= port->first_rxq;
  2108. /* Disable classification engines */
  2109. le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
  2110. /* Update lookup ID table entry */
  2111. mvpp2_cls_lookup_write(port->priv, &le);
  2112. }
  2113. /* Set CPU queue number for oversize packets */
  2114. static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
  2115. {
  2116. u32 val;
  2117. mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
  2118. port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
  2119. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
  2120. (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
  2121. val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
  2122. val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
  2123. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
  2124. }
  2125. /* Buffer Manager configuration routines */
  2126. /* Create pool */
  2127. static int mvpp2_bm_pool_create(struct udevice *dev,
  2128. struct mvpp2 *priv,
  2129. struct mvpp2_bm_pool *bm_pool, int size)
  2130. {
  2131. u32 val;
  2132. /* Number of buffer pointers must be a multiple of 16, as per
  2133. * hardware constraints
  2134. */
  2135. if (!IS_ALIGNED(size, 16))
  2136. return -EINVAL;
  2137. bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
  2138. bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
  2139. if (!bm_pool->virt_addr)
  2140. return -ENOMEM;
  2141. if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
  2142. MVPP2_BM_POOL_PTR_ALIGN)) {
  2143. dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
  2144. bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
  2145. return -ENOMEM;
  2146. }
  2147. mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
  2148. lower_32_bits(bm_pool->dma_addr));
  2149. if (priv->hw_version == MVPP22)
  2150. mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
  2151. (upper_32_bits(bm_pool->dma_addr) &
  2152. MVPP22_BM_POOL_BASE_HIGH_MASK));
  2153. mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
  2154. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2155. val |= MVPP2_BM_START_MASK;
  2156. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2157. bm_pool->type = MVPP2_BM_FREE;
  2158. bm_pool->size = size;
  2159. bm_pool->pkt_size = 0;
  2160. bm_pool->buf_num = 0;
  2161. return 0;
  2162. }
  2163. /* Set pool buffer size */
  2164. static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
  2165. struct mvpp2_bm_pool *bm_pool,
  2166. int buf_size)
  2167. {
  2168. u32 val;
  2169. bm_pool->buf_size = buf_size;
  2170. val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
  2171. mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
  2172. }
  2173. /* Free all buffers from the pool */
  2174. static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
  2175. struct mvpp2_bm_pool *bm_pool)
  2176. {
  2177. int i;
  2178. for (i = 0; i < bm_pool->buf_num; i++) {
  2179. /* Allocate buffer back from the buffer manager */
  2180. mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
  2181. }
  2182. bm_pool->buf_num = 0;
  2183. }
  2184. /* Cleanup pool */
  2185. static int mvpp2_bm_pool_destroy(struct udevice *dev,
  2186. struct mvpp2 *priv,
  2187. struct mvpp2_bm_pool *bm_pool)
  2188. {
  2189. u32 val;
  2190. mvpp2_bm_bufs_free(dev, priv, bm_pool);
  2191. if (bm_pool->buf_num) {
  2192. dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
  2193. return 0;
  2194. }
  2195. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2196. val |= MVPP2_BM_STOP_MASK;
  2197. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2198. return 0;
  2199. }
  2200. static int mvpp2_bm_pools_init(struct udevice *dev,
  2201. struct mvpp2 *priv)
  2202. {
  2203. int i, err, size;
  2204. struct mvpp2_bm_pool *bm_pool;
  2205. /* Create all pools with maximum size */
  2206. size = MVPP2_BM_POOL_SIZE_MAX;
  2207. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2208. bm_pool = &priv->bm_pools[i];
  2209. bm_pool->id = i;
  2210. err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
  2211. if (err)
  2212. goto err_unroll_pools;
  2213. mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
  2214. }
  2215. return 0;
  2216. err_unroll_pools:
  2217. dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
  2218. for (i = i - 1; i >= 0; i--)
  2219. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  2220. return err;
  2221. }
  2222. static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
  2223. {
  2224. int i, err;
  2225. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2226. /* Mask BM all interrupts */
  2227. mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
  2228. /* Clear BM cause register */
  2229. mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
  2230. }
  2231. /* Allocate and initialize BM pools */
  2232. priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
  2233. sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
  2234. if (!priv->bm_pools)
  2235. return -ENOMEM;
  2236. err = mvpp2_bm_pools_init(dev, priv);
  2237. if (err < 0)
  2238. return err;
  2239. return 0;
  2240. }
  2241. /* Attach long pool to rxq */
  2242. static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
  2243. int lrxq, int long_pool)
  2244. {
  2245. u32 val, mask;
  2246. int prxq;
  2247. /* Get queue physical ID */
  2248. prxq = port->rxqs[lrxq]->id;
  2249. if (port->priv->hw_version == MVPP21)
  2250. mask = MVPP21_RXQ_POOL_LONG_MASK;
  2251. else
  2252. mask = MVPP22_RXQ_POOL_LONG_MASK;
  2253. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  2254. val &= ~mask;
  2255. val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
  2256. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  2257. }
  2258. /* Set pool number in a BM cookie */
  2259. static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
  2260. {
  2261. u32 bm;
  2262. bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
  2263. bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
  2264. return bm;
  2265. }
  2266. /* Get pool number from a BM cookie */
  2267. static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
  2268. {
  2269. return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
  2270. }
  2271. /* Release buffer to BM */
  2272. static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
  2273. dma_addr_t buf_dma_addr,
  2274. unsigned long buf_phys_addr)
  2275. {
  2276. if (port->priv->hw_version == MVPP22) {
  2277. u32 val = 0;
  2278. if (sizeof(dma_addr_t) == 8)
  2279. val |= upper_32_bits(buf_dma_addr) &
  2280. MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
  2281. if (sizeof(phys_addr_t) == 8)
  2282. val |= (upper_32_bits(buf_phys_addr)
  2283. << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
  2284. MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
  2285. mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
  2286. }
  2287. /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
  2288. * returned in the "cookie" field of the RX
  2289. * descriptor. Instead of storing the virtual address, we
  2290. * store the physical address
  2291. */
  2292. mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
  2293. mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
  2294. }
  2295. /* Refill BM pool */
  2296. static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  2297. dma_addr_t dma_addr,
  2298. phys_addr_t phys_addr)
  2299. {
  2300. int pool = mvpp2_bm_cookie_pool_get(bm);
  2301. mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
  2302. }
  2303. /* Allocate buffers for the pool */
  2304. static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
  2305. struct mvpp2_bm_pool *bm_pool, int buf_num)
  2306. {
  2307. int i;
  2308. if (buf_num < 0 ||
  2309. (buf_num + bm_pool->buf_num > bm_pool->size)) {
  2310. netdev_err(port->dev,
  2311. "cannot allocate %d buffers for pool %d\n",
  2312. buf_num, bm_pool->id);
  2313. return 0;
  2314. }
  2315. for (i = 0; i < buf_num; i++) {
  2316. mvpp2_bm_pool_put(port, bm_pool->id,
  2317. (dma_addr_t)buffer_loc.rx_buffer[i],
  2318. (unsigned long)buffer_loc.rx_buffer[i]);
  2319. }
  2320. /* Update BM driver with number of buffers added to pool */
  2321. bm_pool->buf_num += i;
  2322. return i;
  2323. }
  2324. /* Notify the driver that BM pool is being used as specific type and return the
  2325. * pool pointer on success
  2326. */
  2327. static struct mvpp2_bm_pool *
  2328. mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
  2329. int pkt_size)
  2330. {
  2331. struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
  2332. int num;
  2333. if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
  2334. netdev_err(port->dev, "mixing pool types is forbidden\n");
  2335. return NULL;
  2336. }
  2337. if (new_pool->type == MVPP2_BM_FREE)
  2338. new_pool->type = type;
  2339. /* Allocate buffers in case BM pool is used as long pool, but packet
  2340. * size doesn't match MTU or BM pool hasn't being used yet
  2341. */
  2342. if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
  2343. (new_pool->pkt_size == 0)) {
  2344. int pkts_num;
  2345. /* Set default buffer number or free all the buffers in case
  2346. * the pool is not empty
  2347. */
  2348. pkts_num = new_pool->buf_num;
  2349. if (pkts_num == 0)
  2350. pkts_num = type == MVPP2_BM_SWF_LONG ?
  2351. MVPP2_BM_LONG_BUF_NUM :
  2352. MVPP2_BM_SHORT_BUF_NUM;
  2353. else
  2354. mvpp2_bm_bufs_free(NULL,
  2355. port->priv, new_pool);
  2356. new_pool->pkt_size = pkt_size;
  2357. /* Allocate buffers for this pool */
  2358. num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
  2359. if (num != pkts_num) {
  2360. dev_err(dev, "pool %d: %d of %d allocated\n",
  2361. new_pool->id, num, pkts_num);
  2362. return NULL;
  2363. }
  2364. }
  2365. return new_pool;
  2366. }
  2367. /* Initialize pools for swf */
  2368. static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
  2369. {
  2370. int rxq;
  2371. if (!port->pool_long) {
  2372. port->pool_long =
  2373. mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
  2374. MVPP2_BM_SWF_LONG,
  2375. port->pkt_size);
  2376. if (!port->pool_long)
  2377. return -ENOMEM;
  2378. port->pool_long->port_map |= (1 << port->id);
  2379. for (rxq = 0; rxq < rxq_number; rxq++)
  2380. mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
  2381. }
  2382. return 0;
  2383. }
  2384. /* Port configuration routines */
  2385. static void mvpp2_port_mii_set(struct mvpp2_port *port)
  2386. {
  2387. u32 val;
  2388. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2389. switch (port->phy_interface) {
  2390. case PHY_INTERFACE_MODE_SGMII:
  2391. val |= MVPP2_GMAC_INBAND_AN_MASK;
  2392. break;
  2393. case PHY_INTERFACE_MODE_RGMII:
  2394. case PHY_INTERFACE_MODE_RGMII_ID:
  2395. val |= MVPP2_GMAC_PORT_RGMII_MASK;
  2396. default:
  2397. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2398. }
  2399. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2400. }
  2401. static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
  2402. {
  2403. u32 val;
  2404. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2405. val |= MVPP2_GMAC_FC_ADV_EN;
  2406. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2407. }
  2408. static void mvpp2_port_enable(struct mvpp2_port *port)
  2409. {
  2410. u32 val;
  2411. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2412. val |= MVPP2_GMAC_PORT_EN_MASK;
  2413. val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
  2414. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2415. }
  2416. static void mvpp2_port_disable(struct mvpp2_port *port)
  2417. {
  2418. u32 val;
  2419. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2420. val &= ~(MVPP2_GMAC_PORT_EN_MASK);
  2421. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2422. }
  2423. /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
  2424. static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
  2425. {
  2426. u32 val;
  2427. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
  2428. ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2429. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2430. }
  2431. /* Configure loopback port */
  2432. static void mvpp2_port_loopback_set(struct mvpp2_port *port)
  2433. {
  2434. u32 val;
  2435. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2436. if (port->speed == 1000)
  2437. val |= MVPP2_GMAC_GMII_LB_EN_MASK;
  2438. else
  2439. val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
  2440. if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
  2441. val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  2442. else
  2443. val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
  2444. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2445. }
  2446. static void mvpp2_port_reset(struct mvpp2_port *port)
  2447. {
  2448. u32 val;
  2449. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2450. ~MVPP2_GMAC_PORT_RESET_MASK;
  2451. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2452. while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2453. MVPP2_GMAC_PORT_RESET_MASK)
  2454. continue;
  2455. }
  2456. /* Change maximum receive size of the port */
  2457. static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
  2458. {
  2459. u32 val;
  2460. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2461. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2462. val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
  2463. MVPP2_GMAC_MAX_RX_SIZE_OFFS);
  2464. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2465. }
  2466. /* PPv2.2 GoP/GMAC config */
  2467. /* Set the MAC to reset or exit from reset */
  2468. static int gop_gmac_reset(struct mvpp2_port *port, int reset)
  2469. {
  2470. u32 val;
  2471. /* read - modify - write */
  2472. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2473. if (reset)
  2474. val |= MVPP2_GMAC_PORT_RESET_MASK;
  2475. else
  2476. val &= ~MVPP2_GMAC_PORT_RESET_MASK;
  2477. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2478. return 0;
  2479. }
  2480. /*
  2481. * gop_gpcs_mode_cfg
  2482. *
  2483. * Configure port to working with Gig PCS or don't.
  2484. */
  2485. static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
  2486. {
  2487. u32 val;
  2488. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2489. if (en)
  2490. val |= MVPP2_GMAC_PCS_ENABLE_MASK;
  2491. else
  2492. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2493. /* enable / disable PCS on this port */
  2494. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2495. return 0;
  2496. }
  2497. static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
  2498. {
  2499. u32 val;
  2500. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2501. if (en)
  2502. val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2503. else
  2504. val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2505. /* enable / disable PCS on this port */
  2506. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2507. return 0;
  2508. }
  2509. static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
  2510. {
  2511. u32 val, thresh;
  2512. /*
  2513. * Configure minimal level of the Tx FIFO before the lower part
  2514. * starts to read a packet
  2515. */
  2516. thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  2517. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2518. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2519. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2520. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2521. /* Disable bypass of sync module */
  2522. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2523. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2524. /* configure DP clock select according to mode */
  2525. val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2526. /* configure QSGMII bypass according to mode */
  2527. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2528. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2529. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2530. /*
  2531. * Configure GIG MAC to 1000Base-X mode connected to a fiber
  2532. * transceiver
  2533. */
  2534. val |= MVPP2_GMAC_PORT_TYPE_MASK;
  2535. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2536. /* configure AN 0x9268 */
  2537. val = MVPP2_GMAC_EN_PCS_AN |
  2538. MVPP2_GMAC_AN_BYPASS_EN |
  2539. MVPP2_GMAC_CONFIG_MII_SPEED |
  2540. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2541. MVPP2_GMAC_FC_ADV_EN |
  2542. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2543. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2544. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2545. }
  2546. static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
  2547. {
  2548. u32 val, thresh;
  2549. /*
  2550. * Configure minimal level of the Tx FIFO before the lower part
  2551. * starts to read a packet
  2552. */
  2553. thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
  2554. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2555. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2556. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2557. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2558. /* Disable bypass of sync module */
  2559. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2560. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2561. /* configure DP clock select according to mode */
  2562. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2563. /* configure QSGMII bypass according to mode */
  2564. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2565. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2566. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2567. /* configure GIG MAC to SGMII mode */
  2568. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2569. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2570. /* configure AN */
  2571. val = MVPP2_GMAC_EN_PCS_AN |
  2572. MVPP2_GMAC_AN_BYPASS_EN |
  2573. MVPP2_GMAC_AN_SPEED_EN |
  2574. MVPP2_GMAC_EN_FC_AN |
  2575. MVPP2_GMAC_AN_DUPLEX_EN |
  2576. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2577. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2578. }
  2579. static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
  2580. {
  2581. u32 val, thresh;
  2582. /*
  2583. * Configure minimal level of the Tx FIFO before the lower part
  2584. * starts to read a packet
  2585. */
  2586. thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
  2587. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2588. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2589. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2590. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2591. /* Disable bypass of sync module */
  2592. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2593. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2594. /* configure DP clock select according to mode */
  2595. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2596. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2597. val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
  2598. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2599. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2600. /* configure GIG MAC to SGMII mode */
  2601. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2602. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2603. /* configure AN 0xb8e8 */
  2604. val = MVPP2_GMAC_AN_BYPASS_EN |
  2605. MVPP2_GMAC_AN_SPEED_EN |
  2606. MVPP2_GMAC_EN_FC_AN |
  2607. MVPP2_GMAC_AN_DUPLEX_EN |
  2608. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2609. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2610. }
  2611. /* Set the internal mux's to the required MAC in the GOP */
  2612. static int gop_gmac_mode_cfg(struct mvpp2_port *port)
  2613. {
  2614. u32 val;
  2615. /* Set TX FIFO thresholds */
  2616. switch (port->phy_interface) {
  2617. case PHY_INTERFACE_MODE_SGMII:
  2618. if (port->phy_speed == 2500)
  2619. gop_gmac_sgmii2_5_cfg(port);
  2620. else
  2621. gop_gmac_sgmii_cfg(port);
  2622. break;
  2623. case PHY_INTERFACE_MODE_RGMII:
  2624. case PHY_INTERFACE_MODE_RGMII_ID:
  2625. gop_gmac_rgmii_cfg(port);
  2626. break;
  2627. default:
  2628. return -1;
  2629. }
  2630. /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
  2631. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2632. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2633. val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
  2634. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2635. /* PeriodicXonEn disable */
  2636. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2637. val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2638. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2639. return 0;
  2640. }
  2641. static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
  2642. {
  2643. u32 val;
  2644. /* relevant only for MAC0 (XLG0 and GMAC0) */
  2645. if (port->gop_id > 0)
  2646. return;
  2647. /* configure 1Gig MAC mode */
  2648. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2649. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2650. val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
  2651. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2652. }
  2653. static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
  2654. {
  2655. u32 val;
  2656. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2657. if (reset)
  2658. val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
  2659. else
  2660. val |= MVPP2_GMAC_SGMII_MODE_MASK;
  2661. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2662. return 0;
  2663. }
  2664. /* Set the internal mux's to the required PCS in the PI */
  2665. static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
  2666. {
  2667. u32 val;
  2668. int lane;
  2669. switch (num_of_lanes) {
  2670. case 1:
  2671. lane = 0;
  2672. break;
  2673. case 2:
  2674. lane = 1;
  2675. break;
  2676. case 4:
  2677. lane = 2;
  2678. break;
  2679. default:
  2680. return -1;
  2681. }
  2682. /* configure XG MAC mode */
  2683. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2684. val &= ~MVPP22_XPCS_PCSMODE_MASK;
  2685. val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
  2686. val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
  2687. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2688. return 0;
  2689. }
  2690. static int gop_mpcs_mode(struct mvpp2_port *port)
  2691. {
  2692. u32 val;
  2693. /* configure PCS40G COMMON CONTROL */
  2694. val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2695. val &= ~FORWARD_ERROR_CORRECTION_MASK;
  2696. writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2697. /* configure PCS CLOCK RESET */
  2698. val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
  2699. val &= ~CLK_DIVISION_RATIO_MASK;
  2700. val |= 1 << CLK_DIVISION_RATIO_OFFS;
  2701. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2702. val &= ~CLK_DIV_PHASE_SET_MASK;
  2703. val |= MAC_CLK_RESET_MASK;
  2704. val |= RX_SD_CLK_RESET_MASK;
  2705. val |= TX_SD_CLK_RESET_MASK;
  2706. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2707. return 0;
  2708. }
  2709. /* Set the internal mux's to the required MAC in the GOP */
  2710. static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
  2711. {
  2712. u32 val;
  2713. /* configure 10G MAC mode */
  2714. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2715. val |= MVPP22_XLG_RX_FC_EN;
  2716. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2717. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2718. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2719. val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
  2720. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2721. /* read - modify - write */
  2722. val = readl(port->base + MVPP22_XLG_CTRL4_REG);
  2723. val &= ~MVPP22_XLG_MODE_DMA_1G;
  2724. val |= MVPP22_XLG_FORWARD_PFC_EN;
  2725. val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
  2726. val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
  2727. writel(val, port->base + MVPP22_XLG_CTRL4_REG);
  2728. /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
  2729. val = readl(port->base + MVPP22_XLG_CTRL1_REG);
  2730. val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
  2731. val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
  2732. writel(val, port->base + MVPP22_XLG_CTRL1_REG);
  2733. /* unmask link change interrupt */
  2734. val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2735. val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
  2736. val |= 1; /* unmask summary bit */
  2737. writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2738. return 0;
  2739. }
  2740. /* Set PCS to reset or exit from reset */
  2741. static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
  2742. {
  2743. u32 val;
  2744. /* read - modify - write */
  2745. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2746. if (reset)
  2747. val &= ~MVPP22_XPCS_PCSRESET;
  2748. else
  2749. val |= MVPP22_XPCS_PCSRESET;
  2750. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2751. return 0;
  2752. }
  2753. /* Set the MAC to reset or exit from reset */
  2754. static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
  2755. {
  2756. u32 val;
  2757. /* read - modify - write */
  2758. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2759. if (reset)
  2760. val &= ~MVPP22_XLG_MAC_RESETN;
  2761. else
  2762. val |= MVPP22_XLG_MAC_RESETN;
  2763. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2764. return 0;
  2765. }
  2766. /*
  2767. * gop_port_init
  2768. *
  2769. * Init physical port. Configures the port mode and all it's elements
  2770. * accordingly.
  2771. * Does not verify that the selected mode/port number is valid at the
  2772. * core level.
  2773. */
  2774. static int gop_port_init(struct mvpp2_port *port)
  2775. {
  2776. int mac_num = port->gop_id;
  2777. int num_of_act_lanes;
  2778. if (mac_num >= MVPP22_GOP_MAC_NUM) {
  2779. netdev_err(NULL, "%s: illegal port number %d", __func__,
  2780. mac_num);
  2781. return -1;
  2782. }
  2783. switch (port->phy_interface) {
  2784. case PHY_INTERFACE_MODE_RGMII:
  2785. case PHY_INTERFACE_MODE_RGMII_ID:
  2786. gop_gmac_reset(port, 1);
  2787. /* configure PCS */
  2788. gop_gpcs_mode_cfg(port, 0);
  2789. gop_bypass_clk_cfg(port, 1);
  2790. /* configure MAC */
  2791. gop_gmac_mode_cfg(port);
  2792. /* pcs unreset */
  2793. gop_gpcs_reset(port, 0);
  2794. /* mac unreset */
  2795. gop_gmac_reset(port, 0);
  2796. break;
  2797. case PHY_INTERFACE_MODE_SGMII:
  2798. /* configure PCS */
  2799. gop_gpcs_mode_cfg(port, 1);
  2800. /* configure MAC */
  2801. gop_gmac_mode_cfg(port);
  2802. /* select proper Mac mode */
  2803. gop_xlg_2_gig_mac_cfg(port);
  2804. /* pcs unreset */
  2805. gop_gpcs_reset(port, 0);
  2806. /* mac unreset */
  2807. gop_gmac_reset(port, 0);
  2808. break;
  2809. case PHY_INTERFACE_MODE_SFI:
  2810. num_of_act_lanes = 2;
  2811. mac_num = 0;
  2812. /* configure PCS */
  2813. gop_xpcs_mode(port, num_of_act_lanes);
  2814. gop_mpcs_mode(port);
  2815. /* configure MAC */
  2816. gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
  2817. /* pcs unreset */
  2818. gop_xpcs_reset(port, 0);
  2819. /* mac unreset */
  2820. gop_xlg_mac_reset(port, 0);
  2821. break;
  2822. default:
  2823. netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
  2824. __func__, port->phy_interface);
  2825. return -1;
  2826. }
  2827. return 0;
  2828. }
  2829. static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
  2830. {
  2831. u32 val;
  2832. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2833. if (enable) {
  2834. /* Enable port and MIB counters update */
  2835. val |= MVPP22_XLG_PORT_EN;
  2836. val &= ~MVPP22_XLG_MIBCNT_DIS;
  2837. } else {
  2838. /* Disable port */
  2839. val &= ~MVPP22_XLG_PORT_EN;
  2840. }
  2841. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2842. }
  2843. static void gop_port_enable(struct mvpp2_port *port, int enable)
  2844. {
  2845. switch (port->phy_interface) {
  2846. case PHY_INTERFACE_MODE_RGMII:
  2847. case PHY_INTERFACE_MODE_RGMII_ID:
  2848. case PHY_INTERFACE_MODE_SGMII:
  2849. if (enable)
  2850. mvpp2_port_enable(port);
  2851. else
  2852. mvpp2_port_disable(port);
  2853. break;
  2854. case PHY_INTERFACE_MODE_SFI:
  2855. gop_xlg_mac_port_enable(port, enable);
  2856. break;
  2857. default:
  2858. netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
  2859. port->phy_interface);
  2860. return;
  2861. }
  2862. }
  2863. /* RFU1 functions */
  2864. static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
  2865. {
  2866. return readl(priv->rfu1_base + offset);
  2867. }
  2868. static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
  2869. {
  2870. writel(data, priv->rfu1_base + offset);
  2871. }
  2872. static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
  2873. {
  2874. u32 val = 0;
  2875. if (gop_id == 2) {
  2876. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2877. val |= MV_NETC_GE_MAC2_SGMII;
  2878. }
  2879. if (gop_id == 3) {
  2880. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2881. val |= MV_NETC_GE_MAC3_SGMII;
  2882. else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
  2883. phy_type == PHY_INTERFACE_MODE_RGMII_ID)
  2884. val |= MV_NETC_GE_MAC3_RGMII;
  2885. }
  2886. return val;
  2887. }
  2888. static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
  2889. {
  2890. u32 reg;
  2891. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2892. reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
  2893. val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
  2894. val &= NETC_PORTS_ACTIVE_MASK(gop_id);
  2895. reg |= val;
  2896. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2897. }
  2898. static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
  2899. {
  2900. u32 reg;
  2901. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2902. reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
  2903. val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
  2904. val &= NETC_GBE_PORT1_MII_MODE_MASK;
  2905. reg |= val;
  2906. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2907. }
  2908. static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
  2909. {
  2910. u32 reg;
  2911. reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
  2912. reg &= ~NETC_GOP_SOFT_RESET_MASK;
  2913. val <<= NETC_GOP_SOFT_RESET_OFFS;
  2914. val &= NETC_GOP_SOFT_RESET_MASK;
  2915. reg |= val;
  2916. gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
  2917. }
  2918. static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
  2919. {
  2920. u32 reg;
  2921. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2922. reg &= ~NETC_CLK_DIV_PHASE_MASK;
  2923. val <<= NETC_CLK_DIV_PHASE_OFFS;
  2924. val &= NETC_CLK_DIV_PHASE_MASK;
  2925. reg |= val;
  2926. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2927. }
  2928. static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
  2929. {
  2930. u32 reg;
  2931. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2932. reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
  2933. val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
  2934. val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
  2935. reg |= val;
  2936. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2937. }
  2938. static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
  2939. u32 val)
  2940. {
  2941. u32 reg, mask, offset;
  2942. if (gop_id == 2) {
  2943. mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
  2944. offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
  2945. } else {
  2946. mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
  2947. offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
  2948. }
  2949. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2950. reg &= ~mask;
  2951. val <<= offset;
  2952. val &= mask;
  2953. reg |= val;
  2954. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2955. }
  2956. static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
  2957. {
  2958. u32 reg;
  2959. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2960. reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
  2961. val <<= NETC_BUS_WIDTH_SELECT_OFFS;
  2962. val &= NETC_BUS_WIDTH_SELECT_MASK;
  2963. reg |= val;
  2964. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2965. }
  2966. static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
  2967. {
  2968. u32 reg;
  2969. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2970. reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
  2971. val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
  2972. val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
  2973. reg |= val;
  2974. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2975. }
  2976. static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
  2977. enum mv_netc_phase phase)
  2978. {
  2979. switch (phase) {
  2980. case MV_NETC_FIRST_PHASE:
  2981. /* Set Bus Width to HB mode = 1 */
  2982. gop_netc_bus_width_select(priv, 1);
  2983. /* Select RGMII mode */
  2984. gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
  2985. break;
  2986. case MV_NETC_SECOND_PHASE:
  2987. /* De-assert the relevant port HB reset */
  2988. gop_netc_port_rf_reset(priv, gop_id, 1);
  2989. break;
  2990. }
  2991. }
  2992. static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
  2993. enum mv_netc_phase phase)
  2994. {
  2995. switch (phase) {
  2996. case MV_NETC_FIRST_PHASE:
  2997. /* Set Bus Width to HB mode = 1 */
  2998. gop_netc_bus_width_select(priv, 1);
  2999. /* Select SGMII mode */
  3000. if (gop_id >= 1) {
  3001. gop_netc_gbe_sgmii_mode_select(priv, gop_id,
  3002. MV_NETC_GBE_SGMII);
  3003. }
  3004. /* Configure the sample stages */
  3005. gop_netc_sample_stages_timing(priv, 0);
  3006. /* Configure the ComPhy Selector */
  3007. /* gop_netc_com_phy_selector_config(netComplex); */
  3008. break;
  3009. case MV_NETC_SECOND_PHASE:
  3010. /* De-assert the relevant port HB reset */
  3011. gop_netc_port_rf_reset(priv, gop_id, 1);
  3012. break;
  3013. }
  3014. }
  3015. static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
  3016. {
  3017. u32 c = priv->netc_config;
  3018. if (c & MV_NETC_GE_MAC2_SGMII)
  3019. gop_netc_mac_to_sgmii(priv, 2, phase);
  3020. else
  3021. gop_netc_mac_to_xgmii(priv, 2, phase);
  3022. if (c & MV_NETC_GE_MAC3_SGMII) {
  3023. gop_netc_mac_to_sgmii(priv, 3, phase);
  3024. } else {
  3025. gop_netc_mac_to_xgmii(priv, 3, phase);
  3026. if (c & MV_NETC_GE_MAC3_RGMII)
  3027. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
  3028. else
  3029. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
  3030. }
  3031. /* Activate gop ports 0, 2, 3 */
  3032. gop_netc_active_port(priv, 0, 1);
  3033. gop_netc_active_port(priv, 2, 1);
  3034. gop_netc_active_port(priv, 3, 1);
  3035. if (phase == MV_NETC_SECOND_PHASE) {
  3036. /* Enable the GOP internal clock logic */
  3037. gop_netc_gop_clock_logic_set(priv, 1);
  3038. /* De-assert GOP unit reset */
  3039. gop_netc_gop_reset(priv, 1);
  3040. }
  3041. return 0;
  3042. }
  3043. /* Set defaults to the MVPP2 port */
  3044. static void mvpp2_defaults_set(struct mvpp2_port *port)
  3045. {
  3046. int tx_port_num, val, queue, ptxq, lrxq;
  3047. if (port->priv->hw_version == MVPP21) {
  3048. /* Configure port to loopback if needed */
  3049. if (port->flags & MVPP2_F_LOOPBACK)
  3050. mvpp2_port_loopback_set(port);
  3051. /* Update TX FIFO MIN Threshold */
  3052. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3053. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  3054. /* Min. TX threshold must be less than minimal packet length */
  3055. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
  3056. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3057. }
  3058. /* Disable Legacy WRR, Disable EJP, Release from reset */
  3059. tx_port_num = mvpp2_egress_port(port);
  3060. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
  3061. tx_port_num);
  3062. mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
  3063. /* Close bandwidth for all queues */
  3064. for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
  3065. ptxq = mvpp2_txq_phys(port->id, queue);
  3066. mvpp2_write(port->priv,
  3067. MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
  3068. }
  3069. /* Set refill period to 1 usec, refill tokens
  3070. * and bucket size to maximum
  3071. */
  3072. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
  3073. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
  3074. val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
  3075. val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
  3076. val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
  3077. mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
  3078. val = MVPP2_TXP_TOKEN_SIZE_MAX;
  3079. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3080. /* Set MaximumLowLatencyPacketSize value to 256 */
  3081. mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
  3082. MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
  3083. MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
  3084. /* Enable Rx cache snoop */
  3085. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3086. queue = port->rxqs[lrxq]->id;
  3087. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3088. val |= MVPP2_SNOOP_PKT_SIZE_MASK |
  3089. MVPP2_SNOOP_BUF_HDR_MASK;
  3090. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3091. }
  3092. }
  3093. /* Enable/disable receiving packets */
  3094. static void mvpp2_ingress_enable(struct mvpp2_port *port)
  3095. {
  3096. u32 val;
  3097. int lrxq, queue;
  3098. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3099. queue = port->rxqs[lrxq]->id;
  3100. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3101. val &= ~MVPP2_RXQ_DISABLE_MASK;
  3102. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3103. }
  3104. }
  3105. static void mvpp2_ingress_disable(struct mvpp2_port *port)
  3106. {
  3107. u32 val;
  3108. int lrxq, queue;
  3109. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3110. queue = port->rxqs[lrxq]->id;
  3111. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3112. val |= MVPP2_RXQ_DISABLE_MASK;
  3113. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3114. }
  3115. }
  3116. /* Enable transmit via physical egress queue
  3117. * - HW starts take descriptors from DRAM
  3118. */
  3119. static void mvpp2_egress_enable(struct mvpp2_port *port)
  3120. {
  3121. u32 qmap;
  3122. int queue;
  3123. int tx_port_num = mvpp2_egress_port(port);
  3124. /* Enable all initialized TXs. */
  3125. qmap = 0;
  3126. for (queue = 0; queue < txq_number; queue++) {
  3127. struct mvpp2_tx_queue *txq = port->txqs[queue];
  3128. if (txq->descs != NULL)
  3129. qmap |= (1 << queue);
  3130. }
  3131. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3132. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
  3133. }
  3134. /* Disable transmit via physical egress queue
  3135. * - HW doesn't take descriptors from DRAM
  3136. */
  3137. static void mvpp2_egress_disable(struct mvpp2_port *port)
  3138. {
  3139. u32 reg_data;
  3140. int delay;
  3141. int tx_port_num = mvpp2_egress_port(port);
  3142. /* Issue stop command for active channels only */
  3143. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3144. reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
  3145. MVPP2_TXP_SCHED_ENQ_MASK;
  3146. if (reg_data != 0)
  3147. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
  3148. (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
  3149. /* Wait for all Tx activity to terminate. */
  3150. delay = 0;
  3151. do {
  3152. if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
  3153. netdev_warn(port->dev,
  3154. "Tx stop timed out, status=0x%08x\n",
  3155. reg_data);
  3156. break;
  3157. }
  3158. mdelay(1);
  3159. delay++;
  3160. /* Check port TX Command register that all
  3161. * Tx queues are stopped
  3162. */
  3163. reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
  3164. } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
  3165. }
  3166. /* Rx descriptors helper methods */
  3167. /* Get number of Rx descriptors occupied by received packets */
  3168. static inline int
  3169. mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
  3170. {
  3171. u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
  3172. return val & MVPP2_RXQ_OCCUPIED_MASK;
  3173. }
  3174. /* Update Rx queue status with the number of occupied and available
  3175. * Rx descriptor slots.
  3176. */
  3177. static inline void
  3178. mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
  3179. int used_count, int free_count)
  3180. {
  3181. /* Decrement the number of used descriptors and increment count
  3182. * increment the number of free descriptors.
  3183. */
  3184. u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
  3185. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
  3186. }
  3187. /* Get pointer to next RX descriptor to be processed by SW */
  3188. static inline struct mvpp2_rx_desc *
  3189. mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
  3190. {
  3191. int rx_desc = rxq->next_desc_to_proc;
  3192. rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
  3193. prefetch(rxq->descs + rxq->next_desc_to_proc);
  3194. return rxq->descs + rx_desc;
  3195. }
  3196. /* Set rx queue offset */
  3197. static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
  3198. int prxq, int offset)
  3199. {
  3200. u32 val;
  3201. /* Convert offset from bytes to units of 32 bytes */
  3202. offset = offset >> 5;
  3203. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  3204. val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
  3205. /* Offset is in */
  3206. val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
  3207. MVPP2_RXQ_PACKET_OFFSET_MASK);
  3208. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  3209. }
  3210. /* Obtain BM cookie information from descriptor */
  3211. static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
  3212. struct mvpp2_rx_desc *rx_desc)
  3213. {
  3214. int cpu = smp_processor_id();
  3215. int pool;
  3216. pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
  3217. MVPP2_RXD_BM_POOL_ID_MASK) >>
  3218. MVPP2_RXD_BM_POOL_ID_OFFS;
  3219. return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
  3220. ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
  3221. }
  3222. /* Tx descriptors helper methods */
  3223. /* Get number of Tx descriptors waiting to be transmitted by HW */
  3224. static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
  3225. struct mvpp2_tx_queue *txq)
  3226. {
  3227. u32 val;
  3228. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3229. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3230. return val & MVPP2_TXQ_PENDING_MASK;
  3231. }
  3232. /* Get pointer to next Tx descriptor to be processed (send) by HW */
  3233. static struct mvpp2_tx_desc *
  3234. mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
  3235. {
  3236. int tx_desc = txq->next_desc_to_proc;
  3237. txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
  3238. return txq->descs + tx_desc;
  3239. }
  3240. /* Update HW with number of aggregated Tx descriptors to be sent */
  3241. static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
  3242. {
  3243. /* aggregated access - relevant TXQ number is written in TX desc */
  3244. mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
  3245. }
  3246. /* Get number of sent descriptors and decrement counter.
  3247. * The number of sent descriptors is returned.
  3248. * Per-CPU access
  3249. */
  3250. static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
  3251. struct mvpp2_tx_queue *txq)
  3252. {
  3253. u32 val;
  3254. /* Reading status reg resets transmitted descriptor counter */
  3255. val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
  3256. return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
  3257. MVPP2_TRANSMITTED_COUNT_OFFSET;
  3258. }
  3259. static void mvpp2_txq_sent_counter_clear(void *arg)
  3260. {
  3261. struct mvpp2_port *port = arg;
  3262. int queue;
  3263. for (queue = 0; queue < txq_number; queue++) {
  3264. int id = port->txqs[queue]->id;
  3265. mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
  3266. }
  3267. }
  3268. /* Set max sizes for Tx queues */
  3269. static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
  3270. {
  3271. u32 val, size, mtu;
  3272. int txq, tx_port_num;
  3273. mtu = port->pkt_size * 8;
  3274. if (mtu > MVPP2_TXP_MTU_MAX)
  3275. mtu = MVPP2_TXP_MTU_MAX;
  3276. /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
  3277. mtu = 3 * mtu;
  3278. /* Indirect access to registers */
  3279. tx_port_num = mvpp2_egress_port(port);
  3280. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3281. /* Set MTU */
  3282. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
  3283. val &= ~MVPP2_TXP_MTU_MAX;
  3284. val |= mtu;
  3285. mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
  3286. /* TXP token size and all TXQs token size must be larger that MTU */
  3287. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
  3288. size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
  3289. if (size < mtu) {
  3290. size = mtu;
  3291. val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
  3292. val |= size;
  3293. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3294. }
  3295. for (txq = 0; txq < txq_number; txq++) {
  3296. val = mvpp2_read(port->priv,
  3297. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
  3298. size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
  3299. if (size < mtu) {
  3300. size = mtu;
  3301. val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
  3302. val |= size;
  3303. mvpp2_write(port->priv,
  3304. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
  3305. val);
  3306. }
  3307. }
  3308. }
  3309. /* Free Tx queue skbuffs */
  3310. static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
  3311. struct mvpp2_tx_queue *txq,
  3312. struct mvpp2_txq_pcpu *txq_pcpu, int num)
  3313. {
  3314. int i;
  3315. for (i = 0; i < num; i++)
  3316. mvpp2_txq_inc_get(txq_pcpu);
  3317. }
  3318. static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
  3319. u32 cause)
  3320. {
  3321. int queue = fls(cause) - 1;
  3322. return port->rxqs[queue];
  3323. }
  3324. static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
  3325. u32 cause)
  3326. {
  3327. int queue = fls(cause) - 1;
  3328. return port->txqs[queue];
  3329. }
  3330. /* Rx/Tx queue initialization/cleanup methods */
  3331. /* Allocate and initialize descriptors for aggr TXQ */
  3332. static int mvpp2_aggr_txq_init(struct udevice *dev,
  3333. struct mvpp2_tx_queue *aggr_txq,
  3334. int desc_num, int cpu,
  3335. struct mvpp2 *priv)
  3336. {
  3337. u32 txq_dma;
  3338. /* Allocate memory for TX descriptors */
  3339. aggr_txq->descs = buffer_loc.aggr_tx_descs;
  3340. aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
  3341. if (!aggr_txq->descs)
  3342. return -ENOMEM;
  3343. /* Make sure descriptor address is cache line size aligned */
  3344. BUG_ON(aggr_txq->descs !=
  3345. PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3346. aggr_txq->last_desc = aggr_txq->size - 1;
  3347. /* Aggr TXQ no reset WA */
  3348. aggr_txq->next_desc_to_proc = mvpp2_read(priv,
  3349. MVPP2_AGGR_TXQ_INDEX_REG(cpu));
  3350. /* Set Tx descriptors queue starting address indirect
  3351. * access
  3352. */
  3353. if (priv->hw_version == MVPP21)
  3354. txq_dma = aggr_txq->descs_dma;
  3355. else
  3356. txq_dma = aggr_txq->descs_dma >>
  3357. MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
  3358. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
  3359. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
  3360. return 0;
  3361. }
  3362. /* Create a specified Rx queue */
  3363. static int mvpp2_rxq_init(struct mvpp2_port *port,
  3364. struct mvpp2_rx_queue *rxq)
  3365. {
  3366. u32 rxq_dma;
  3367. rxq->size = port->rx_ring_size;
  3368. /* Allocate memory for RX descriptors */
  3369. rxq->descs = buffer_loc.rx_descs;
  3370. rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
  3371. if (!rxq->descs)
  3372. return -ENOMEM;
  3373. BUG_ON(rxq->descs !=
  3374. PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3375. rxq->last_desc = rxq->size - 1;
  3376. /* Zero occupied and non-occupied counters - direct access */
  3377. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3378. /* Set Rx descriptors queue starting address - indirect access */
  3379. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3380. if (port->priv->hw_version == MVPP21)
  3381. rxq_dma = rxq->descs_dma;
  3382. else
  3383. rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
  3384. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
  3385. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
  3386. mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
  3387. /* Set Offset */
  3388. mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
  3389. /* Add number of descriptors ready for receiving packets */
  3390. mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
  3391. return 0;
  3392. }
  3393. /* Push packets received by the RXQ to BM pool */
  3394. static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
  3395. struct mvpp2_rx_queue *rxq)
  3396. {
  3397. int rx_received, i;
  3398. rx_received = mvpp2_rxq_received(port, rxq->id);
  3399. if (!rx_received)
  3400. return;
  3401. for (i = 0; i < rx_received; i++) {
  3402. struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
  3403. u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
  3404. mvpp2_pool_refill(port, bm,
  3405. mvpp2_rxdesc_dma_addr_get(port, rx_desc),
  3406. mvpp2_rxdesc_cookie_get(port, rx_desc));
  3407. }
  3408. mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
  3409. }
  3410. /* Cleanup Rx queue */
  3411. static void mvpp2_rxq_deinit(struct mvpp2_port *port,
  3412. struct mvpp2_rx_queue *rxq)
  3413. {
  3414. mvpp2_rxq_drop_pkts(port, rxq);
  3415. rxq->descs = NULL;
  3416. rxq->last_desc = 0;
  3417. rxq->next_desc_to_proc = 0;
  3418. rxq->descs_dma = 0;
  3419. /* Clear Rx descriptors queue starting address and size;
  3420. * free descriptor number
  3421. */
  3422. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3423. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3424. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
  3425. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
  3426. }
  3427. /* Create and initialize a Tx queue */
  3428. static int mvpp2_txq_init(struct mvpp2_port *port,
  3429. struct mvpp2_tx_queue *txq)
  3430. {
  3431. u32 val;
  3432. int cpu, desc, desc_per_txq, tx_port_num;
  3433. struct mvpp2_txq_pcpu *txq_pcpu;
  3434. txq->size = port->tx_ring_size;
  3435. /* Allocate memory for Tx descriptors */
  3436. txq->descs = buffer_loc.tx_descs;
  3437. txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
  3438. if (!txq->descs)
  3439. return -ENOMEM;
  3440. /* Make sure descriptor address is cache line size aligned */
  3441. BUG_ON(txq->descs !=
  3442. PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3443. txq->last_desc = txq->size - 1;
  3444. /* Set Tx descriptors queue starting address - indirect access */
  3445. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3446. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
  3447. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
  3448. MVPP2_TXQ_DESC_SIZE_MASK);
  3449. mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
  3450. mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
  3451. txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
  3452. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3453. val &= ~MVPP2_TXQ_PENDING_MASK;
  3454. mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
  3455. /* Calculate base address in prefetch buffer. We reserve 16 descriptors
  3456. * for each existing TXQ.
  3457. * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
  3458. * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
  3459. */
  3460. desc_per_txq = 16;
  3461. desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
  3462. (txq->log_id * desc_per_txq);
  3463. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
  3464. MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
  3465. MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
  3466. /* WRR / EJP configuration - indirect access */
  3467. tx_port_num = mvpp2_egress_port(port);
  3468. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3469. val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
  3470. val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
  3471. val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
  3472. val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
  3473. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
  3474. val = MVPP2_TXQ_TOKEN_SIZE_MAX;
  3475. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
  3476. val);
  3477. for_each_present_cpu(cpu) {
  3478. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3479. txq_pcpu->size = txq->size;
  3480. }
  3481. return 0;
  3482. }
  3483. /* Free allocated TXQ resources */
  3484. static void mvpp2_txq_deinit(struct mvpp2_port *port,
  3485. struct mvpp2_tx_queue *txq)
  3486. {
  3487. txq->descs = NULL;
  3488. txq->last_desc = 0;
  3489. txq->next_desc_to_proc = 0;
  3490. txq->descs_dma = 0;
  3491. /* Set minimum bandwidth for disabled TXQs */
  3492. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
  3493. /* Set Tx descriptors queue starting address and size */
  3494. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3495. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
  3496. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
  3497. }
  3498. /* Cleanup Tx ports */
  3499. static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
  3500. {
  3501. struct mvpp2_txq_pcpu *txq_pcpu;
  3502. int delay, pending, cpu;
  3503. u32 val;
  3504. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3505. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  3506. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  3507. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3508. /* The napi queue has been stopped so wait for all packets
  3509. * to be transmitted.
  3510. */
  3511. delay = 0;
  3512. do {
  3513. if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
  3514. netdev_warn(port->dev,
  3515. "port %d: cleaning queue %d timed out\n",
  3516. port->id, txq->log_id);
  3517. break;
  3518. }
  3519. mdelay(1);
  3520. delay++;
  3521. pending = mvpp2_txq_pend_desc_num_get(port, txq);
  3522. } while (pending);
  3523. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  3524. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3525. for_each_present_cpu(cpu) {
  3526. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3527. /* Release all packets */
  3528. mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
  3529. /* Reset queue */
  3530. txq_pcpu->count = 0;
  3531. txq_pcpu->txq_put_index = 0;
  3532. txq_pcpu->txq_get_index = 0;
  3533. }
  3534. }
  3535. /* Cleanup all Tx queues */
  3536. static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
  3537. {
  3538. struct mvpp2_tx_queue *txq;
  3539. int queue;
  3540. u32 val;
  3541. val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
  3542. /* Reset Tx ports and delete Tx queues */
  3543. val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3544. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3545. for (queue = 0; queue < txq_number; queue++) {
  3546. txq = port->txqs[queue];
  3547. mvpp2_txq_clean(port, txq);
  3548. mvpp2_txq_deinit(port, txq);
  3549. }
  3550. mvpp2_txq_sent_counter_clear(port);
  3551. val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3552. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3553. }
  3554. /* Cleanup all Rx queues */
  3555. static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
  3556. {
  3557. int queue;
  3558. for (queue = 0; queue < rxq_number; queue++)
  3559. mvpp2_rxq_deinit(port, port->rxqs[queue]);
  3560. }
  3561. /* Init all Rx queues for port */
  3562. static int mvpp2_setup_rxqs(struct mvpp2_port *port)
  3563. {
  3564. int queue, err;
  3565. for (queue = 0; queue < rxq_number; queue++) {
  3566. err = mvpp2_rxq_init(port, port->rxqs[queue]);
  3567. if (err)
  3568. goto err_cleanup;
  3569. }
  3570. return 0;
  3571. err_cleanup:
  3572. mvpp2_cleanup_rxqs(port);
  3573. return err;
  3574. }
  3575. /* Init all tx queues for port */
  3576. static int mvpp2_setup_txqs(struct mvpp2_port *port)
  3577. {
  3578. struct mvpp2_tx_queue *txq;
  3579. int queue, err;
  3580. for (queue = 0; queue < txq_number; queue++) {
  3581. txq = port->txqs[queue];
  3582. err = mvpp2_txq_init(port, txq);
  3583. if (err)
  3584. goto err_cleanup;
  3585. }
  3586. mvpp2_txq_sent_counter_clear(port);
  3587. return 0;
  3588. err_cleanup:
  3589. mvpp2_cleanup_txqs(port);
  3590. return err;
  3591. }
  3592. /* Adjust link */
  3593. static void mvpp2_link_event(struct mvpp2_port *port)
  3594. {
  3595. struct phy_device *phydev = port->phy_dev;
  3596. int status_change = 0;
  3597. u32 val;
  3598. if (phydev->link) {
  3599. if ((port->speed != phydev->speed) ||
  3600. (port->duplex != phydev->duplex)) {
  3601. u32 val;
  3602. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3603. val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
  3604. MVPP2_GMAC_CONFIG_GMII_SPEED |
  3605. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  3606. MVPP2_GMAC_AN_SPEED_EN |
  3607. MVPP2_GMAC_AN_DUPLEX_EN);
  3608. if (phydev->duplex)
  3609. val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
  3610. if (phydev->speed == SPEED_1000)
  3611. val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
  3612. else if (phydev->speed == SPEED_100)
  3613. val |= MVPP2_GMAC_CONFIG_MII_SPEED;
  3614. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3615. port->duplex = phydev->duplex;
  3616. port->speed = phydev->speed;
  3617. }
  3618. }
  3619. if (phydev->link != port->link) {
  3620. if (!phydev->link) {
  3621. port->duplex = -1;
  3622. port->speed = 0;
  3623. }
  3624. port->link = phydev->link;
  3625. status_change = 1;
  3626. }
  3627. if (status_change) {
  3628. if (phydev->link) {
  3629. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3630. val |= (MVPP2_GMAC_FORCE_LINK_PASS |
  3631. MVPP2_GMAC_FORCE_LINK_DOWN);
  3632. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3633. mvpp2_egress_enable(port);
  3634. mvpp2_ingress_enable(port);
  3635. } else {
  3636. mvpp2_ingress_disable(port);
  3637. mvpp2_egress_disable(port);
  3638. }
  3639. }
  3640. }
  3641. /* Main RX/TX processing routines */
  3642. /* Display more error info */
  3643. static void mvpp2_rx_error(struct mvpp2_port *port,
  3644. struct mvpp2_rx_desc *rx_desc)
  3645. {
  3646. u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
  3647. size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
  3648. switch (status & MVPP2_RXD_ERR_CODE_MASK) {
  3649. case MVPP2_RXD_ERR_CRC:
  3650. netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
  3651. status, sz);
  3652. break;
  3653. case MVPP2_RXD_ERR_OVERRUN:
  3654. netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
  3655. status, sz);
  3656. break;
  3657. case MVPP2_RXD_ERR_RESOURCE:
  3658. netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
  3659. status, sz);
  3660. break;
  3661. }
  3662. }
  3663. /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
  3664. static int mvpp2_rx_refill(struct mvpp2_port *port,
  3665. struct mvpp2_bm_pool *bm_pool,
  3666. u32 bm, dma_addr_t dma_addr)
  3667. {
  3668. mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
  3669. return 0;
  3670. }
  3671. /* Set hw internals when starting port */
  3672. static void mvpp2_start_dev(struct mvpp2_port *port)
  3673. {
  3674. switch (port->phy_interface) {
  3675. case PHY_INTERFACE_MODE_RGMII:
  3676. case PHY_INTERFACE_MODE_RGMII_ID:
  3677. case PHY_INTERFACE_MODE_SGMII:
  3678. mvpp2_gmac_max_rx_size_set(port);
  3679. default:
  3680. break;
  3681. }
  3682. mvpp2_txp_max_tx_size_set(port);
  3683. if (port->priv->hw_version == MVPP21)
  3684. mvpp2_port_enable(port);
  3685. else
  3686. gop_port_enable(port, 1);
  3687. }
  3688. /* Set hw internals when stopping port */
  3689. static void mvpp2_stop_dev(struct mvpp2_port *port)
  3690. {
  3691. /* Stop new packets from arriving to RXQs */
  3692. mvpp2_ingress_disable(port);
  3693. mvpp2_egress_disable(port);
  3694. if (port->priv->hw_version == MVPP21)
  3695. mvpp2_port_disable(port);
  3696. else
  3697. gop_port_enable(port, 0);
  3698. }
  3699. static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
  3700. {
  3701. struct phy_device *phy_dev;
  3702. if (!port->init || port->link == 0) {
  3703. phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
  3704. dev, port->phy_interface);
  3705. /*
  3706. * If the phy doesn't match with any existing u-boot drivers the
  3707. * phy framework will connect it to generic one which
  3708. * uid == 0xffffffff. In this case act as if the phy wouldn't be
  3709. * declared in dts. Otherwise in case of 3310 (for which the
  3710. * driver doesn't exist) the link will not be correctly
  3711. * detected. Removing phy entry from dts in case of 3310 is not
  3712. * an option because it is required for the phy_fw_down
  3713. * procedure.
  3714. */
  3715. if (phy_dev &&
  3716. phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
  3717. netdev_warn(port->dev,
  3718. "Marking phy as invalid, link will not be checked\n");
  3719. /* set phy_addr to invalid value */
  3720. port->phyaddr = PHY_MAX_ADDR;
  3721. mvpp2_egress_enable(port);
  3722. mvpp2_ingress_enable(port);
  3723. return;
  3724. }
  3725. port->phy_dev = phy_dev;
  3726. if (!phy_dev) {
  3727. netdev_err(port->dev, "cannot connect to phy\n");
  3728. return;
  3729. }
  3730. phy_dev->supported &= PHY_GBIT_FEATURES;
  3731. phy_dev->advertising = phy_dev->supported;
  3732. port->phy_dev = phy_dev;
  3733. port->link = 0;
  3734. port->duplex = 0;
  3735. port->speed = 0;
  3736. phy_config(phy_dev);
  3737. phy_startup(phy_dev);
  3738. if (!phy_dev->link)
  3739. printf("%s: No link\n", phy_dev->dev->name);
  3740. else
  3741. port->init = 1;
  3742. } else {
  3743. mvpp2_egress_enable(port);
  3744. mvpp2_ingress_enable(port);
  3745. }
  3746. }
  3747. static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
  3748. {
  3749. unsigned char mac_bcast[ETH_ALEN] = {
  3750. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3751. int err;
  3752. err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
  3753. if (err) {
  3754. netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
  3755. return err;
  3756. }
  3757. err = mvpp2_prs_mac_da_accept(port->priv, port->id,
  3758. port->dev_addr, true);
  3759. if (err) {
  3760. netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
  3761. return err;
  3762. }
  3763. err = mvpp2_prs_def_flow(port);
  3764. if (err) {
  3765. netdev_err(dev, "mvpp2_prs_def_flow failed\n");
  3766. return err;
  3767. }
  3768. /* Allocate the Rx/Tx queues */
  3769. err = mvpp2_setup_rxqs(port);
  3770. if (err) {
  3771. netdev_err(port->dev, "cannot allocate Rx queues\n");
  3772. return err;
  3773. }
  3774. err = mvpp2_setup_txqs(port);
  3775. if (err) {
  3776. netdev_err(port->dev, "cannot allocate Tx queues\n");
  3777. return err;
  3778. }
  3779. if (port->phyaddr < PHY_MAX_ADDR) {
  3780. mvpp2_phy_connect(dev, port);
  3781. mvpp2_link_event(port);
  3782. } else {
  3783. mvpp2_egress_enable(port);
  3784. mvpp2_ingress_enable(port);
  3785. }
  3786. mvpp2_start_dev(port);
  3787. return 0;
  3788. }
  3789. /* No Device ops here in U-Boot */
  3790. /* Driver initialization */
  3791. static void mvpp2_port_power_up(struct mvpp2_port *port)
  3792. {
  3793. struct mvpp2 *priv = port->priv;
  3794. /* On PPv2.2 the GoP / interface configuration has already been done */
  3795. if (priv->hw_version == MVPP21)
  3796. mvpp2_port_mii_set(port);
  3797. mvpp2_port_periodic_xon_disable(port);
  3798. if (priv->hw_version == MVPP21)
  3799. mvpp2_port_fc_adv_enable(port);
  3800. mvpp2_port_reset(port);
  3801. }
  3802. /* Initialize port HW */
  3803. static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
  3804. {
  3805. struct mvpp2 *priv = port->priv;
  3806. struct mvpp2_txq_pcpu *txq_pcpu;
  3807. int queue, cpu, err;
  3808. if (port->first_rxq + rxq_number >
  3809. MVPP2_MAX_PORTS * priv->max_port_rxqs)
  3810. return -EINVAL;
  3811. /* Disable port */
  3812. mvpp2_egress_disable(port);
  3813. if (priv->hw_version == MVPP21)
  3814. mvpp2_port_disable(port);
  3815. else
  3816. gop_port_enable(port, 0);
  3817. port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
  3818. GFP_KERNEL);
  3819. if (!port->txqs)
  3820. return -ENOMEM;
  3821. /* Associate physical Tx queues to this port and initialize.
  3822. * The mapping is predefined.
  3823. */
  3824. for (queue = 0; queue < txq_number; queue++) {
  3825. int queue_phy_id = mvpp2_txq_phys(port->id, queue);
  3826. struct mvpp2_tx_queue *txq;
  3827. txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
  3828. if (!txq)
  3829. return -ENOMEM;
  3830. txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
  3831. GFP_KERNEL);
  3832. if (!txq->pcpu)
  3833. return -ENOMEM;
  3834. txq->id = queue_phy_id;
  3835. txq->log_id = queue;
  3836. txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
  3837. for_each_present_cpu(cpu) {
  3838. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3839. txq_pcpu->cpu = cpu;
  3840. }
  3841. port->txqs[queue] = txq;
  3842. }
  3843. port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
  3844. GFP_KERNEL);
  3845. if (!port->rxqs)
  3846. return -ENOMEM;
  3847. /* Allocate and initialize Rx queue for this port */
  3848. for (queue = 0; queue < rxq_number; queue++) {
  3849. struct mvpp2_rx_queue *rxq;
  3850. /* Map physical Rx queue to port's logical Rx queue */
  3851. rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
  3852. if (!rxq)
  3853. return -ENOMEM;
  3854. /* Map this Rx queue to a physical queue */
  3855. rxq->id = port->first_rxq + queue;
  3856. rxq->port = port->id;
  3857. rxq->logic_rxq = queue;
  3858. port->rxqs[queue] = rxq;
  3859. }
  3860. /* Create Rx descriptor rings */
  3861. for (queue = 0; queue < rxq_number; queue++) {
  3862. struct mvpp2_rx_queue *rxq = port->rxqs[queue];
  3863. rxq->size = port->rx_ring_size;
  3864. rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
  3865. rxq->time_coal = MVPP2_RX_COAL_USEC;
  3866. }
  3867. mvpp2_ingress_disable(port);
  3868. /* Port default configuration */
  3869. mvpp2_defaults_set(port);
  3870. /* Port's classifier configuration */
  3871. mvpp2_cls_oversize_rxq_set(port);
  3872. mvpp2_cls_port_config(port);
  3873. /* Provide an initial Rx packet size */
  3874. port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
  3875. /* Initialize pools for swf */
  3876. err = mvpp2_swf_bm_pool_init(port);
  3877. if (err)
  3878. return err;
  3879. return 0;
  3880. }
  3881. static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
  3882. {
  3883. int port_node = dev_of_offset(dev);
  3884. const char *phy_mode_str;
  3885. int phy_node;
  3886. u32 id;
  3887. u32 phyaddr = 0;
  3888. int phy_mode = -1;
  3889. int ret;
  3890. phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
  3891. if (phy_node > 0) {
  3892. int parent;
  3893. phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
  3894. if (phyaddr < 0) {
  3895. dev_err(&pdev->dev, "could not find phy address\n");
  3896. return -1;
  3897. }
  3898. parent = fdt_parent_offset(gd->fdt_blob, phy_node);
  3899. ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
  3900. &port->mdio_dev);
  3901. if (ret)
  3902. return ret;
  3903. } else {
  3904. /* phy_addr is set to invalid value */
  3905. phyaddr = PHY_MAX_ADDR;
  3906. }
  3907. phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
  3908. if (phy_mode_str)
  3909. phy_mode = phy_get_interface_by_name(phy_mode_str);
  3910. if (phy_mode == -1) {
  3911. dev_err(&pdev->dev, "incorrect phy mode\n");
  3912. return -EINVAL;
  3913. }
  3914. id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
  3915. if (id == -1) {
  3916. dev_err(&pdev->dev, "missing port-id value\n");
  3917. return -EINVAL;
  3918. }
  3919. #if CONFIG_IS_ENABLED(DM_GPIO)
  3920. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  3921. &port->phy_reset_gpio, GPIOD_IS_OUT);
  3922. gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
  3923. &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
  3924. #endif
  3925. /*
  3926. * ToDo:
  3927. * Not sure if this DT property "phy-speed" will get accepted, so
  3928. * this might change later
  3929. */
  3930. /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
  3931. port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
  3932. "phy-speed", 1000);
  3933. port->id = id;
  3934. if (port->priv->hw_version == MVPP21)
  3935. port->first_rxq = port->id * rxq_number;
  3936. else
  3937. port->first_rxq = port->id * port->priv->max_port_rxqs;
  3938. port->phy_interface = phy_mode;
  3939. port->phyaddr = phyaddr;
  3940. return 0;
  3941. }
  3942. #if CONFIG_IS_ENABLED(DM_GPIO)
  3943. /* Port GPIO initialization */
  3944. static void mvpp2_gpio_init(struct mvpp2_port *port)
  3945. {
  3946. if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
  3947. dm_gpio_set_value(&port->phy_reset_gpio, 1);
  3948. mdelay(10);
  3949. dm_gpio_set_value(&port->phy_reset_gpio, 0);
  3950. }
  3951. if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
  3952. dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
  3953. }
  3954. #endif
  3955. /* Ports initialization */
  3956. static int mvpp2_port_probe(struct udevice *dev,
  3957. struct mvpp2_port *port,
  3958. int port_node,
  3959. struct mvpp2 *priv)
  3960. {
  3961. int err;
  3962. port->tx_ring_size = MVPP2_MAX_TXD;
  3963. port->rx_ring_size = MVPP2_MAX_RXD;
  3964. err = mvpp2_port_init(dev, port);
  3965. if (err < 0) {
  3966. dev_err(&pdev->dev, "failed to init port %d\n", port->id);
  3967. return err;
  3968. }
  3969. mvpp2_port_power_up(port);
  3970. #if CONFIG_IS_ENABLED(DM_GPIO)
  3971. mvpp2_gpio_init(port);
  3972. #endif
  3973. priv->port_list[port->id] = port;
  3974. priv->num_ports++;
  3975. return 0;
  3976. }
  3977. /* Initialize decoding windows */
  3978. static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
  3979. struct mvpp2 *priv)
  3980. {
  3981. u32 win_enable;
  3982. int i;
  3983. for (i = 0; i < 6; i++) {
  3984. mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
  3985. mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
  3986. if (i < 4)
  3987. mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
  3988. }
  3989. win_enable = 0;
  3990. for (i = 0; i < dram->num_cs; i++) {
  3991. const struct mbus_dram_window *cs = dram->cs + i;
  3992. mvpp2_write(priv, MVPP2_WIN_BASE(i),
  3993. (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
  3994. dram->mbus_dram_target_id);
  3995. mvpp2_write(priv, MVPP2_WIN_SIZE(i),
  3996. (cs->size - 1) & 0xffff0000);
  3997. win_enable |= (1 << i);
  3998. }
  3999. mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
  4000. }
  4001. /* Initialize Rx FIFO's */
  4002. static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
  4003. {
  4004. int port;
  4005. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4006. if (priv->hw_version == MVPP22) {
  4007. if (port == 0) {
  4008. mvpp2_write(priv,
  4009. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4010. MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
  4011. mvpp2_write(priv,
  4012. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4013. MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
  4014. } else if (port == 1) {
  4015. mvpp2_write(priv,
  4016. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4017. MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
  4018. mvpp2_write(priv,
  4019. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4020. MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
  4021. } else {
  4022. mvpp2_write(priv,
  4023. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4024. MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
  4025. mvpp2_write(priv,
  4026. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4027. MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
  4028. }
  4029. } else {
  4030. mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4031. MVPP21_RX_FIFO_PORT_DATA_SIZE);
  4032. mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4033. MVPP21_RX_FIFO_PORT_ATTR_SIZE);
  4034. }
  4035. }
  4036. mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
  4037. MVPP2_RX_FIFO_PORT_MIN_PKT);
  4038. mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
  4039. }
  4040. /* Initialize Tx FIFO's */
  4041. static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
  4042. {
  4043. int port, val;
  4044. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4045. /* Port 0 supports 10KB TX FIFO */
  4046. if (port == 0) {
  4047. val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
  4048. MVPP22_TX_FIFO_SIZE_MASK;
  4049. } else {
  4050. val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
  4051. MVPP22_TX_FIFO_SIZE_MASK;
  4052. }
  4053. mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
  4054. }
  4055. }
  4056. static void mvpp2_axi_init(struct mvpp2 *priv)
  4057. {
  4058. u32 val, rdval, wrval;
  4059. mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
  4060. /* AXI Bridge Configuration */
  4061. rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4062. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4063. rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4064. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4065. wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4066. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4067. wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4068. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4069. /* BM */
  4070. mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
  4071. mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
  4072. /* Descriptors */
  4073. mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
  4074. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
  4075. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
  4076. mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
  4077. /* Buffer Data */
  4078. mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
  4079. mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
  4080. val = MVPP22_AXI_CODE_CACHE_NON_CACHE
  4081. << MVPP22_AXI_CODE_CACHE_OFFS;
  4082. val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
  4083. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4084. mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
  4085. mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
  4086. val = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4087. << MVPP22_AXI_CODE_CACHE_OFFS;
  4088. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4089. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4090. mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
  4091. val = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4092. << MVPP22_AXI_CODE_CACHE_OFFS;
  4093. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4094. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4095. mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
  4096. }
  4097. /* Initialize network controller common part HW */
  4098. static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
  4099. {
  4100. const struct mbus_dram_target_info *dram_target_info;
  4101. int err, i;
  4102. u32 val;
  4103. /* Checks for hardware constraints (U-Boot uses only one rxq) */
  4104. if ((rxq_number > priv->max_port_rxqs) ||
  4105. (txq_number > MVPP2_MAX_TXQ)) {
  4106. dev_err(&pdev->dev, "invalid queue size parameter\n");
  4107. return -EINVAL;
  4108. }
  4109. if (priv->hw_version == MVPP22)
  4110. mvpp2_axi_init(priv);
  4111. else {
  4112. /* MBUS windows configuration */
  4113. dram_target_info = mvebu_mbus_dram_info();
  4114. if (dram_target_info)
  4115. mvpp2_conf_mbus_windows(dram_target_info, priv);
  4116. }
  4117. if (priv->hw_version == MVPP21) {
  4118. /* Disable HW PHY polling */
  4119. val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4120. val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
  4121. writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4122. } else {
  4123. /* Enable HW PHY polling */
  4124. val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4125. val |= MVPP22_SMI_POLLING_EN;
  4126. writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4127. }
  4128. /* Allocate and initialize aggregated TXQs */
  4129. priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
  4130. sizeof(struct mvpp2_tx_queue),
  4131. GFP_KERNEL);
  4132. if (!priv->aggr_txqs)
  4133. return -ENOMEM;
  4134. for_each_present_cpu(i) {
  4135. priv->aggr_txqs[i].id = i;
  4136. priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
  4137. err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
  4138. MVPP2_AGGR_TXQ_SIZE, i, priv);
  4139. if (err < 0)
  4140. return err;
  4141. }
  4142. /* Rx Fifo Init */
  4143. mvpp2_rx_fifo_init(priv);
  4144. /* Tx Fifo Init */
  4145. if (priv->hw_version == MVPP22)
  4146. mvpp2_tx_fifo_init(priv);
  4147. if (priv->hw_version == MVPP21)
  4148. writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
  4149. priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
  4150. /* Allow cache snoop when transmiting packets */
  4151. mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
  4152. /* Buffer Manager initialization */
  4153. err = mvpp2_bm_init(dev, priv);
  4154. if (err < 0)
  4155. return err;
  4156. /* Parser default initialization */
  4157. err = mvpp2_prs_default_init(dev, priv);
  4158. if (err < 0)
  4159. return err;
  4160. /* Classifier default initialization */
  4161. mvpp2_cls_init(priv);
  4162. return 0;
  4163. }
  4164. static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
  4165. {
  4166. struct mvpp2_port *port = dev_get_priv(dev);
  4167. struct mvpp2_rx_desc *rx_desc;
  4168. struct mvpp2_bm_pool *bm_pool;
  4169. dma_addr_t dma_addr;
  4170. u32 bm, rx_status;
  4171. int pool, rx_bytes, err;
  4172. int rx_received;
  4173. struct mvpp2_rx_queue *rxq;
  4174. u8 *data;
  4175. if (port->phyaddr < PHY_MAX_ADDR)
  4176. if (!port->phy_dev->link)
  4177. return 0;
  4178. /* Process RX packets */
  4179. rxq = port->rxqs[0];
  4180. /* Get number of received packets and clamp the to-do */
  4181. rx_received = mvpp2_rxq_received(port, rxq->id);
  4182. /* Return if no packets are received */
  4183. if (!rx_received)
  4184. return 0;
  4185. rx_desc = mvpp2_rxq_next_desc_get(rxq);
  4186. rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
  4187. rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
  4188. rx_bytes -= MVPP2_MH_SIZE;
  4189. dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
  4190. bm = mvpp2_bm_cookie_build(port, rx_desc);
  4191. pool = mvpp2_bm_cookie_pool_get(bm);
  4192. bm_pool = &port->priv->bm_pools[pool];
  4193. /* In case of an error, release the requested buffer pointer
  4194. * to the Buffer Manager. This request process is controlled
  4195. * by the hardware, and the information about the buffer is
  4196. * comprised by the RX descriptor.
  4197. */
  4198. if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
  4199. mvpp2_rx_error(port, rx_desc);
  4200. /* Return the buffer to the pool */
  4201. mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
  4202. return 0;
  4203. }
  4204. err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
  4205. if (err) {
  4206. netdev_err(port->dev, "failed to refill BM pools\n");
  4207. return 0;
  4208. }
  4209. /* Update Rx queue management counters */
  4210. mb();
  4211. mvpp2_rxq_status_update(port, rxq->id, 1, 1);
  4212. /* give packet to stack - skip on first n bytes */
  4213. data = (u8 *)dma_addr + 2 + 32;
  4214. if (rx_bytes <= 0)
  4215. return 0;
  4216. /*
  4217. * No cache invalidation needed here, since the rx_buffer's are
  4218. * located in a uncached memory region
  4219. */
  4220. *packetp = data;
  4221. return rx_bytes;
  4222. }
  4223. static int mvpp2_send(struct udevice *dev, void *packet, int length)
  4224. {
  4225. struct mvpp2_port *port = dev_get_priv(dev);
  4226. struct mvpp2_tx_queue *txq, *aggr_txq;
  4227. struct mvpp2_tx_desc *tx_desc;
  4228. int tx_done;
  4229. int timeout;
  4230. if (port->phyaddr < PHY_MAX_ADDR)
  4231. if (!port->phy_dev->link)
  4232. return 0;
  4233. txq = port->txqs[0];
  4234. aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
  4235. /* Get a descriptor for the first part of the packet */
  4236. tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
  4237. mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
  4238. mvpp2_txdesc_size_set(port, tx_desc, length);
  4239. mvpp2_txdesc_offset_set(port, tx_desc,
  4240. (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
  4241. mvpp2_txdesc_dma_addr_set(port, tx_desc,
  4242. (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
  4243. /* First and Last descriptor */
  4244. mvpp2_txdesc_cmd_set(port, tx_desc,
  4245. MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
  4246. | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
  4247. /* Flush tx data */
  4248. flush_dcache_range((unsigned long)packet,
  4249. (unsigned long)packet + ALIGN(length, PKTALIGN));
  4250. /* Enable transmit */
  4251. mb();
  4252. mvpp2_aggr_txq_pend_desc_add(port, 1);
  4253. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  4254. timeout = 0;
  4255. do {
  4256. if (timeout++ > 10000) {
  4257. printf("timeout: packet not sent from aggregated to phys TXQ\n");
  4258. return 0;
  4259. }
  4260. tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
  4261. } while (tx_done);
  4262. timeout = 0;
  4263. do {
  4264. if (timeout++ > 10000) {
  4265. printf("timeout: packet not sent\n");
  4266. return 0;
  4267. }
  4268. tx_done = mvpp2_txq_sent_desc_proc(port, txq);
  4269. } while (!tx_done);
  4270. return 0;
  4271. }
  4272. static int mvpp2_start(struct udevice *dev)
  4273. {
  4274. struct eth_pdata *pdata = dev_get_platdata(dev);
  4275. struct mvpp2_port *port = dev_get_priv(dev);
  4276. /* Load current MAC address */
  4277. memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
  4278. /* Reconfigure parser accept the original MAC address */
  4279. mvpp2_prs_update_mac_da(port, port->dev_addr);
  4280. switch (port->phy_interface) {
  4281. case PHY_INTERFACE_MODE_RGMII:
  4282. case PHY_INTERFACE_MODE_RGMII_ID:
  4283. case PHY_INTERFACE_MODE_SGMII:
  4284. mvpp2_port_power_up(port);
  4285. default:
  4286. break;
  4287. }
  4288. mvpp2_open(dev, port);
  4289. return 0;
  4290. }
  4291. static void mvpp2_stop(struct udevice *dev)
  4292. {
  4293. struct mvpp2_port *port = dev_get_priv(dev);
  4294. mvpp2_stop_dev(port);
  4295. mvpp2_cleanup_rxqs(port);
  4296. mvpp2_cleanup_txqs(port);
  4297. }
  4298. static int mvpp2_write_hwaddr(struct udevice *dev)
  4299. {
  4300. struct mvpp2_port *port = dev_get_priv(dev);
  4301. return mvpp2_prs_update_mac_da(port, port->dev_addr);
  4302. }
  4303. static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
  4304. {
  4305. writel(port->phyaddr, port->priv->iface_base +
  4306. MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
  4307. return 0;
  4308. }
  4309. static int mvpp2_base_probe(struct udevice *dev)
  4310. {
  4311. struct mvpp2 *priv = dev_get_priv(dev);
  4312. void *bd_space;
  4313. u32 size = 0;
  4314. int i;
  4315. /* Save hw-version */
  4316. priv->hw_version = dev_get_driver_data(dev);
  4317. /*
  4318. * U-Boot special buffer handling:
  4319. *
  4320. * Allocate buffer area for descs and rx_buffers. This is only
  4321. * done once for all interfaces. As only one interface can
  4322. * be active. Make this area DMA-safe by disabling the D-cache
  4323. */
  4324. /* Align buffer area for descs and rx_buffers to 1MiB */
  4325. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  4326. mmu_set_region_dcache_behaviour((unsigned long)bd_space,
  4327. BD_SPACE, DCACHE_OFF);
  4328. buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
  4329. size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
  4330. buffer_loc.tx_descs =
  4331. (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
  4332. size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
  4333. buffer_loc.rx_descs =
  4334. (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
  4335. size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
  4336. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  4337. buffer_loc.bm_pool[i] =
  4338. (unsigned long *)((unsigned long)bd_space + size);
  4339. if (priv->hw_version == MVPP21)
  4340. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
  4341. else
  4342. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
  4343. }
  4344. for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
  4345. buffer_loc.rx_buffer[i] =
  4346. (unsigned long *)((unsigned long)bd_space + size);
  4347. size += RX_BUFFER_SIZE;
  4348. }
  4349. /* Clear the complete area so that all descriptors are cleared */
  4350. memset(bd_space, 0, size);
  4351. /* Save base addresses for later use */
  4352. priv->base = (void *)devfdt_get_addr_index(dev, 0);
  4353. if (IS_ERR(priv->base))
  4354. return PTR_ERR(priv->base);
  4355. if (priv->hw_version == MVPP21) {
  4356. priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
  4357. if (IS_ERR(priv->lms_base))
  4358. return PTR_ERR(priv->lms_base);
  4359. } else {
  4360. priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
  4361. if (IS_ERR(priv->iface_base))
  4362. return PTR_ERR(priv->iface_base);
  4363. /* Store common base addresses for all ports */
  4364. priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
  4365. priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
  4366. priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
  4367. }
  4368. if (priv->hw_version == MVPP21)
  4369. priv->max_port_rxqs = 8;
  4370. else
  4371. priv->max_port_rxqs = 32;
  4372. return 0;
  4373. }
  4374. static int mvpp2_probe(struct udevice *dev)
  4375. {
  4376. struct mvpp2_port *port = dev_get_priv(dev);
  4377. struct mvpp2 *priv = dev_get_priv(dev->parent);
  4378. int err;
  4379. /* Only call the probe function for the parent once */
  4380. if (!priv->probe_done)
  4381. err = mvpp2_base_probe(dev->parent);
  4382. port->priv = priv;
  4383. err = phy_info_parse(dev, port);
  4384. if (err)
  4385. return err;
  4386. /*
  4387. * We need the port specific io base addresses at this stage, since
  4388. * gop_port_init() accesses these registers
  4389. */
  4390. if (priv->hw_version == MVPP21) {
  4391. int priv_common_regs_num = 2;
  4392. port->base = (void __iomem *)devfdt_get_addr_index(
  4393. dev->parent, priv_common_regs_num + port->id);
  4394. if (IS_ERR(port->base))
  4395. return PTR_ERR(port->base);
  4396. } else {
  4397. port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  4398. "gop-port-id", -1);
  4399. if (port->id == -1) {
  4400. dev_err(&pdev->dev, "missing gop-port-id value\n");
  4401. return -EINVAL;
  4402. }
  4403. port->base = priv->iface_base + MVPP22_PORT_BASE +
  4404. port->gop_id * MVPP22_PORT_OFFSET;
  4405. /* Set phy address of the port */
  4406. if (port->phyaddr < PHY_MAX_ADDR)
  4407. mvpp22_smi_phy_addr_cfg(port);
  4408. /* GoP Init */
  4409. gop_port_init(port);
  4410. }
  4411. if (!priv->probe_done) {
  4412. /* Initialize network controller */
  4413. err = mvpp2_init(dev, priv);
  4414. if (err < 0) {
  4415. dev_err(&pdev->dev, "failed to initialize controller\n");
  4416. return err;
  4417. }
  4418. priv->num_ports = 0;
  4419. priv->probe_done = 1;
  4420. }
  4421. err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
  4422. if (err)
  4423. return err;
  4424. if (priv->hw_version == MVPP22) {
  4425. priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
  4426. port->phy_interface);
  4427. /* Netcomplex configurations for all ports */
  4428. gop_netc_init(priv, MV_NETC_FIRST_PHASE);
  4429. gop_netc_init(priv, MV_NETC_SECOND_PHASE);
  4430. }
  4431. return 0;
  4432. }
  4433. /*
  4434. * Empty BM pool and stop its activity before the OS is started
  4435. */
  4436. static int mvpp2_remove(struct udevice *dev)
  4437. {
  4438. struct mvpp2_port *port = dev_get_priv(dev);
  4439. struct mvpp2 *priv = port->priv;
  4440. int i;
  4441. priv->num_ports--;
  4442. if (priv->num_ports)
  4443. return 0;
  4444. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
  4445. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  4446. return 0;
  4447. }
  4448. static const struct eth_ops mvpp2_ops = {
  4449. .start = mvpp2_start,
  4450. .send = mvpp2_send,
  4451. .recv = mvpp2_recv,
  4452. .stop = mvpp2_stop,
  4453. .write_hwaddr = mvpp2_write_hwaddr
  4454. };
  4455. static struct driver mvpp2_driver = {
  4456. .name = "mvpp2",
  4457. .id = UCLASS_ETH,
  4458. .probe = mvpp2_probe,
  4459. .remove = mvpp2_remove,
  4460. .ops = &mvpp2_ops,
  4461. .priv_auto_alloc_size = sizeof(struct mvpp2_port),
  4462. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  4463. .flags = DM_FLAG_ACTIVE_DMA,
  4464. };
  4465. /*
  4466. * Use a MISC device to bind the n instances (child nodes) of the
  4467. * network base controller in UCLASS_ETH.
  4468. */
  4469. static int mvpp2_base_bind(struct udevice *parent)
  4470. {
  4471. const void *blob = gd->fdt_blob;
  4472. int node = dev_of_offset(parent);
  4473. struct uclass_driver *drv;
  4474. struct udevice *dev;
  4475. struct eth_pdata *plat;
  4476. char *name;
  4477. int subnode;
  4478. u32 id;
  4479. int base_id_add;
  4480. /* Lookup eth driver */
  4481. drv = lists_uclass_lookup(UCLASS_ETH);
  4482. if (!drv) {
  4483. puts("Cannot find eth driver\n");
  4484. return -ENOENT;
  4485. }
  4486. base_id_add = base_id;
  4487. fdt_for_each_subnode(subnode, blob, node) {
  4488. /* Increment base_id for all subnodes, also the disabled ones */
  4489. base_id++;
  4490. /* Skip disabled ports */
  4491. if (!fdtdec_get_is_enabled(blob, subnode))
  4492. continue;
  4493. plat = calloc(1, sizeof(*plat));
  4494. if (!plat)
  4495. return -ENOMEM;
  4496. id = fdtdec_get_int(blob, subnode, "port-id", -1);
  4497. id += base_id_add;
  4498. name = calloc(1, 16);
  4499. if (!name) {
  4500. free(plat);
  4501. return -ENOMEM;
  4502. }
  4503. sprintf(name, "mvpp2-%d", id);
  4504. /* Create child device UCLASS_ETH and bind it */
  4505. device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
  4506. dev_set_of_offset(dev, subnode);
  4507. }
  4508. return 0;
  4509. }
  4510. static const struct udevice_id mvpp2_ids[] = {
  4511. {
  4512. .compatible = "marvell,armada-375-pp2",
  4513. .data = MVPP21,
  4514. },
  4515. {
  4516. .compatible = "marvell,armada-7k-pp22",
  4517. .data = MVPP22,
  4518. },
  4519. { }
  4520. };
  4521. U_BOOT_DRIVER(mvpp2_base) = {
  4522. .name = "mvpp2_base",
  4523. .id = UCLASS_MISC,
  4524. .of_match = mvpp2_ids,
  4525. .bind = mvpp2_base_bind,
  4526. .priv_auto_alloc_size = sizeof(struct mvpp2),
  4527. };