mvneta.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  4. *
  5. * U-Boot version:
  6. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  7. *
  8. * Based on the Linux version which is:
  9. * Copyright (C) 2012 Marvell
  10. *
  11. * Rami Rosen <rosenr@marvell.com>
  12. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13. */
  14. #include <common.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. #include <config.h>
  21. #include <malloc.h>
  22. #include <asm/cache.h>
  23. #include <asm/io.h>
  24. #include <dm/device_compat.h>
  25. #include <dm/devres.h>
  26. #include <linux/bug.h>
  27. #include <linux/errno.h>
  28. #include <phy.h>
  29. #include <miiphy.h>
  30. #include <watchdog.h>
  31. #include <asm/arch/cpu.h>
  32. #include <asm/arch/soc.h>
  33. #include <linux/compat.h>
  34. #include <linux/mbus.h>
  35. #include <asm-generic/gpio.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #if !defined(CONFIG_PHYLIB)
  38. # error Marvell mvneta requires PHYLIB
  39. #endif
  40. #define CONFIG_NR_CPUS 1
  41. #define ETH_HLEN 14 /* Total octets in header */
  42. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  43. #define WRAP (2 + ETH_HLEN + 4 + 32)
  44. #define MTU 1500
  45. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  46. #define MVNETA_SMI_TIMEOUT 10000
  47. /* Registers */
  48. #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
  49. #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
  50. #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
  51. #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
  52. #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
  53. #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
  54. #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
  55. #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
  56. #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
  57. #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
  58. #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
  59. #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
  60. #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
  61. #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
  62. #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
  63. #define MVNETA_PORT_RX_RESET 0x1cc0
  64. #define MVNETA_PORT_RX_DMA_RESET BIT(0)
  65. #define MVNETA_PHY_ADDR 0x2000
  66. #define MVNETA_PHY_ADDR_MASK 0x1f
  67. #define MVNETA_SMI 0x2004
  68. #define MVNETA_PHY_REG_MASK 0x1f
  69. /* SMI register fields */
  70. #define MVNETA_SMI_DATA_OFFS 0 /* Data */
  71. #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
  72. #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  73. #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  74. #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  75. #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
  76. #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
  77. #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
  78. #define MVNETA_MBUS_RETRY 0x2010
  79. #define MVNETA_UNIT_INTR_CAUSE 0x2080
  80. #define MVNETA_UNIT_CONTROL 0x20B0
  81. #define MVNETA_PHY_POLLING_ENABLE BIT(1)
  82. #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
  83. #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
  84. #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
  85. #define MVNETA_WIN_SIZE_MASK (0xffff0000)
  86. #define MVNETA_BASE_ADDR_ENABLE 0x2290
  87. #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
  88. #define MVNETA_PORT_ACCESS_PROTECT 0x2294
  89. #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
  90. #define MVNETA_PORT_CONFIG 0x2400
  91. #define MVNETA_UNI_PROMISC_MODE BIT(0)
  92. #define MVNETA_DEF_RXQ(q) ((q) << 1)
  93. #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
  94. #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
  95. #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
  96. #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
  97. #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
  98. #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
  99. #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
  100. MVNETA_DEF_RXQ_ARP(q) | \
  101. MVNETA_DEF_RXQ_TCP(q) | \
  102. MVNETA_DEF_RXQ_UDP(q) | \
  103. MVNETA_DEF_RXQ_BPDU(q) | \
  104. MVNETA_TX_UNSET_ERR_SUM | \
  105. MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
  106. #define MVNETA_PORT_CONFIG_EXTEND 0x2404
  107. #define MVNETA_MAC_ADDR_LOW 0x2414
  108. #define MVNETA_MAC_ADDR_HIGH 0x2418
  109. #define MVNETA_SDMA_CONFIG 0x241c
  110. #define MVNETA_SDMA_BRST_SIZE_16 4
  111. #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
  112. #define MVNETA_RX_NO_DATA_SWAP BIT(4)
  113. #define MVNETA_TX_NO_DATA_SWAP BIT(5)
  114. #define MVNETA_DESC_SWAP BIT(6)
  115. #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
  116. #define MVNETA_PORT_STATUS 0x2444
  117. #define MVNETA_TX_IN_PRGRS BIT(1)
  118. #define MVNETA_TX_FIFO_EMPTY BIT(8)
  119. #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
  120. #define MVNETA_SERDES_CFG 0x24A0
  121. #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
  122. #define MVNETA_QSGMII_SERDES_PROTO 0x0667
  123. #define MVNETA_TYPE_PRIO 0x24bc
  124. #define MVNETA_FORCE_UNI BIT(21)
  125. #define MVNETA_TXQ_CMD_1 0x24e4
  126. #define MVNETA_TXQ_CMD 0x2448
  127. #define MVNETA_TXQ_DISABLE_SHIFT 8
  128. #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
  129. #define MVNETA_ACC_MODE 0x2500
  130. #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
  131. #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
  132. #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
  133. #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
  134. /* Exception Interrupt Port/Queue Cause register */
  135. #define MVNETA_INTR_NEW_CAUSE 0x25a0
  136. #define MVNETA_INTR_NEW_MASK 0x25a4
  137. /* bits 0..7 = TXQ SENT, one bit per queue.
  138. * bits 8..15 = RXQ OCCUP, one bit per queue.
  139. * bits 16..23 = RXQ FREE, one bit per queue.
  140. * bit 29 = OLD_REG_SUM, see old reg ?
  141. * bit 30 = TX_ERR_SUM, one bit for 4 ports
  142. * bit 31 = MISC_SUM, one bit for 4 ports
  143. */
  144. #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
  145. #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
  146. #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
  147. #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
  148. #define MVNETA_INTR_OLD_CAUSE 0x25a8
  149. #define MVNETA_INTR_OLD_MASK 0x25ac
  150. /* Data Path Port/Queue Cause Register */
  151. #define MVNETA_INTR_MISC_CAUSE 0x25b0
  152. #define MVNETA_INTR_MISC_MASK 0x25b4
  153. #define MVNETA_INTR_ENABLE 0x25b8
  154. #define MVNETA_RXQ_CMD 0x2680
  155. #define MVNETA_RXQ_DISABLE_SHIFT 8
  156. #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
  157. #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
  158. #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
  159. #define MVNETA_GMAC_CTRL_0 0x2c00
  160. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  161. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  162. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  163. #define MVNETA_GMAC_CTRL_2 0x2c08
  164. #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
  165. #define MVNETA_GMAC2_PORT_RGMII BIT(4)
  166. #define MVNETA_GMAC2_PORT_RESET BIT(6)
  167. #define MVNETA_GMAC_STATUS 0x2c10
  168. #define MVNETA_GMAC_LINK_UP BIT(0)
  169. #define MVNETA_GMAC_SPEED_1000 BIT(1)
  170. #define MVNETA_GMAC_SPEED_100 BIT(2)
  171. #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
  172. #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
  173. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  174. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  175. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  176. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  177. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  178. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  179. #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
  180. #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
  181. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  182. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  183. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  184. #define MVNETA_GMAC_SET_FC_EN BIT(8)
  185. #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
  186. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  187. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  188. #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
  189. #define MVNETA_MIB_COUNTERS_BASE 0x3080
  190. #define MVNETA_MIB_LATE_COLLISION 0x7c
  191. #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
  192. #define MVNETA_DA_FILT_OTH_MCAST 0x3500
  193. #define MVNETA_DA_FILT_UCAST_BASE 0x3600
  194. #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
  195. #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
  196. #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
  197. #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
  198. #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
  199. #define MVNETA_TXQ_DEC_SENT_SHIFT 16
  200. #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
  201. #define MVNETA_TXQ_SENT_DESC_SHIFT 16
  202. #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
  203. #define MVNETA_PORT_TX_RESET 0x3cf0
  204. #define MVNETA_PORT_TX_DMA_RESET BIT(0)
  205. #define MVNETA_TX_MTU 0x3e0c
  206. #define MVNETA_TX_TOKEN_SIZE 0x3e14
  207. #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
  208. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  209. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  210. /* Descriptor ring Macros */
  211. #define MVNETA_QUEUE_NEXT_DESC(q, index) \
  212. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  213. /* Various constants */
  214. /* Coalescing */
  215. #define MVNETA_TXDONE_COAL_PKTS 16
  216. #define MVNETA_RX_COAL_PKTS 32
  217. #define MVNETA_RX_COAL_USEC 100
  218. /* The two bytes Marvell header. Either contains a special value used
  219. * by Marvell switches when a specific hardware mode is enabled (not
  220. * supported by this driver) or is filled automatically by zeroes on
  221. * the RX side. Those two bytes being at the front of the Ethernet
  222. * header, they allow to have the IP header aligned on a 4 bytes
  223. * boundary automatically: the hardware skips those two bytes on its
  224. * own.
  225. */
  226. #define MVNETA_MH_SIZE 2
  227. #define MVNETA_VLAN_TAG_LEN 4
  228. #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
  229. #define MVNETA_TX_CSUM_MAX_SIZE 9800
  230. #define MVNETA_ACC_MODE_EXT 1
  231. /* Timeout constants */
  232. #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
  233. #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
  234. #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
  235. #define MVNETA_TX_MTU_MAX 0x3ffff
  236. /* Max number of Rx descriptors */
  237. #define MVNETA_MAX_RXD 16
  238. /* Max number of Tx descriptors */
  239. #define MVNETA_MAX_TXD 16
  240. /* descriptor aligned size */
  241. #define MVNETA_DESC_ALIGNED_SIZE 32
  242. struct mvneta_port {
  243. void __iomem *base;
  244. struct mvneta_rx_queue *rxqs;
  245. struct mvneta_tx_queue *txqs;
  246. u8 mcast_count[256];
  247. u16 tx_ring_size;
  248. u16 rx_ring_size;
  249. phy_interface_t phy_interface;
  250. unsigned int link;
  251. unsigned int duplex;
  252. unsigned int speed;
  253. int init;
  254. int phyaddr;
  255. struct phy_device *phydev;
  256. #if CONFIG_IS_ENABLED(DM_GPIO)
  257. struct gpio_desc phy_reset_gpio;
  258. #endif
  259. struct mii_dev *bus;
  260. };
  261. /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
  262. * layout of the transmit and reception DMA descriptors, and their
  263. * layout is therefore defined by the hardware design
  264. */
  265. #define MVNETA_TX_L3_OFF_SHIFT 0
  266. #define MVNETA_TX_IP_HLEN_SHIFT 8
  267. #define MVNETA_TX_L4_UDP BIT(16)
  268. #define MVNETA_TX_L3_IP6 BIT(17)
  269. #define MVNETA_TXD_IP_CSUM BIT(18)
  270. #define MVNETA_TXD_Z_PAD BIT(19)
  271. #define MVNETA_TXD_L_DESC BIT(20)
  272. #define MVNETA_TXD_F_DESC BIT(21)
  273. #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
  274. MVNETA_TXD_L_DESC | \
  275. MVNETA_TXD_F_DESC)
  276. #define MVNETA_TX_L4_CSUM_FULL BIT(30)
  277. #define MVNETA_TX_L4_CSUM_NOT BIT(31)
  278. #define MVNETA_RXD_ERR_CRC 0x0
  279. #define MVNETA_RXD_ERR_SUMMARY BIT(16)
  280. #define MVNETA_RXD_ERR_OVERRUN BIT(17)
  281. #define MVNETA_RXD_ERR_LEN BIT(18)
  282. #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
  283. #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
  284. #define MVNETA_RXD_L3_IP4 BIT(25)
  285. #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
  286. #define MVNETA_RXD_L4_CSUM_OK BIT(30)
  287. struct mvneta_tx_desc {
  288. u32 command; /* Options used by HW for packet transmitting.*/
  289. u16 reserverd1; /* csum_l4 (for future use) */
  290. u16 data_size; /* Data size of transmitted packet in bytes */
  291. u32 buf_phys_addr; /* Physical addr of transmitted buffer */
  292. u32 reserved2; /* hw_cmd - (for future use, PMT) */
  293. u32 reserved3[4]; /* Reserved - (for future use) */
  294. };
  295. struct mvneta_rx_desc {
  296. u32 status; /* Info about received packet */
  297. u16 reserved1; /* pnc_info - (for future use, PnC) */
  298. u16 data_size; /* Size of received packet in bytes */
  299. u32 buf_phys_addr; /* Physical address of the buffer */
  300. u32 reserved2; /* pnc_flow_id (for future use, PnC) */
  301. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  302. u16 reserved3; /* prefetch_cmd, for future use */
  303. u16 reserved4; /* csum_l4 - (for future use, PnC) */
  304. u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
  305. u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
  306. };
  307. struct mvneta_tx_queue {
  308. /* Number of this TX queue, in the range 0-7 */
  309. u8 id;
  310. /* Number of TX DMA descriptors in the descriptor ring */
  311. int size;
  312. /* Index of last TX DMA descriptor that was inserted */
  313. int txq_put_index;
  314. /* Index of the TX DMA descriptor to be cleaned up */
  315. int txq_get_index;
  316. /* Virtual address of the TX DMA descriptors array */
  317. struct mvneta_tx_desc *descs;
  318. /* DMA address of the TX DMA descriptors array */
  319. dma_addr_t descs_phys;
  320. /* Index of the last TX DMA descriptor */
  321. int last_desc;
  322. /* Index of the next TX DMA descriptor to process */
  323. int next_desc_to_proc;
  324. };
  325. struct mvneta_rx_queue {
  326. /* rx queue number, in the range 0-7 */
  327. u8 id;
  328. /* num of rx descriptors in the rx descriptor ring */
  329. int size;
  330. /* Virtual address of the RX DMA descriptors array */
  331. struct mvneta_rx_desc *descs;
  332. /* DMA address of the RX DMA descriptors array */
  333. dma_addr_t descs_phys;
  334. /* Index of the last RX DMA descriptor */
  335. int last_desc;
  336. /* Index of the next RX DMA descriptor to process */
  337. int next_desc_to_proc;
  338. };
  339. /* U-Boot doesn't use the queues, so set the number to 1 */
  340. static int rxq_number = 1;
  341. static int txq_number = 1;
  342. static int rxq_def;
  343. struct buffer_location {
  344. struct mvneta_tx_desc *tx_descs;
  345. struct mvneta_rx_desc *rx_descs;
  346. u32 rx_buffers;
  347. };
  348. /*
  349. * All 4 interfaces use the same global buffer, since only one interface
  350. * can be enabled at once
  351. */
  352. static struct buffer_location buffer_loc;
  353. /*
  354. * Page table entries are set to 1MB, or multiples of 1MB
  355. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  356. */
  357. #define BD_SPACE (1 << 20)
  358. /*
  359. * Dummy implementation that can be overwritten by a board
  360. * specific function
  361. */
  362. __weak int board_network_enable(struct mii_dev *bus)
  363. {
  364. return 0;
  365. }
  366. /* Utility/helper methods */
  367. /* Write helper method */
  368. static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
  369. {
  370. writel(data, pp->base + offset);
  371. }
  372. /* Read helper method */
  373. static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
  374. {
  375. return readl(pp->base + offset);
  376. }
  377. /* Clear all MIB counters */
  378. static void mvneta_mib_counters_clear(struct mvneta_port *pp)
  379. {
  380. int i;
  381. /* Perform dummy reads from MIB counters */
  382. for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
  383. mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
  384. }
  385. /* Rx descriptors helper methods */
  386. /* Checks whether the RX descriptor having this status is both the first
  387. * and the last descriptor for the RX packet. Each RX packet is currently
  388. * received through a single RX descriptor, so not having each RX
  389. * descriptor with its first and last bits set is an error
  390. */
  391. static int mvneta_rxq_desc_is_first_last(u32 status)
  392. {
  393. return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
  394. MVNETA_RXD_FIRST_LAST_DESC;
  395. }
  396. /* Add number of descriptors ready to receive new packets */
  397. static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
  398. struct mvneta_rx_queue *rxq,
  399. int ndescs)
  400. {
  401. /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
  402. * be added at once
  403. */
  404. while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
  405. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  406. (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
  407. MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  408. ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
  409. }
  410. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  411. (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  412. }
  413. /* Get number of RX descriptors occupied by received packets */
  414. static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
  415. struct mvneta_rx_queue *rxq)
  416. {
  417. u32 val;
  418. val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
  419. return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
  420. }
  421. /* Update num of rx desc called upon return from rx path or
  422. * from mvneta_rxq_drop_pkts().
  423. */
  424. static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
  425. struct mvneta_rx_queue *rxq,
  426. int rx_done, int rx_filled)
  427. {
  428. u32 val;
  429. if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
  430. val = rx_done |
  431. (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
  432. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  433. return;
  434. }
  435. /* Only 255 descriptors can be added at once */
  436. while ((rx_done > 0) || (rx_filled > 0)) {
  437. if (rx_done <= 0xff) {
  438. val = rx_done;
  439. rx_done = 0;
  440. } else {
  441. val = 0xff;
  442. rx_done -= 0xff;
  443. }
  444. if (rx_filled <= 0xff) {
  445. val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  446. rx_filled = 0;
  447. } else {
  448. val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  449. rx_filled -= 0xff;
  450. }
  451. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  452. }
  453. }
  454. /* Get pointer to next RX descriptor to be processed by SW */
  455. static struct mvneta_rx_desc *
  456. mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
  457. {
  458. int rx_desc = rxq->next_desc_to_proc;
  459. rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
  460. return rxq->descs + rx_desc;
  461. }
  462. /* Tx descriptors helper methods */
  463. /* Update HW with number of TX descriptors to be sent */
  464. static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
  465. struct mvneta_tx_queue *txq,
  466. int pend_desc)
  467. {
  468. u32 val;
  469. /* Only 255 descriptors can be added at once ; Assume caller
  470. * process TX descriptors in quanta less than 256
  471. */
  472. val = pend_desc;
  473. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  474. }
  475. /* Get pointer to next TX descriptor to be processed (send) by HW */
  476. static struct mvneta_tx_desc *
  477. mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
  478. {
  479. int tx_desc = txq->next_desc_to_proc;
  480. txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
  481. return txq->descs + tx_desc;
  482. }
  483. /* Set rxq buf size */
  484. static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
  485. struct mvneta_rx_queue *rxq,
  486. int buf_size)
  487. {
  488. u32 val;
  489. val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
  490. val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
  491. val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
  492. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
  493. }
  494. static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
  495. {
  496. /* phy_addr is set to invalid value for fixed link */
  497. return pp->phyaddr > PHY_MAX_ADDR;
  498. }
  499. /* Start the Ethernet port RX and TX activity */
  500. static void mvneta_port_up(struct mvneta_port *pp)
  501. {
  502. int queue;
  503. u32 q_map;
  504. /* Enable all initialized TXs. */
  505. mvneta_mib_counters_clear(pp);
  506. q_map = 0;
  507. for (queue = 0; queue < txq_number; queue++) {
  508. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  509. if (txq->descs != NULL)
  510. q_map |= (1 << queue);
  511. }
  512. mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
  513. /* Enable all initialized RXQs. */
  514. q_map = 0;
  515. for (queue = 0; queue < rxq_number; queue++) {
  516. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  517. if (rxq->descs != NULL)
  518. q_map |= (1 << queue);
  519. }
  520. mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
  521. }
  522. /* Stop the Ethernet port activity */
  523. static void mvneta_port_down(struct mvneta_port *pp)
  524. {
  525. u32 val;
  526. int count;
  527. /* Stop Rx port activity. Check port Rx activity. */
  528. val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
  529. /* Issue stop command for active channels only */
  530. if (val != 0)
  531. mvreg_write(pp, MVNETA_RXQ_CMD,
  532. val << MVNETA_RXQ_DISABLE_SHIFT);
  533. /* Wait for all Rx activity to terminate. */
  534. count = 0;
  535. do {
  536. if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
  537. netdev_warn(pp->dev,
  538. "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
  539. val);
  540. break;
  541. }
  542. mdelay(1);
  543. val = mvreg_read(pp, MVNETA_RXQ_CMD);
  544. } while (val & 0xff);
  545. /* Stop Tx port activity. Check port Tx activity. Issue stop
  546. * command for active channels only
  547. */
  548. val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
  549. if (val != 0)
  550. mvreg_write(pp, MVNETA_TXQ_CMD,
  551. (val << MVNETA_TXQ_DISABLE_SHIFT));
  552. /* Wait for all Tx activity to terminate. */
  553. count = 0;
  554. do {
  555. if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
  556. netdev_warn(pp->dev,
  557. "TIMEOUT for TX stopped status=0x%08x\n",
  558. val);
  559. break;
  560. }
  561. mdelay(1);
  562. /* Check TX Command reg that all Txqs are stopped */
  563. val = mvreg_read(pp, MVNETA_TXQ_CMD);
  564. } while (val & 0xff);
  565. /* Double check to verify that TX FIFO is empty */
  566. count = 0;
  567. do {
  568. if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
  569. netdev_warn(pp->dev,
  570. "TX FIFO empty timeout status=0x08%x\n",
  571. val);
  572. break;
  573. }
  574. mdelay(1);
  575. val = mvreg_read(pp, MVNETA_PORT_STATUS);
  576. } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
  577. (val & MVNETA_TX_IN_PRGRS));
  578. udelay(200);
  579. }
  580. /* Enable the port by setting the port enable bit of the MAC control register */
  581. static void mvneta_port_enable(struct mvneta_port *pp)
  582. {
  583. u32 val;
  584. /* Enable port */
  585. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  586. val |= MVNETA_GMAC0_PORT_ENABLE;
  587. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  588. }
  589. /* Disable the port and wait for about 200 usec before retuning */
  590. static void mvneta_port_disable(struct mvneta_port *pp)
  591. {
  592. u32 val;
  593. /* Reset the Enable bit in the Serial Control Register */
  594. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  595. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  596. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  597. udelay(200);
  598. }
  599. /* Multicast tables methods */
  600. /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
  601. static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
  602. {
  603. int offset;
  604. u32 val;
  605. if (queue == -1) {
  606. val = 0;
  607. } else {
  608. val = 0x1 | (queue << 1);
  609. val |= (val << 24) | (val << 16) | (val << 8);
  610. }
  611. for (offset = 0; offset <= 0xc; offset += 4)
  612. mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
  613. }
  614. /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
  615. static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
  616. {
  617. int offset;
  618. u32 val;
  619. if (queue == -1) {
  620. val = 0;
  621. } else {
  622. val = 0x1 | (queue << 1);
  623. val |= (val << 24) | (val << 16) | (val << 8);
  624. }
  625. for (offset = 0; offset <= 0xfc; offset += 4)
  626. mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
  627. }
  628. /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
  629. static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
  630. {
  631. int offset;
  632. u32 val;
  633. if (queue == -1) {
  634. memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
  635. val = 0;
  636. } else {
  637. memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
  638. val = 0x1 | (queue << 1);
  639. val |= (val << 24) | (val << 16) | (val << 8);
  640. }
  641. for (offset = 0; offset <= 0xfc; offset += 4)
  642. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  643. }
  644. /* This method sets defaults to the NETA port:
  645. * Clears interrupt Cause and Mask registers.
  646. * Clears all MAC tables.
  647. * Sets defaults to all registers.
  648. * Resets RX and TX descriptor rings.
  649. * Resets PHY.
  650. * This method can be called after mvneta_port_down() to return the port
  651. * settings to defaults.
  652. */
  653. static void mvneta_defaults_set(struct mvneta_port *pp)
  654. {
  655. int cpu;
  656. int queue;
  657. u32 val;
  658. /* Clear all Cause registers */
  659. mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
  660. mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
  661. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  662. /* Mask all interrupts */
  663. mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
  664. mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
  665. mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
  666. mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
  667. /* Enable MBUS Retry bit16 */
  668. mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
  669. /* Set CPU queue access map - all CPUs have access to all RX
  670. * queues and to all TX queues
  671. */
  672. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
  673. mvreg_write(pp, MVNETA_CPU_MAP(cpu),
  674. (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
  675. MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
  676. /* Reset RX and TX DMAs */
  677. mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
  678. mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
  679. /* Disable Legacy WRR, Disable EJP, Release from reset */
  680. mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
  681. for (queue = 0; queue < txq_number; queue++) {
  682. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
  683. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
  684. }
  685. mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
  686. mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
  687. /* Set Port Acceleration Mode */
  688. val = MVNETA_ACC_MODE_EXT;
  689. mvreg_write(pp, MVNETA_ACC_MODE, val);
  690. /* Update val of portCfg register accordingly with all RxQueue types */
  691. val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
  692. mvreg_write(pp, MVNETA_PORT_CONFIG, val);
  693. val = 0;
  694. mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
  695. mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
  696. /* Build PORT_SDMA_CONFIG_REG */
  697. val = 0;
  698. /* Default burst size */
  699. val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  700. val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  701. val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
  702. /* Assign port SDMA configuration */
  703. mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
  704. /* Enable PHY polling in hardware if not in fixed-link mode */
  705. if (!mvneta_port_is_fixed_link(pp)) {
  706. val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
  707. val |= MVNETA_PHY_POLLING_ENABLE;
  708. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  709. }
  710. mvneta_set_ucast_table(pp, -1);
  711. mvneta_set_special_mcast_table(pp, -1);
  712. mvneta_set_other_mcast_table(pp, -1);
  713. }
  714. /* Set unicast address */
  715. static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
  716. int queue)
  717. {
  718. unsigned int unicast_reg;
  719. unsigned int tbl_offset;
  720. unsigned int reg_offset;
  721. /* Locate the Unicast table entry */
  722. last_nibble = (0xf & last_nibble);
  723. /* offset from unicast tbl base */
  724. tbl_offset = (last_nibble / 4) * 4;
  725. /* offset within the above reg */
  726. reg_offset = last_nibble % 4;
  727. unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
  728. if (queue == -1) {
  729. /* Clear accepts frame bit at specified unicast DA tbl entry */
  730. unicast_reg &= ~(0xff << (8 * reg_offset));
  731. } else {
  732. unicast_reg &= ~(0xff << (8 * reg_offset));
  733. unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
  734. }
  735. mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
  736. }
  737. /* Set mac address */
  738. static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
  739. int queue)
  740. {
  741. unsigned int mac_h;
  742. unsigned int mac_l;
  743. if (queue != -1) {
  744. mac_l = (addr[4] << 8) | (addr[5]);
  745. mac_h = (addr[0] << 24) | (addr[1] << 16) |
  746. (addr[2] << 8) | (addr[3] << 0);
  747. mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
  748. mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
  749. }
  750. /* Accept frames of this address */
  751. mvneta_set_ucast_addr(pp, addr[5], queue);
  752. }
  753. static int mvneta_write_hwaddr(struct udevice *dev)
  754. {
  755. mvneta_mac_addr_set(dev_get_priv(dev),
  756. ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
  757. rxq_def);
  758. return 0;
  759. }
  760. /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
  761. static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
  762. u32 phys_addr, u32 cookie)
  763. {
  764. rx_desc->buf_cookie = cookie;
  765. rx_desc->buf_phys_addr = phys_addr;
  766. }
  767. /* Decrement sent descriptors counter */
  768. static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
  769. struct mvneta_tx_queue *txq,
  770. int sent_desc)
  771. {
  772. u32 val;
  773. /* Only 255 TX descriptors can be updated at once */
  774. while (sent_desc > 0xff) {
  775. val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
  776. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  777. sent_desc = sent_desc - 0xff;
  778. }
  779. val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
  780. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  781. }
  782. /* Get number of TX descriptors already sent by HW */
  783. static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
  784. struct mvneta_tx_queue *txq)
  785. {
  786. u32 val;
  787. int sent_desc;
  788. val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
  789. sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
  790. MVNETA_TXQ_SENT_DESC_SHIFT;
  791. return sent_desc;
  792. }
  793. /* Display more error info */
  794. static void mvneta_rx_error(struct mvneta_port *pp,
  795. struct mvneta_rx_desc *rx_desc)
  796. {
  797. u32 status = rx_desc->status;
  798. if (!mvneta_rxq_desc_is_first_last(status)) {
  799. netdev_err(pp->dev,
  800. "bad rx status %08x (buffer oversize), size=%d\n",
  801. status, rx_desc->data_size);
  802. return;
  803. }
  804. switch (status & MVNETA_RXD_ERR_CODE_MASK) {
  805. case MVNETA_RXD_ERR_CRC:
  806. netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
  807. status, rx_desc->data_size);
  808. break;
  809. case MVNETA_RXD_ERR_OVERRUN:
  810. netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
  811. status, rx_desc->data_size);
  812. break;
  813. case MVNETA_RXD_ERR_LEN:
  814. netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
  815. status, rx_desc->data_size);
  816. break;
  817. case MVNETA_RXD_ERR_RESOURCE:
  818. netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
  819. status, rx_desc->data_size);
  820. break;
  821. }
  822. }
  823. static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
  824. int rxq)
  825. {
  826. return &pp->rxqs[rxq];
  827. }
  828. /* Drop packets received by the RXQ and free buffers */
  829. static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
  830. struct mvneta_rx_queue *rxq)
  831. {
  832. int rx_done;
  833. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  834. if (rx_done)
  835. mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
  836. }
  837. /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
  838. static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
  839. int num)
  840. {
  841. int i;
  842. for (i = 0; i < num; i++) {
  843. u32 addr;
  844. /* U-Boot special: Fill in the rx buffer addresses */
  845. addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
  846. mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
  847. }
  848. /* Add this number of RX descriptors as non occupied (ready to
  849. * get packets)
  850. */
  851. mvneta_rxq_non_occup_desc_add(pp, rxq, i);
  852. return 0;
  853. }
  854. /* Rx/Tx queue initialization/cleanup methods */
  855. /* Create a specified RX queue */
  856. static int mvneta_rxq_init(struct mvneta_port *pp,
  857. struct mvneta_rx_queue *rxq)
  858. {
  859. rxq->size = pp->rx_ring_size;
  860. /* Allocate memory for RX descriptors */
  861. rxq->descs_phys = (dma_addr_t)rxq->descs;
  862. if (rxq->descs == NULL)
  863. return -ENOMEM;
  864. WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
  865. rxq->last_desc = rxq->size - 1;
  866. /* Set Rx descriptors queue starting address */
  867. mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
  868. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
  869. /* Fill RXQ with buffers from RX pool */
  870. mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
  871. mvneta_rxq_fill(pp, rxq, rxq->size);
  872. return 0;
  873. }
  874. /* Cleanup Rx queue */
  875. static void mvneta_rxq_deinit(struct mvneta_port *pp,
  876. struct mvneta_rx_queue *rxq)
  877. {
  878. mvneta_rxq_drop_pkts(pp, rxq);
  879. rxq->descs = NULL;
  880. rxq->last_desc = 0;
  881. rxq->next_desc_to_proc = 0;
  882. rxq->descs_phys = 0;
  883. }
  884. /* Create and initialize a tx queue */
  885. static int mvneta_txq_init(struct mvneta_port *pp,
  886. struct mvneta_tx_queue *txq)
  887. {
  888. txq->size = pp->tx_ring_size;
  889. /* Allocate memory for TX descriptors */
  890. txq->descs_phys = (dma_addr_t)txq->descs;
  891. if (txq->descs == NULL)
  892. return -ENOMEM;
  893. WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
  894. txq->last_desc = txq->size - 1;
  895. /* Set maximum bandwidth for enabled TXQs */
  896. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
  897. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
  898. /* Set Tx descriptors queue starting address */
  899. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
  900. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
  901. return 0;
  902. }
  903. /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
  904. static void mvneta_txq_deinit(struct mvneta_port *pp,
  905. struct mvneta_tx_queue *txq)
  906. {
  907. txq->descs = NULL;
  908. txq->last_desc = 0;
  909. txq->next_desc_to_proc = 0;
  910. txq->descs_phys = 0;
  911. /* Set minimum bandwidth for disabled TXQs */
  912. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
  913. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
  914. /* Set Tx descriptors queue starting address and size */
  915. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
  916. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
  917. }
  918. /* Cleanup all Tx queues */
  919. static void mvneta_cleanup_txqs(struct mvneta_port *pp)
  920. {
  921. int queue;
  922. for (queue = 0; queue < txq_number; queue++)
  923. mvneta_txq_deinit(pp, &pp->txqs[queue]);
  924. }
  925. /* Cleanup all Rx queues */
  926. static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
  927. {
  928. int queue;
  929. for (queue = 0; queue < rxq_number; queue++)
  930. mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
  931. }
  932. /* Init all Rx queues */
  933. static int mvneta_setup_rxqs(struct mvneta_port *pp)
  934. {
  935. int queue;
  936. for (queue = 0; queue < rxq_number; queue++) {
  937. int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
  938. if (err) {
  939. netdev_err(pp->dev, "%s: can't create rxq=%d\n",
  940. __func__, queue);
  941. mvneta_cleanup_rxqs(pp);
  942. return err;
  943. }
  944. }
  945. return 0;
  946. }
  947. /* Init all tx queues */
  948. static int mvneta_setup_txqs(struct mvneta_port *pp)
  949. {
  950. int queue;
  951. for (queue = 0; queue < txq_number; queue++) {
  952. int err = mvneta_txq_init(pp, &pp->txqs[queue]);
  953. if (err) {
  954. netdev_err(pp->dev, "%s: can't create txq=%d\n",
  955. __func__, queue);
  956. mvneta_cleanup_txqs(pp);
  957. return err;
  958. }
  959. }
  960. return 0;
  961. }
  962. static void mvneta_start_dev(struct mvneta_port *pp)
  963. {
  964. /* start the Rx/Tx activity */
  965. mvneta_port_enable(pp);
  966. }
  967. static void mvneta_adjust_link(struct udevice *dev)
  968. {
  969. struct mvneta_port *pp = dev_get_priv(dev);
  970. struct phy_device *phydev = pp->phydev;
  971. int status_change = 0;
  972. if (mvneta_port_is_fixed_link(pp)) {
  973. debug("Using fixed link, skip link adjust\n");
  974. return;
  975. }
  976. if (phydev->link) {
  977. if ((pp->speed != phydev->speed) ||
  978. (pp->duplex != phydev->duplex)) {
  979. u32 val;
  980. val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  981. val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  982. MVNETA_GMAC_CONFIG_GMII_SPEED |
  983. MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  984. MVNETA_GMAC_AN_SPEED_EN |
  985. MVNETA_GMAC_AN_DUPLEX_EN);
  986. if (phydev->duplex)
  987. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  988. if (phydev->speed == SPEED_1000)
  989. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  990. else
  991. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  992. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  993. pp->duplex = phydev->duplex;
  994. pp->speed = phydev->speed;
  995. }
  996. }
  997. if (phydev->link != pp->link) {
  998. if (!phydev->link) {
  999. pp->duplex = -1;
  1000. pp->speed = 0;
  1001. }
  1002. pp->link = phydev->link;
  1003. status_change = 1;
  1004. }
  1005. if (status_change) {
  1006. if (phydev->link) {
  1007. u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  1008. val |= (MVNETA_GMAC_FORCE_LINK_PASS |
  1009. MVNETA_GMAC_FORCE_LINK_DOWN);
  1010. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1011. mvneta_port_up(pp);
  1012. } else {
  1013. mvneta_port_down(pp);
  1014. }
  1015. }
  1016. }
  1017. static int mvneta_open(struct udevice *dev)
  1018. {
  1019. struct mvneta_port *pp = dev_get_priv(dev);
  1020. int ret;
  1021. ret = mvneta_setup_rxqs(pp);
  1022. if (ret)
  1023. return ret;
  1024. ret = mvneta_setup_txqs(pp);
  1025. if (ret)
  1026. return ret;
  1027. mvneta_adjust_link(dev);
  1028. mvneta_start_dev(pp);
  1029. return 0;
  1030. }
  1031. /* Initialize hw */
  1032. static int mvneta_init2(struct mvneta_port *pp)
  1033. {
  1034. int queue;
  1035. /* Disable port */
  1036. mvneta_port_disable(pp);
  1037. /* Set port default values */
  1038. mvneta_defaults_set(pp);
  1039. pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
  1040. GFP_KERNEL);
  1041. if (!pp->txqs)
  1042. return -ENOMEM;
  1043. /* U-Boot special: use preallocated area */
  1044. pp->txqs[0].descs = buffer_loc.tx_descs;
  1045. /* Initialize TX descriptor rings */
  1046. for (queue = 0; queue < txq_number; queue++) {
  1047. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  1048. txq->id = queue;
  1049. txq->size = pp->tx_ring_size;
  1050. }
  1051. pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
  1052. GFP_KERNEL);
  1053. if (!pp->rxqs) {
  1054. kfree(pp->txqs);
  1055. return -ENOMEM;
  1056. }
  1057. /* U-Boot special: use preallocated area */
  1058. pp->rxqs[0].descs = buffer_loc.rx_descs;
  1059. /* Create Rx descriptor rings */
  1060. for (queue = 0; queue < rxq_number; queue++) {
  1061. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  1062. rxq->id = queue;
  1063. rxq->size = pp->rx_ring_size;
  1064. }
  1065. return 0;
  1066. }
  1067. /* platform glue : initialize decoding windows */
  1068. /*
  1069. * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
  1070. * First layer is: GbE Address window that resides inside the GBE unit,
  1071. * Second layer is: Fabric address window which is located in the NIC400
  1072. * (South Fabric).
  1073. * To simplify the address decode configuration for Armada3700, we bypass the
  1074. * first layer of GBE decode window by setting the first window to 4GB.
  1075. */
  1076. static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
  1077. {
  1078. /*
  1079. * Set window size to 4GB, to bypass GBE address decode, leave the
  1080. * work to MBUS decode window
  1081. */
  1082. mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
  1083. /* Enable GBE address decode window 0 by set bit 0 to 0 */
  1084. clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
  1085. MVNETA_BASE_ADDR_ENABLE_BIT);
  1086. /* Set GBE address decode window 0 to full Access (read or write) */
  1087. setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
  1088. MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
  1089. }
  1090. static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
  1091. {
  1092. const struct mbus_dram_target_info *dram;
  1093. u32 win_enable;
  1094. u32 win_protect;
  1095. int i;
  1096. dram = mvebu_mbus_dram_info();
  1097. for (i = 0; i < 6; i++) {
  1098. mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
  1099. mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
  1100. if (i < 4)
  1101. mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
  1102. }
  1103. win_enable = 0x3f;
  1104. win_protect = 0;
  1105. for (i = 0; i < dram->num_cs; i++) {
  1106. const struct mbus_dram_window *cs = dram->cs + i;
  1107. mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
  1108. (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
  1109. mvreg_write(pp, MVNETA_WIN_SIZE(i),
  1110. (cs->size - 1) & 0xffff0000);
  1111. win_enable &= ~(1 << i);
  1112. win_protect |= 3 << (2 * i);
  1113. }
  1114. mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
  1115. }
  1116. /* Power up the port */
  1117. static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
  1118. {
  1119. u32 ctrl;
  1120. /* MAC Cause register should be cleared */
  1121. mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
  1122. ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  1123. /* Even though it might look weird, when we're configured in
  1124. * SGMII or QSGMII mode, the RGMII bit needs to be set.
  1125. */
  1126. switch (phy_mode) {
  1127. case PHY_INTERFACE_MODE_QSGMII:
  1128. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
  1129. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1130. break;
  1131. case PHY_INTERFACE_MODE_SGMII:
  1132. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
  1133. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1134. break;
  1135. case PHY_INTERFACE_MODE_RGMII:
  1136. case PHY_INTERFACE_MODE_RGMII_ID:
  1137. ctrl |= MVNETA_GMAC2_PORT_RGMII;
  1138. break;
  1139. default:
  1140. return -EINVAL;
  1141. }
  1142. /* Cancel Port Reset */
  1143. ctrl &= ~MVNETA_GMAC2_PORT_RESET;
  1144. mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
  1145. while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
  1146. MVNETA_GMAC2_PORT_RESET) != 0)
  1147. continue;
  1148. return 0;
  1149. }
  1150. /* Device initialization routine */
  1151. static int mvneta_init(struct udevice *dev)
  1152. {
  1153. struct eth_pdata *pdata = dev_get_platdata(dev);
  1154. struct mvneta_port *pp = dev_get_priv(dev);
  1155. int err;
  1156. pp->tx_ring_size = MVNETA_MAX_TXD;
  1157. pp->rx_ring_size = MVNETA_MAX_RXD;
  1158. err = mvneta_init2(pp);
  1159. if (err < 0) {
  1160. dev_err(&pdev->dev, "can't init eth hal\n");
  1161. return err;
  1162. }
  1163. mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
  1164. err = mvneta_port_power_up(pp, pp->phy_interface);
  1165. if (err < 0) {
  1166. dev_err(&pdev->dev, "can't power up port\n");
  1167. return err;
  1168. }
  1169. /* Call open() now as it needs to be done before runing send() */
  1170. mvneta_open(dev);
  1171. return 0;
  1172. }
  1173. /* U-Boot only functions follow here */
  1174. /* SMI / MDIO functions */
  1175. static int smi_wait_ready(struct mvneta_port *pp)
  1176. {
  1177. u32 timeout = MVNETA_SMI_TIMEOUT;
  1178. u32 smi_reg;
  1179. /* wait till the SMI is not busy */
  1180. do {
  1181. /* read smi register */
  1182. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1183. if (timeout-- == 0) {
  1184. printf("Error: SMI busy timeout\n");
  1185. return -EFAULT;
  1186. }
  1187. } while (smi_reg & MVNETA_SMI_BUSY);
  1188. return 0;
  1189. }
  1190. /*
  1191. * mvneta_mdio_read - miiphy_read callback function.
  1192. *
  1193. * Returns 16bit phy register value, or 0xffff on error
  1194. */
  1195. static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  1196. {
  1197. struct mvneta_port *pp = bus->priv;
  1198. u32 smi_reg;
  1199. u32 timeout;
  1200. /* check parameters */
  1201. if (addr > MVNETA_PHY_ADDR_MASK) {
  1202. printf("Error: Invalid PHY address %d\n", addr);
  1203. return -EFAULT;
  1204. }
  1205. if (reg > MVNETA_PHY_REG_MASK) {
  1206. printf("Err: Invalid register offset %d\n", reg);
  1207. return -EFAULT;
  1208. }
  1209. /* wait till the SMI is not busy */
  1210. if (smi_wait_ready(pp) < 0)
  1211. return -EFAULT;
  1212. /* fill the phy address and regiser offset and read opcode */
  1213. smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1214. | (reg << MVNETA_SMI_REG_ADDR_OFFS)
  1215. | MVNETA_SMI_OPCODE_READ;
  1216. /* write the smi register */
  1217. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1218. /* wait till read value is ready */
  1219. timeout = MVNETA_SMI_TIMEOUT;
  1220. do {
  1221. /* read smi register */
  1222. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1223. if (timeout-- == 0) {
  1224. printf("Err: SMI read ready timeout\n");
  1225. return -EFAULT;
  1226. }
  1227. } while (!(smi_reg & MVNETA_SMI_READ_VALID));
  1228. /* Wait for the data to update in the SMI register */
  1229. for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
  1230. ;
  1231. return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
  1232. }
  1233. /*
  1234. * mvneta_mdio_write - miiphy_write callback function.
  1235. *
  1236. * Returns 0 if write succeed, -EINVAL on bad parameters
  1237. * -ETIME on timeout
  1238. */
  1239. static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  1240. u16 value)
  1241. {
  1242. struct mvneta_port *pp = bus->priv;
  1243. u32 smi_reg;
  1244. /* check parameters */
  1245. if (addr > MVNETA_PHY_ADDR_MASK) {
  1246. printf("Error: Invalid PHY address %d\n", addr);
  1247. return -EFAULT;
  1248. }
  1249. if (reg > MVNETA_PHY_REG_MASK) {
  1250. printf("Err: Invalid register offset %d\n", reg);
  1251. return -EFAULT;
  1252. }
  1253. /* wait till the SMI is not busy */
  1254. if (smi_wait_ready(pp) < 0)
  1255. return -EFAULT;
  1256. /* fill the phy addr and reg offset and write opcode and data */
  1257. smi_reg = value << MVNETA_SMI_DATA_OFFS;
  1258. smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1259. | (reg << MVNETA_SMI_REG_ADDR_OFFS);
  1260. smi_reg &= ~MVNETA_SMI_OPCODE_READ;
  1261. /* write the smi register */
  1262. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1263. return 0;
  1264. }
  1265. static int mvneta_start(struct udevice *dev)
  1266. {
  1267. struct mvneta_port *pp = dev_get_priv(dev);
  1268. struct phy_device *phydev;
  1269. mvneta_port_power_up(pp, pp->phy_interface);
  1270. if (!pp->init || pp->link == 0) {
  1271. if (mvneta_port_is_fixed_link(pp)) {
  1272. u32 val;
  1273. pp->init = 1;
  1274. pp->link = 1;
  1275. mvneta_init(dev);
  1276. val = MVNETA_GMAC_FORCE_LINK_UP |
  1277. MVNETA_GMAC_IB_BYPASS_AN_EN |
  1278. MVNETA_GMAC_SET_FC_EN |
  1279. MVNETA_GMAC_ADVERT_FC_EN |
  1280. MVNETA_GMAC_SAMPLE_TX_CFG_EN;
  1281. if (pp->duplex)
  1282. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  1283. if (pp->speed == SPEED_1000)
  1284. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  1285. else if (pp->speed == SPEED_100)
  1286. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  1287. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1288. } else {
  1289. /* Set phy address of the port */
  1290. mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
  1291. phydev = phy_connect(pp->bus, pp->phyaddr, dev,
  1292. pp->phy_interface);
  1293. if (!phydev) {
  1294. printf("phy_connect failed\n");
  1295. return -ENODEV;
  1296. }
  1297. pp->phydev = phydev;
  1298. phy_config(phydev);
  1299. phy_startup(phydev);
  1300. if (!phydev->link) {
  1301. printf("%s: No link.\n", phydev->dev->name);
  1302. return -1;
  1303. }
  1304. /* Full init on first call */
  1305. mvneta_init(dev);
  1306. pp->init = 1;
  1307. return 0;
  1308. }
  1309. }
  1310. /* Upon all following calls, this is enough */
  1311. mvneta_port_up(pp);
  1312. mvneta_port_enable(pp);
  1313. return 0;
  1314. }
  1315. static int mvneta_send(struct udevice *dev, void *packet, int length)
  1316. {
  1317. struct mvneta_port *pp = dev_get_priv(dev);
  1318. struct mvneta_tx_queue *txq = &pp->txqs[0];
  1319. struct mvneta_tx_desc *tx_desc;
  1320. int sent_desc;
  1321. u32 timeout = 0;
  1322. /* Get a descriptor for the first part of the packet */
  1323. tx_desc = mvneta_txq_next_desc_get(txq);
  1324. tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
  1325. tx_desc->data_size = length;
  1326. flush_dcache_range((ulong)packet,
  1327. (ulong)packet + ALIGN(length, PKTALIGN));
  1328. /* First and Last descriptor */
  1329. tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
  1330. mvneta_txq_pend_desc_add(pp, txq, 1);
  1331. /* Wait for packet to be sent (queue might help with speed here) */
  1332. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1333. while (!sent_desc) {
  1334. if (timeout++ > 10000) {
  1335. printf("timeout: packet not sent\n");
  1336. return -1;
  1337. }
  1338. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1339. }
  1340. /* txDone has increased - hw sent packet */
  1341. mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
  1342. return 0;
  1343. }
  1344. static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
  1345. {
  1346. struct mvneta_port *pp = dev_get_priv(dev);
  1347. int rx_done;
  1348. struct mvneta_rx_queue *rxq;
  1349. int rx_bytes = 0;
  1350. /* get rx queue */
  1351. rxq = mvneta_rxq_handle_get(pp, rxq_def);
  1352. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  1353. if (rx_done) {
  1354. struct mvneta_rx_desc *rx_desc;
  1355. unsigned char *data;
  1356. u32 rx_status;
  1357. /*
  1358. * No cache invalidation needed here, since the desc's are
  1359. * located in a uncached memory region
  1360. */
  1361. rx_desc = mvneta_rxq_next_desc_get(rxq);
  1362. rx_status = rx_desc->status;
  1363. if (!mvneta_rxq_desc_is_first_last(rx_status) ||
  1364. (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
  1365. mvneta_rx_error(pp, rx_desc);
  1366. /* leave the descriptor untouched */
  1367. return -EIO;
  1368. }
  1369. /* 2 bytes for marvell header. 4 bytes for crc */
  1370. rx_bytes = rx_desc->data_size - 6;
  1371. /* give packet to stack - skip on first 2 bytes */
  1372. data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
  1373. /*
  1374. * No cache invalidation needed here, since the rx_buffer's are
  1375. * located in a uncached memory region
  1376. */
  1377. *packetp = data;
  1378. /*
  1379. * Only mark one descriptor as free
  1380. * since only one was processed
  1381. */
  1382. mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
  1383. }
  1384. return rx_bytes;
  1385. }
  1386. static int mvneta_probe(struct udevice *dev)
  1387. {
  1388. struct eth_pdata *pdata = dev_get_platdata(dev);
  1389. struct mvneta_port *pp = dev_get_priv(dev);
  1390. void *blob = (void *)gd->fdt_blob;
  1391. int node = dev_of_offset(dev);
  1392. struct mii_dev *bus;
  1393. unsigned long addr;
  1394. void *bd_space;
  1395. int ret;
  1396. int fl_node;
  1397. /*
  1398. * Allocate buffer area for descs and rx_buffers. This is only
  1399. * done once for all interfaces. As only one interface can
  1400. * be active. Make this area DMA safe by disabling the D-cache
  1401. */
  1402. if (!buffer_loc.tx_descs) {
  1403. u32 size;
  1404. /* Align buffer area for descs and rx_buffers to 1MiB */
  1405. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  1406. flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
  1407. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
  1408. DCACHE_OFF);
  1409. buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
  1410. size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
  1411. ARCH_DMA_MINALIGN);
  1412. memset(buffer_loc.tx_descs, 0, size);
  1413. buffer_loc.rx_descs = (struct mvneta_rx_desc *)
  1414. ((phys_addr_t)bd_space + size);
  1415. size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
  1416. ARCH_DMA_MINALIGN);
  1417. buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
  1418. }
  1419. pp->base = (void __iomem *)pdata->iobase;
  1420. /* Configure MBUS address windows */
  1421. if (device_is_compatible(dev, "marvell,armada-3700-neta"))
  1422. mvneta_bypass_mbus_windows(pp);
  1423. else
  1424. mvneta_conf_mbus_windows(pp);
  1425. /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
  1426. pp->phy_interface = pdata->phy_interface;
  1427. /* fetch 'fixed-link' property from 'neta' node */
  1428. fl_node = fdt_subnode_offset(blob, node, "fixed-link");
  1429. if (fl_node != -FDT_ERR_NOTFOUND) {
  1430. /* set phy_addr to invalid value for fixed link */
  1431. pp->phyaddr = PHY_MAX_ADDR + 1;
  1432. pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  1433. pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  1434. } else {
  1435. /* Now read phyaddr from DT */
  1436. addr = fdtdec_get_int(blob, node, "phy", 0);
  1437. addr = fdt_node_offset_by_phandle(blob, addr);
  1438. pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  1439. }
  1440. bus = mdio_alloc();
  1441. if (!bus) {
  1442. printf("Failed to allocate MDIO bus\n");
  1443. return -ENOMEM;
  1444. }
  1445. bus->read = mvneta_mdio_read;
  1446. bus->write = mvneta_mdio_write;
  1447. snprintf(bus->name, sizeof(bus->name), dev->name);
  1448. bus->priv = (void *)pp;
  1449. pp->bus = bus;
  1450. ret = mdio_register(bus);
  1451. if (ret)
  1452. return ret;
  1453. #if CONFIG_IS_ENABLED(DM_GPIO)
  1454. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1455. &pp->phy_reset_gpio, GPIOD_IS_OUT);
  1456. if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
  1457. dm_gpio_set_value(&pp->phy_reset_gpio, 1);
  1458. mdelay(10);
  1459. dm_gpio_set_value(&pp->phy_reset_gpio, 0);
  1460. }
  1461. #endif
  1462. return board_network_enable(bus);
  1463. }
  1464. static void mvneta_stop(struct udevice *dev)
  1465. {
  1466. struct mvneta_port *pp = dev_get_priv(dev);
  1467. mvneta_port_down(pp);
  1468. mvneta_port_disable(pp);
  1469. }
  1470. static const struct eth_ops mvneta_ops = {
  1471. .start = mvneta_start,
  1472. .send = mvneta_send,
  1473. .recv = mvneta_recv,
  1474. .stop = mvneta_stop,
  1475. .write_hwaddr = mvneta_write_hwaddr,
  1476. };
  1477. static int mvneta_ofdata_to_platdata(struct udevice *dev)
  1478. {
  1479. struct eth_pdata *pdata = dev_get_platdata(dev);
  1480. const char *phy_mode;
  1481. pdata->iobase = devfdt_get_addr(dev);
  1482. /* Get phy-mode / phy_interface from DT */
  1483. pdata->phy_interface = -1;
  1484. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1485. NULL);
  1486. if (phy_mode)
  1487. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1488. if (pdata->phy_interface == -1) {
  1489. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1490. return -EINVAL;
  1491. }
  1492. return 0;
  1493. }
  1494. static const struct udevice_id mvneta_ids[] = {
  1495. { .compatible = "marvell,armada-370-neta" },
  1496. { .compatible = "marvell,armada-xp-neta" },
  1497. { .compatible = "marvell,armada-3700-neta" },
  1498. { }
  1499. };
  1500. U_BOOT_DRIVER(mvneta) = {
  1501. .name = "mvneta",
  1502. .id = UCLASS_ETH,
  1503. .of_match = mvneta_ids,
  1504. .ofdata_to_platdata = mvneta_ofdata_to_platdata,
  1505. .probe = mvneta_probe,
  1506. .ops = &mvneta_ops,
  1507. .priv_auto_alloc_size = sizeof(struct mvneta_port),
  1508. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1509. };