qbman_sys.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor
  4. */
  5. /* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
  6. * driver. They are only included via qbman_private.h, which is itself a
  7. * platform-independent file and is included by all the other driver source.
  8. *
  9. * qbman_sys_decl.h is included prior to all other declarations and logic, and
  10. * it exists to provide compatibility with any linux interfaces our
  11. * single-source driver code is dependent on (eg. kmalloc). Ie. this file
  12. * provides linux compatibility.
  13. *
  14. * This qbman_sys.h header, on the other hand, is included *after* any common
  15. * and platform-neutral declarations and logic in qbman_private.h, and exists to
  16. * implement any platform-specific logic of the qbman driver itself. Ie. it is
  17. * *not* to provide linux compatibility.
  18. */
  19. /* Trace the 3 different classes of read/write access to QBMan. #undef as
  20. * required. */
  21. #include <linux/bug.h>
  22. #undef QBMAN_CCSR_TRACE
  23. #undef QBMAN_CINH_TRACE
  24. #undef QBMAN_CENA_TRACE
  25. /* Temporarily define this to get around the fact that cache enabled mapping is
  26. * not working right now. Will remove this after uboot could map the cache
  27. * enabled portal memory.
  28. */
  29. #define QBMAN_CINH_ONLY
  30. static inline void word_copy(void *d, const void *s, unsigned int cnt)
  31. {
  32. uint32_t *dd = d;
  33. const uint32_t *ss = s;
  34. while (cnt--)
  35. *(dd++) = *(ss++);
  36. }
  37. /* Currently, the CENA support code expects each 32-bit word to be written in
  38. * host order, and these are converted to hardware (little-endian) order on
  39. * command submission. However, 64-bit quantities are must be written (and read)
  40. * as two 32-bit words with the least-significant word first, irrespective of
  41. * host endianness. */
  42. static inline void u64_to_le32_copy(void *d, const uint64_t *s,
  43. unsigned int cnt)
  44. {
  45. uint32_t *dd = d;
  46. const uint32_t *ss = (const uint32_t *)s;
  47. while (cnt--) {
  48. /* TBD: the toolchain was choking on the use of 64-bit types up
  49. * until recently so this works entirely with 32-bit variables.
  50. * When 64-bit types become usable again, investigate better
  51. * ways of doing this. */
  52. #if defined(__BIG_ENDIAN)
  53. *(dd++) = ss[1];
  54. *(dd++) = ss[0];
  55. ss += 2;
  56. #else
  57. *(dd++) = *(ss++);
  58. *(dd++) = *(ss++);
  59. #endif
  60. }
  61. }
  62. static inline void u64_from_le32_copy(uint64_t *d, const void *s,
  63. unsigned int cnt)
  64. {
  65. const uint32_t *ss = s;
  66. uint32_t *dd = (uint32_t *)d;
  67. while (cnt--) {
  68. #if defined(__BIG_ENDIAN)
  69. dd[1] = *(ss++);
  70. dd[0] = *(ss++);
  71. dd += 2;
  72. #else
  73. *(dd++) = *(ss++);
  74. *(dd++) = *(ss++);
  75. #endif
  76. }
  77. }
  78. /* Convert a host-native 32bit value into little endian */
  79. #if defined(__BIG_ENDIAN)
  80. static inline uint32_t make_le32(uint32_t val)
  81. {
  82. return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
  83. ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
  84. }
  85. #else
  86. #define make_le32(val) (val)
  87. #endif
  88. static inline void make_le32_n(uint32_t *val, unsigned int num)
  89. {
  90. while (num--) {
  91. *val = make_le32(*val);
  92. val++;
  93. }
  94. }
  95. /******************/
  96. /* Portal access */
  97. /******************/
  98. struct qbman_swp_sys {
  99. /* On GPP, the sys support for qbman_swp is here. The CENA region isi
  100. * not an mmap() of the real portal registers, but an allocated
  101. * place-holder, because the actual writes/reads to/from the portal are
  102. * marshalled from these allocated areas using QBMan's "MC access
  103. * registers". CINH accesses are atomic so there's no need for a
  104. * place-holder. */
  105. void *cena;
  106. void __iomem *addr_cena;
  107. void __iomem *addr_cinh;
  108. };
  109. /* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
  110. * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
  111. * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
  112. * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
  113. * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
  114. * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
  115. */
  116. static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
  117. uint32_t val)
  118. {
  119. __raw_writel(val, s->addr_cinh + offset);
  120. #ifdef QBMAN_CINH_TRACE
  121. pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n",
  122. s->addr_cinh, offset, val);
  123. #endif
  124. }
  125. static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
  126. {
  127. uint32_t reg = __raw_readl(s->addr_cinh + offset);
  128. #ifdef QBMAN_CINH_TRACE
  129. pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n",
  130. s->addr_cinh, offset, reg);
  131. #endif
  132. return reg;
  133. }
  134. static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
  135. uint32_t offset)
  136. {
  137. void *shadow = s->cena + offset;
  138. #ifdef QBMAN_CENA_TRACE
  139. pr_info("qbman_cena_write_start(%p:0x%03x) %p\n",
  140. s->addr_cena, offset, shadow);
  141. #endif
  142. BUG_ON(offset & 63);
  143. dcbz(shadow);
  144. return shadow;
  145. }
  146. static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
  147. uint32_t offset, void *cmd)
  148. {
  149. const uint32_t *shadow = cmd;
  150. int loop;
  151. #ifdef QBMAN_CENA_TRACE
  152. pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n",
  153. s->addr_cena, offset, shadow);
  154. hexdump(cmd, 64);
  155. #endif
  156. for (loop = 15; loop >= 0; loop--)
  157. #ifdef QBMAN_CINH_ONLY
  158. __raw_writel(shadow[loop], s->addr_cinh +
  159. offset + loop * 4);
  160. #else
  161. __raw_writel(shadow[loop], s->addr_cena +
  162. offset + loop * 4);
  163. #endif
  164. }
  165. static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
  166. {
  167. uint32_t *shadow = s->cena + offset;
  168. unsigned int loop;
  169. #ifdef QBMAN_CENA_TRACE
  170. pr_info("qbman_cena_read(%p:0x%03x) %p\n",
  171. s->addr_cena, offset, shadow);
  172. #endif
  173. for (loop = 0; loop < 16; loop++)
  174. #ifdef QBMAN_CINH_ONLY
  175. shadow[loop] = __raw_readl(s->addr_cinh + offset
  176. + loop * 4);
  177. #else
  178. shadow[loop] = __raw_readl(s->addr_cena + offset
  179. + loop * 4);
  180. #endif
  181. #ifdef QBMAN_CENA_TRACE
  182. hexdump(shadow, 64);
  183. #endif
  184. return shadow;
  185. }
  186. static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
  187. uint32_t offset)
  188. {
  189. }
  190. /******************/
  191. /* Portal support */
  192. /******************/
  193. /* The SWP_CFG portal register is special, in that it is used by the
  194. * platform-specific code rather than the platform-independent code in
  195. * qbman_portal.c. So use of it is declared locally here. */
  196. #define QBMAN_CINH_SWP_CFG 0xd00
  197. /* For MC portal use, we always configure with
  198. * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
  199. * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0)
  200. * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
  201. * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
  202. * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3)
  203. * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE)
  204. * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
  205. * SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0)
  206. * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
  207. * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0)
  208. * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE)
  209. */
  210. static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
  211. uint8_t est, uint8_t rpm, uint8_t dcm,
  212. uint8_t epm, int sd, int sp, int se,
  213. int dp, int de, int ep)
  214. {
  215. uint32_t reg;
  216. reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
  217. e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) |
  218. e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) |
  219. e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) |
  220. e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) |
  221. e32_uint8_t(14, 1, wn);
  222. return reg;
  223. }
  224. static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
  225. const struct qbman_swp_desc *d,
  226. uint8_t dqrr_size)
  227. {
  228. uint32_t reg;
  229. s->addr_cena = d->cena_bar;
  230. s->addr_cinh = d->cinh_bar;
  231. s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
  232. if (!s->cena) {
  233. printf("Could not allocate page for cena shadow\n");
  234. return -1;
  235. }
  236. memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
  237. #ifdef QBMAN_CHECKING
  238. /* We should never be asked to initialise for a portal that isn't in
  239. * the power-on state. (Ie. don't forget to reset portals when they are
  240. * decommissioned!)
  241. */
  242. reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
  243. BUG_ON(reg);
  244. #endif
  245. #ifdef QBMAN_CINH_ONLY
  246. reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
  247. #else
  248. reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
  249. #endif
  250. qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
  251. reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
  252. if (!reg) {
  253. printf("The portal is not enabled!\n");
  254. free(s->cena);
  255. return -1;
  256. }
  257. return 0;
  258. }
  259. static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
  260. {
  261. free((void *)s->cena);
  262. }