ep93xx_eth.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cirrus Logic EP93xx ethernet MAC / MII driver.
  4. *
  5. * Copyright (C) 2010, 2009
  6. * Matthias Kaehlcke <matthias@kaehlcke.net>
  7. *
  8. * Copyright (C) 2004, 2005
  9. * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
  10. *
  11. * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
  12. * which is
  13. *
  14. * (C) Copyright 2002 2003
  15. * Adam Bezanson, Network Audio Technologies, Inc.
  16. * <bezanson@netaudiotech.com>
  17. */
  18. #include <command.h>
  19. #include <common.h>
  20. #include <log.h>
  21. #include <net.h>
  22. #include <asm/arch/ep93xx.h>
  23. #include <asm/io.h>
  24. #include <malloc.h>
  25. #include <miiphy.h>
  26. #include <linux/bug.h>
  27. #include <linux/types.h>
  28. #include "ep93xx_eth.h"
  29. #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
  30. #define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
  31. /* ep93xx_miiphy ops forward declarations */
  32. static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
  33. int reg);
  34. static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
  35. int reg, u16 value);
  36. #if defined(EP93XX_MAC_DEBUG)
  37. /**
  38. * Dump ep93xx_mac values to the terminal.
  39. */
  40. static void dump_dev(struct eth_device *dev)
  41. {
  42. struct ep93xx_priv *priv = GET_PRIV(dev);
  43. int i;
  44. printf("\ndump_dev()\n");
  45. printf(" rx_dq.base %p\n", priv->rx_dq.base);
  46. printf(" rx_dq.current %p\n", priv->rx_dq.current);
  47. printf(" rx_dq.end %p\n", priv->rx_dq.end);
  48. printf(" rx_sq.base %p\n", priv->rx_sq.base);
  49. printf(" rx_sq.current %p\n", priv->rx_sq.current);
  50. printf(" rx_sq.end %p\n", priv->rx_sq.end);
  51. for (i = 0; i < NUMRXDESC; i++)
  52. printf(" rx_buffer[%2.d] %p\n", i, net_rx_packets[i]);
  53. printf(" tx_dq.base %p\n", priv->tx_dq.base);
  54. printf(" tx_dq.current %p\n", priv->tx_dq.current);
  55. printf(" tx_dq.end %p\n", priv->tx_dq.end);
  56. printf(" tx_sq.base %p\n", priv->tx_sq.base);
  57. printf(" tx_sq.current %p\n", priv->tx_sq.current);
  58. printf(" tx_sq.end %p\n", priv->tx_sq.end);
  59. }
  60. /**
  61. * Dump all RX status queue entries to the terminal.
  62. */
  63. static void dump_rx_status_queue(struct eth_device *dev)
  64. {
  65. struct ep93xx_priv *priv = GET_PRIV(dev);
  66. int i;
  67. printf("\ndump_rx_status_queue()\n");
  68. printf(" descriptor address word1 word2\n");
  69. for (i = 0; i < NUMRXDESC; i++) {
  70. printf(" [ %p ] %08X %08X\n",
  71. priv->rx_sq.base + i,
  72. (priv->rx_sq.base + i)->word1,
  73. (priv->rx_sq.base + i)->word2);
  74. }
  75. }
  76. /**
  77. * Dump all RX descriptor queue entries to the terminal.
  78. */
  79. static void dump_rx_descriptor_queue(struct eth_device *dev)
  80. {
  81. struct ep93xx_priv *priv = GET_PRIV(dev);
  82. int i;
  83. printf("\ndump_rx_descriptor_queue()\n");
  84. printf(" descriptor address word1 word2\n");
  85. for (i = 0; i < NUMRXDESC; i++) {
  86. printf(" [ %p ] %08X %08X\n",
  87. priv->rx_dq.base + i,
  88. (priv->rx_dq.base + i)->word1,
  89. (priv->rx_dq.base + i)->word2);
  90. }
  91. }
  92. /**
  93. * Dump all TX descriptor queue entries to the terminal.
  94. */
  95. static void dump_tx_descriptor_queue(struct eth_device *dev)
  96. {
  97. struct ep93xx_priv *priv = GET_PRIV(dev);
  98. int i;
  99. printf("\ndump_tx_descriptor_queue()\n");
  100. printf(" descriptor address word1 word2\n");
  101. for (i = 0; i < NUMTXDESC; i++) {
  102. printf(" [ %p ] %08X %08X\n",
  103. priv->tx_dq.base + i,
  104. (priv->tx_dq.base + i)->word1,
  105. (priv->tx_dq.base + i)->word2);
  106. }
  107. }
  108. /**
  109. * Dump all TX status queue entries to the terminal.
  110. */
  111. static void dump_tx_status_queue(struct eth_device *dev)
  112. {
  113. struct ep93xx_priv *priv = GET_PRIV(dev);
  114. int i;
  115. printf("\ndump_tx_status_queue()\n");
  116. printf(" descriptor address word1\n");
  117. for (i = 0; i < NUMTXDESC; i++) {
  118. printf(" [ %p ] %08X\n",
  119. priv->rx_sq.base + i,
  120. (priv->rx_sq.base + i)->word1);
  121. }
  122. }
  123. #else
  124. #define dump_dev(x)
  125. #define dump_rx_descriptor_queue(x)
  126. #define dump_rx_status_queue(x)
  127. #define dump_tx_descriptor_queue(x)
  128. #define dump_tx_status_queue(x)
  129. #endif /* defined(EP93XX_MAC_DEBUG) */
  130. /**
  131. * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
  132. * it's cleared.
  133. */
  134. static void ep93xx_mac_reset(struct eth_device *dev)
  135. {
  136. struct mac_regs *mac = GET_REGS(dev);
  137. uint32_t value;
  138. debug("+ep93xx_mac_reset");
  139. value = readl(&mac->selfctl);
  140. value |= SELFCTL_RESET;
  141. writel(value, &mac->selfctl);
  142. while (readl(&mac->selfctl) & SELFCTL_RESET)
  143. ; /* noop */
  144. debug("-ep93xx_mac_reset");
  145. }
  146. /* Eth device open */
  147. static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
  148. {
  149. struct ep93xx_priv *priv = GET_PRIV(dev);
  150. struct mac_regs *mac = GET_REGS(dev);
  151. uchar *mac_addr = dev->enetaddr;
  152. int i;
  153. debug("+ep93xx_eth_open");
  154. /* Reset the MAC */
  155. ep93xx_mac_reset(dev);
  156. /* Reset the descriptor queues' current and end address values */
  157. priv->tx_dq.current = priv->tx_dq.base;
  158. priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
  159. priv->tx_sq.current = priv->tx_sq.base;
  160. priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
  161. priv->rx_dq.current = priv->rx_dq.base;
  162. priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
  163. priv->rx_sq.current = priv->rx_sq.base;
  164. priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
  165. /*
  166. * Set the transmit descriptor and status queues' base address,
  167. * current address, and length registers. Set the maximum frame
  168. * length and threshold. Enable the transmit descriptor processor.
  169. */
  170. writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
  171. writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
  172. writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
  173. writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
  174. writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
  175. writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
  176. writel(0x00040000, &mac->txdthrshld);
  177. writel(0x00040000, &mac->txststhrshld);
  178. writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
  179. writel(BMCTL_TXEN, &mac->bmctl);
  180. /*
  181. * Set the receive descriptor and status queues' base address,
  182. * current address, and length registers. Enable the receive
  183. * descriptor processor.
  184. */
  185. writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
  186. writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
  187. writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
  188. writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
  189. writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
  190. writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
  191. writel(0x00040000, &mac->rxdthrshld);
  192. writel(BMCTL_RXEN, &mac->bmctl);
  193. writel(0x00040000, &mac->rxststhrshld);
  194. /* Wait until the receive descriptor processor is active */
  195. while (!(readl(&mac->bmsts) & BMSTS_RXACT))
  196. ; /* noop */
  197. /*
  198. * Initialize the RX descriptor queue. Clear the TX descriptor queue.
  199. * Clear the RX and TX status queues. Enqueue the RX descriptor and
  200. * status entries to the MAC.
  201. */
  202. for (i = 0; i < NUMRXDESC; i++) {
  203. /* set buffer address */
  204. (priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i];
  205. /* set buffer length, clear buffer index and NSOF */
  206. (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
  207. }
  208. memset(priv->tx_dq.base, 0,
  209. (sizeof(struct tx_descriptor) * NUMTXDESC));
  210. memset(priv->rx_sq.base, 0,
  211. (sizeof(struct rx_status) * NUMRXDESC));
  212. memset(priv->tx_sq.base, 0,
  213. (sizeof(struct tx_status) * NUMTXDESC));
  214. writel(NUMRXDESC, &mac->rxdqenq);
  215. writel(NUMRXDESC, &mac->rxstsqenq);
  216. /* Set the primary MAC address */
  217. writel(AFP_IAPRIMARY, &mac->afp);
  218. writel(mac_addr[0] | (mac_addr[1] << 8) |
  219. (mac_addr[2] << 16) | (mac_addr[3] << 24),
  220. &mac->indad);
  221. writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
  222. /* Turn on RX and TX */
  223. writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
  224. RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
  225. writel(TXCTL_STXON, &mac->txctl);
  226. /* Dump data structures if we're debugging */
  227. dump_dev(dev);
  228. dump_rx_descriptor_queue(dev);
  229. dump_rx_status_queue(dev);
  230. dump_tx_descriptor_queue(dev);
  231. dump_tx_status_queue(dev);
  232. debug("-ep93xx_eth_open");
  233. return 1;
  234. }
  235. /**
  236. * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
  237. * registers.
  238. */
  239. static void ep93xx_eth_close(struct eth_device *dev)
  240. {
  241. struct mac_regs *mac = GET_REGS(dev);
  242. debug("+ep93xx_eth_close");
  243. writel(0x00000000, &mac->rxctl);
  244. writel(0x00000000, &mac->txctl);
  245. debug("-ep93xx_eth_close");
  246. }
  247. /**
  248. * Copy a frame of data from the MAC into the protocol layer for further
  249. * processing.
  250. */
  251. static int ep93xx_eth_rcv_packet(struct eth_device *dev)
  252. {
  253. struct mac_regs *mac = GET_REGS(dev);
  254. struct ep93xx_priv *priv = GET_PRIV(dev);
  255. int len = -1;
  256. debug("+ep93xx_eth_rcv_packet");
  257. if (RX_STATUS_RFP(priv->rx_sq.current)) {
  258. if (RX_STATUS_RWE(priv->rx_sq.current)) {
  259. /*
  260. * We have a good frame. Extract the frame's length
  261. * from the current rx_status_queue entry, and copy
  262. * the frame's data into net_rx_packets[] of the
  263. * protocol stack. We track the total number of
  264. * bytes in the frame (nbytes_frame) which will be
  265. * used when we pass the data off to the protocol
  266. * layer via net_process_received_packet().
  267. */
  268. len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
  269. net_process_received_packet(
  270. (uchar *)priv->rx_dq.current->word1, len);
  271. debug("reporting %d bytes...\n", len);
  272. } else {
  273. /* Do we have an erroneous packet? */
  274. pr_err("packet rx error, status %08X %08X",
  275. priv->rx_sq.current->word1,
  276. priv->rx_sq.current->word2);
  277. dump_rx_descriptor_queue(dev);
  278. dump_rx_status_queue(dev);
  279. }
  280. /*
  281. * Clear the associated status queue entry, and
  282. * increment our current pointers to the next RX
  283. * descriptor and status queue entries (making sure
  284. * we wrap properly).
  285. */
  286. memset((void *)priv->rx_sq.current, 0,
  287. sizeof(struct rx_status));
  288. priv->rx_sq.current++;
  289. if (priv->rx_sq.current >= priv->rx_sq.end)
  290. priv->rx_sq.current = priv->rx_sq.base;
  291. priv->rx_dq.current++;
  292. if (priv->rx_dq.current >= priv->rx_dq.end)
  293. priv->rx_dq.current = priv->rx_dq.base;
  294. /*
  295. * Finally, return the RX descriptor and status entries
  296. * back to the MAC engine, and loop again, checking for
  297. * more descriptors to process.
  298. */
  299. writel(1, &mac->rxdqenq);
  300. writel(1, &mac->rxstsqenq);
  301. } else {
  302. len = 0;
  303. }
  304. debug("-ep93xx_eth_rcv_packet %d", len);
  305. return len;
  306. }
  307. /**
  308. * Send a block of data via ethernet.
  309. */
  310. static int ep93xx_eth_send_packet(struct eth_device *dev,
  311. void * const packet, int const length)
  312. {
  313. struct mac_regs *mac = GET_REGS(dev);
  314. struct ep93xx_priv *priv = GET_PRIV(dev);
  315. int ret = -1;
  316. debug("+ep93xx_eth_send_packet");
  317. /* Parameter check */
  318. BUG_ON(packet == NULL);
  319. /*
  320. * Initialize the TX descriptor queue with the new packet's info.
  321. * Clear the associated status queue entry. Enqueue the packet
  322. * to the MAC for transmission.
  323. */
  324. /* set buffer address */
  325. priv->tx_dq.current->word1 = (uint32_t)packet;
  326. /* set buffer length and EOF bit */
  327. priv->tx_dq.current->word2 = length | TX_DESC_EOF;
  328. /* clear tx status */
  329. priv->tx_sq.current->word1 = 0;
  330. /* enqueue the TX descriptor */
  331. writel(1, &mac->txdqenq);
  332. /* wait for the frame to become processed */
  333. while (!TX_STATUS_TXFP(priv->tx_sq.current))
  334. ; /* noop */
  335. if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
  336. pr_err("packet tx error, status %08X",
  337. priv->tx_sq.current->word1);
  338. dump_tx_descriptor_queue(dev);
  339. dump_tx_status_queue(dev);
  340. /* TODO: Add better error handling? */
  341. goto eth_send_out;
  342. }
  343. ret = 0;
  344. /* Fall through */
  345. eth_send_out:
  346. debug("-ep93xx_eth_send_packet %d", ret);
  347. return ret;
  348. }
  349. #if defined(CONFIG_MII)
  350. int ep93xx_miiphy_initialize(bd_t * const bd)
  351. {
  352. int retval;
  353. struct mii_dev *mdiodev = mdio_alloc();
  354. if (!mdiodev)
  355. return -ENOMEM;
  356. strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
  357. mdiodev->read = ep93xx_miiphy_read;
  358. mdiodev->write = ep93xx_miiphy_write;
  359. retval = mdio_register(mdiodev);
  360. if (retval < 0)
  361. return retval;
  362. return 0;
  363. }
  364. #endif
  365. /**
  366. * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
  367. * allocated, if necessary, for the TX and RX descriptor and status queues,
  368. * as well as for received packets. The EP93XX MAC hardware is initialized.
  369. * Transmit and receive operations are enabled.
  370. */
  371. int ep93xx_eth_initialize(u8 dev_num, int base_addr)
  372. {
  373. int ret = -1;
  374. struct eth_device *dev;
  375. struct ep93xx_priv *priv;
  376. debug("+ep93xx_eth_initialize");
  377. priv = malloc(sizeof(*priv));
  378. if (!priv) {
  379. pr_err("malloc() failed");
  380. goto eth_init_failed_0;
  381. }
  382. memset(priv, 0, sizeof(*priv));
  383. priv->regs = (struct mac_regs *)base_addr;
  384. priv->tx_dq.base = calloc(NUMTXDESC,
  385. sizeof(struct tx_descriptor));
  386. if (priv->tx_dq.base == NULL) {
  387. pr_err("calloc() failed");
  388. goto eth_init_failed_1;
  389. }
  390. priv->tx_sq.base = calloc(NUMTXDESC,
  391. sizeof(struct tx_status));
  392. if (priv->tx_sq.base == NULL) {
  393. pr_err("calloc() failed");
  394. goto eth_init_failed_2;
  395. }
  396. priv->rx_dq.base = calloc(NUMRXDESC,
  397. sizeof(struct rx_descriptor));
  398. if (priv->rx_dq.base == NULL) {
  399. pr_err("calloc() failed");
  400. goto eth_init_failed_3;
  401. }
  402. priv->rx_sq.base = calloc(NUMRXDESC,
  403. sizeof(struct rx_status));
  404. if (priv->rx_sq.base == NULL) {
  405. pr_err("calloc() failed");
  406. goto eth_init_failed_4;
  407. }
  408. dev = malloc(sizeof *dev);
  409. if (dev == NULL) {
  410. pr_err("malloc() failed");
  411. goto eth_init_failed_5;
  412. }
  413. memset(dev, 0, sizeof *dev);
  414. dev->iobase = base_addr;
  415. dev->priv = priv;
  416. dev->init = ep93xx_eth_open;
  417. dev->halt = ep93xx_eth_close;
  418. dev->send = ep93xx_eth_send_packet;
  419. dev->recv = ep93xx_eth_rcv_packet;
  420. sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
  421. eth_register(dev);
  422. /* Done! */
  423. ret = 1;
  424. goto eth_init_done;
  425. eth_init_failed_5:
  426. free(priv->rx_sq.base);
  427. /* Fall through */
  428. eth_init_failed_4:
  429. free(priv->rx_dq.base);
  430. /* Fall through */
  431. eth_init_failed_3:
  432. free(priv->tx_sq.base);
  433. /* Fall through */
  434. eth_init_failed_2:
  435. free(priv->tx_dq.base);
  436. /* Fall through */
  437. eth_init_failed_1:
  438. free(priv);
  439. /* Fall through */
  440. eth_init_failed_0:
  441. /* Fall through */
  442. eth_init_done:
  443. debug("-ep93xx_eth_initialize %d", ret);
  444. return ret;
  445. }
  446. #if defined(CONFIG_MII)
  447. /**
  448. * Maximum MII address we support
  449. */
  450. #define MII_ADDRESS_MAX 31
  451. /**
  452. * Maximum MII register address we support
  453. */
  454. #define MII_REGISTER_MAX 31
  455. /**
  456. * Read a 16-bit value from an MII register.
  457. */
  458. static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
  459. int reg)
  460. {
  461. unsigned short value = 0;
  462. struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
  463. int ret = -1;
  464. uint32_t self_ctl;
  465. debug("+ep93xx_miiphy_read");
  466. /* Parameter checks */
  467. BUG_ON(bus->name == NULL);
  468. BUG_ON(addr > MII_ADDRESS_MAX);
  469. BUG_ON(reg > MII_REGISTER_MAX);
  470. /*
  471. * Save the current SelfCTL register value. Set MAC to suppress
  472. * preamble bits. Wait for any previous MII command to complete
  473. * before issuing the new command.
  474. */
  475. self_ctl = readl(&mac->selfctl);
  476. #if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
  477. writel(self_ctl & ~(1 << 8), &mac->selfctl);
  478. #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
  479. while (readl(&mac->miists) & MIISTS_BUSY)
  480. ; /* noop */
  481. /*
  482. * Issue the MII 'read' command. Wait for the command to complete.
  483. * Read the MII data value.
  484. */
  485. writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
  486. &mac->miicmd);
  487. while (readl(&mac->miists) & MIISTS_BUSY)
  488. ; /* noop */
  489. value = (unsigned short)readl(&mac->miidata);
  490. /* Restore the saved SelfCTL value and return. */
  491. writel(self_ctl, &mac->selfctl);
  492. ret = 0;
  493. /* Fall through */
  494. debug("-ep93xx_miiphy_read");
  495. if (ret < 0)
  496. return ret;
  497. return value;
  498. }
  499. /**
  500. * Write a 16-bit value to an MII register.
  501. */
  502. static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
  503. int reg, u16 value)
  504. {
  505. struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
  506. int ret = -1;
  507. uint32_t self_ctl;
  508. debug("+ep93xx_miiphy_write");
  509. /* Parameter checks */
  510. BUG_ON(bus->name == NULL);
  511. BUG_ON(addr > MII_ADDRESS_MAX);
  512. BUG_ON(reg > MII_REGISTER_MAX);
  513. /*
  514. * Save the current SelfCTL register value. Set MAC to suppress
  515. * preamble bits. Wait for any previous MII command to complete
  516. * before issuing the new command.
  517. */
  518. self_ctl = readl(&mac->selfctl);
  519. #if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
  520. writel(self_ctl & ~(1 << 8), &mac->selfctl);
  521. #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
  522. while (readl(&mac->miists) & MIISTS_BUSY)
  523. ; /* noop */
  524. /* Issue the MII 'write' command. Wait for the command to complete. */
  525. writel((uint32_t)value, &mac->miidata);
  526. writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
  527. &mac->miicmd);
  528. while (readl(&mac->miists) & MIISTS_BUSY)
  529. ; /* noop */
  530. /* Restore the saved SelfCTL value and return. */
  531. writel(self_ctl, &mac->selfctl);
  532. ret = 0;
  533. /* Fall through */
  534. debug("-ep93xx_miiphy_write");
  535. return ret;
  536. }
  537. #endif /* defined(CONFIG_MII) */