core.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2017 Micron Technology, Inc.
  4. *
  5. * Authors:
  6. * Peter Pan <peterpandong@micron.com>
  7. * Boris Brezillon <boris.brezillon@bootlin.com>
  8. */
  9. #define pr_fmt(fmt) "spi-nand: " fmt
  10. #ifndef __UBOOT__
  11. #include <linux/device.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/mtd/spinand.h>
  16. #include <linux/of.h>
  17. #include <linux/slab.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/spi-mem.h>
  20. #else
  21. #include <common.h>
  22. #include <errno.h>
  23. #include <spi.h>
  24. #include <spi-mem.h>
  25. #include <dm/device_compat.h>
  26. #include <dm/devres.h>
  27. #include <linux/bug.h>
  28. #include <linux/mtd/spinand.h>
  29. #endif
  30. /* SPI NAND index visible in MTD names */
  31. static int spi_nand_idx;
  32. static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
  33. const struct nand_page_io_req *req,
  34. u16 *column)
  35. {
  36. struct nand_device *nand = spinand_to_nand(spinand);
  37. unsigned int shift;
  38. if (nand->memorg.planes_per_lun < 2)
  39. return;
  40. /* The plane number is passed in MSB just above the column address */
  41. shift = fls(nand->memorg.pagesize);
  42. *column |= req->pos.plane << shift;
  43. }
  44. static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
  45. {
  46. struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
  47. spinand->scratchbuf);
  48. int ret;
  49. ret = spi_mem_exec_op(spinand->slave, &op);
  50. if (ret)
  51. return ret;
  52. *val = *spinand->scratchbuf;
  53. return 0;
  54. }
  55. static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
  56. {
  57. struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
  58. spinand->scratchbuf);
  59. *spinand->scratchbuf = val;
  60. return spi_mem_exec_op(spinand->slave, &op);
  61. }
  62. static int spinand_read_status(struct spinand_device *spinand, u8 *status)
  63. {
  64. return spinand_read_reg_op(spinand, REG_STATUS, status);
  65. }
  66. static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg)
  67. {
  68. struct nand_device *nand = spinand_to_nand(spinand);
  69. if (WARN_ON(spinand->cur_target < 0 ||
  70. spinand->cur_target >= nand->memorg.ntargets))
  71. return -EINVAL;
  72. *cfg = spinand->cfg_cache[spinand->cur_target];
  73. return 0;
  74. }
  75. static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg)
  76. {
  77. struct nand_device *nand = spinand_to_nand(spinand);
  78. int ret;
  79. if (WARN_ON(spinand->cur_target < 0 ||
  80. spinand->cur_target >= nand->memorg.ntargets))
  81. return -EINVAL;
  82. if (spinand->cfg_cache[spinand->cur_target] == cfg)
  83. return 0;
  84. ret = spinand_write_reg_op(spinand, REG_CFG, cfg);
  85. if (ret)
  86. return ret;
  87. spinand->cfg_cache[spinand->cur_target] = cfg;
  88. return 0;
  89. }
  90. /**
  91. * spinand_upd_cfg() - Update the configuration register
  92. * @spinand: the spinand device
  93. * @mask: the mask encoding the bits to update in the config reg
  94. * @val: the new value to apply
  95. *
  96. * Update the configuration register.
  97. *
  98. * Return: 0 on success, a negative error code otherwise.
  99. */
  100. int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val)
  101. {
  102. int ret;
  103. u8 cfg;
  104. ret = spinand_get_cfg(spinand, &cfg);
  105. if (ret)
  106. return ret;
  107. cfg &= ~mask;
  108. cfg |= val;
  109. return spinand_set_cfg(spinand, cfg);
  110. }
  111. /**
  112. * spinand_select_target() - Select a specific NAND target/die
  113. * @spinand: the spinand device
  114. * @target: the target/die to select
  115. *
  116. * Select a new target/die. If chip only has one die, this function is a NOOP.
  117. *
  118. * Return: 0 on success, a negative error code otherwise.
  119. */
  120. int spinand_select_target(struct spinand_device *spinand, unsigned int target)
  121. {
  122. struct nand_device *nand = spinand_to_nand(spinand);
  123. int ret;
  124. if (WARN_ON(target >= nand->memorg.ntargets))
  125. return -EINVAL;
  126. if (spinand->cur_target == target)
  127. return 0;
  128. if (nand->memorg.ntargets == 1) {
  129. spinand->cur_target = target;
  130. return 0;
  131. }
  132. ret = spinand->select_target(spinand, target);
  133. if (ret)
  134. return ret;
  135. spinand->cur_target = target;
  136. return 0;
  137. }
  138. static int spinand_init_cfg_cache(struct spinand_device *spinand)
  139. {
  140. struct nand_device *nand = spinand_to_nand(spinand);
  141. struct udevice *dev = spinand->slave->dev;
  142. unsigned int target;
  143. int ret;
  144. spinand->cfg_cache = devm_kzalloc(dev,
  145. sizeof(*spinand->cfg_cache) *
  146. nand->memorg.ntargets,
  147. GFP_KERNEL);
  148. if (!spinand->cfg_cache)
  149. return -ENOMEM;
  150. for (target = 0; target < nand->memorg.ntargets; target++) {
  151. ret = spinand_select_target(spinand, target);
  152. if (ret)
  153. return ret;
  154. /*
  155. * We use spinand_read_reg_op() instead of spinand_get_cfg()
  156. * here to bypass the config cache.
  157. */
  158. ret = spinand_read_reg_op(spinand, REG_CFG,
  159. &spinand->cfg_cache[target]);
  160. if (ret)
  161. return ret;
  162. }
  163. return 0;
  164. }
  165. static int spinand_init_quad_enable(struct spinand_device *spinand)
  166. {
  167. bool enable = false;
  168. if (!(spinand->flags & SPINAND_HAS_QE_BIT))
  169. return 0;
  170. if (spinand->op_templates.read_cache->data.buswidth == 4 ||
  171. spinand->op_templates.write_cache->data.buswidth == 4 ||
  172. spinand->op_templates.update_cache->data.buswidth == 4)
  173. enable = true;
  174. return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
  175. enable ? CFG_QUAD_ENABLE : 0);
  176. }
  177. static int spinand_ecc_enable(struct spinand_device *spinand,
  178. bool enable)
  179. {
  180. return spinand_upd_cfg(spinand, CFG_ECC_ENABLE,
  181. enable ? CFG_ECC_ENABLE : 0);
  182. }
  183. static int spinand_write_enable_op(struct spinand_device *spinand)
  184. {
  185. struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
  186. return spi_mem_exec_op(spinand->slave, &op);
  187. }
  188. static int spinand_load_page_op(struct spinand_device *spinand,
  189. const struct nand_page_io_req *req)
  190. {
  191. struct nand_device *nand = spinand_to_nand(spinand);
  192. unsigned int row = nanddev_pos_to_row(nand, &req->pos);
  193. struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
  194. return spi_mem_exec_op(spinand->slave, &op);
  195. }
  196. static int spinand_read_from_cache_op(struct spinand_device *spinand,
  197. const struct nand_page_io_req *req)
  198. {
  199. struct spi_mem_op op = *spinand->op_templates.read_cache;
  200. struct nand_device *nand = spinand_to_nand(spinand);
  201. struct mtd_info *mtd = nanddev_to_mtd(nand);
  202. struct nand_page_io_req adjreq = *req;
  203. unsigned int nbytes = 0;
  204. void *buf = NULL;
  205. u16 column = 0;
  206. int ret;
  207. if (req->datalen) {
  208. adjreq.datalen = nanddev_page_size(nand);
  209. adjreq.dataoffs = 0;
  210. adjreq.databuf.in = spinand->databuf;
  211. buf = spinand->databuf;
  212. nbytes = adjreq.datalen;
  213. }
  214. if (req->ooblen) {
  215. adjreq.ooblen = nanddev_per_page_oobsize(nand);
  216. adjreq.ooboffs = 0;
  217. adjreq.oobbuf.in = spinand->oobbuf;
  218. nbytes += nanddev_per_page_oobsize(nand);
  219. if (!buf) {
  220. buf = spinand->oobbuf;
  221. column = nanddev_page_size(nand);
  222. }
  223. }
  224. spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
  225. op.addr.val = column;
  226. /*
  227. * Some controllers are limited in term of max RX data size. In this
  228. * case, just repeat the READ_CACHE operation after updating the
  229. * column.
  230. */
  231. while (nbytes) {
  232. op.data.buf.in = buf;
  233. op.data.nbytes = nbytes;
  234. ret = spi_mem_adjust_op_size(spinand->slave, &op);
  235. if (ret)
  236. return ret;
  237. ret = spi_mem_exec_op(spinand->slave, &op);
  238. if (ret)
  239. return ret;
  240. buf += op.data.nbytes;
  241. nbytes -= op.data.nbytes;
  242. op.addr.val += op.data.nbytes;
  243. }
  244. if (req->datalen)
  245. memcpy(req->databuf.in, spinand->databuf + req->dataoffs,
  246. req->datalen);
  247. if (req->ooblen) {
  248. if (req->mode == MTD_OPS_AUTO_OOB)
  249. mtd_ooblayout_get_databytes(mtd, req->oobbuf.in,
  250. spinand->oobbuf,
  251. req->ooboffs,
  252. req->ooblen);
  253. else
  254. memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs,
  255. req->ooblen);
  256. }
  257. return 0;
  258. }
  259. static int spinand_write_to_cache_op(struct spinand_device *spinand,
  260. const struct nand_page_io_req *req)
  261. {
  262. struct spi_mem_op op = *spinand->op_templates.write_cache;
  263. struct nand_device *nand = spinand_to_nand(spinand);
  264. struct mtd_info *mtd = nanddev_to_mtd(nand);
  265. struct nand_page_io_req adjreq = *req;
  266. unsigned int nbytes = 0;
  267. void *buf = NULL;
  268. u16 column = 0;
  269. int ret;
  270. memset(spinand->databuf, 0xff,
  271. nanddev_page_size(nand) +
  272. nanddev_per_page_oobsize(nand));
  273. if (req->datalen) {
  274. memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
  275. req->datalen);
  276. adjreq.dataoffs = 0;
  277. adjreq.datalen = nanddev_page_size(nand);
  278. adjreq.databuf.out = spinand->databuf;
  279. nbytes = adjreq.datalen;
  280. buf = spinand->databuf;
  281. }
  282. if (req->ooblen) {
  283. if (req->mode == MTD_OPS_AUTO_OOB)
  284. mtd_ooblayout_set_databytes(mtd, req->oobbuf.out,
  285. spinand->oobbuf,
  286. req->ooboffs,
  287. req->ooblen);
  288. else
  289. memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
  290. req->ooblen);
  291. adjreq.ooblen = nanddev_per_page_oobsize(nand);
  292. adjreq.ooboffs = 0;
  293. nbytes += nanddev_per_page_oobsize(nand);
  294. if (!buf) {
  295. buf = spinand->oobbuf;
  296. column = nanddev_page_size(nand);
  297. }
  298. }
  299. spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
  300. op = *spinand->op_templates.write_cache;
  301. op.addr.val = column;
  302. /*
  303. * Some controllers are limited in term of max TX data size. In this
  304. * case, split the operation into one LOAD CACHE and one or more
  305. * LOAD RANDOM CACHE.
  306. */
  307. while (nbytes) {
  308. op.data.buf.out = buf;
  309. op.data.nbytes = nbytes;
  310. ret = spi_mem_adjust_op_size(spinand->slave, &op);
  311. if (ret)
  312. return ret;
  313. ret = spi_mem_exec_op(spinand->slave, &op);
  314. if (ret)
  315. return ret;
  316. buf += op.data.nbytes;
  317. nbytes -= op.data.nbytes;
  318. op.addr.val += op.data.nbytes;
  319. /*
  320. * We need to use the RANDOM LOAD CACHE operation if there's
  321. * more than one iteration, because the LOAD operation resets
  322. * the cache to 0xff.
  323. */
  324. if (nbytes) {
  325. column = op.addr.val;
  326. op = *spinand->op_templates.update_cache;
  327. op.addr.val = column;
  328. }
  329. }
  330. return 0;
  331. }
  332. static int spinand_program_op(struct spinand_device *spinand,
  333. const struct nand_page_io_req *req)
  334. {
  335. struct nand_device *nand = spinand_to_nand(spinand);
  336. unsigned int row = nanddev_pos_to_row(nand, &req->pos);
  337. struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
  338. return spi_mem_exec_op(spinand->slave, &op);
  339. }
  340. static int spinand_erase_op(struct spinand_device *spinand,
  341. const struct nand_pos *pos)
  342. {
  343. struct nand_device *nand = &spinand->base;
  344. unsigned int row = nanddev_pos_to_row(nand, pos);
  345. struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
  346. return spi_mem_exec_op(spinand->slave, &op);
  347. }
  348. static int spinand_wait(struct spinand_device *spinand, u8 *s)
  349. {
  350. unsigned long start, stop;
  351. u8 status;
  352. int ret;
  353. start = get_timer(0);
  354. stop = 400;
  355. do {
  356. ret = spinand_read_status(spinand, &status);
  357. if (ret)
  358. return ret;
  359. if (!(status & STATUS_BUSY))
  360. goto out;
  361. } while (get_timer(start) < stop);
  362. /*
  363. * Extra read, just in case the STATUS_READY bit has changed
  364. * since our last check
  365. */
  366. ret = spinand_read_status(spinand, &status);
  367. if (ret)
  368. return ret;
  369. out:
  370. if (s)
  371. *s = status;
  372. return status & STATUS_BUSY ? -ETIMEDOUT : 0;
  373. }
  374. static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
  375. {
  376. struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
  377. SPINAND_MAX_ID_LEN);
  378. int ret;
  379. ret = spi_mem_exec_op(spinand->slave, &op);
  380. if (!ret)
  381. memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
  382. return ret;
  383. }
  384. static int spinand_reset_op(struct spinand_device *spinand)
  385. {
  386. struct spi_mem_op op = SPINAND_RESET_OP;
  387. int ret;
  388. ret = spi_mem_exec_op(spinand->slave, &op);
  389. if (ret)
  390. return ret;
  391. return spinand_wait(spinand, NULL);
  392. }
  393. static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
  394. {
  395. return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
  396. }
  397. static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
  398. {
  399. struct nand_device *nand = spinand_to_nand(spinand);
  400. if (spinand->eccinfo.get_status)
  401. return spinand->eccinfo.get_status(spinand, status);
  402. switch (status & STATUS_ECC_MASK) {
  403. case STATUS_ECC_NO_BITFLIPS:
  404. return 0;
  405. case STATUS_ECC_HAS_BITFLIPS:
  406. /*
  407. * We have no way to know exactly how many bitflips have been
  408. * fixed, so let's return the maximum possible value so that
  409. * wear-leveling layers move the data immediately.
  410. */
  411. return nand->eccreq.strength;
  412. case STATUS_ECC_UNCOR_ERROR:
  413. return -EBADMSG;
  414. default:
  415. break;
  416. }
  417. return -EINVAL;
  418. }
  419. static int spinand_read_page(struct spinand_device *spinand,
  420. const struct nand_page_io_req *req,
  421. bool ecc_enabled)
  422. {
  423. u8 status;
  424. int ret;
  425. ret = spinand_load_page_op(spinand, req);
  426. if (ret)
  427. return ret;
  428. ret = spinand_wait(spinand, &status);
  429. if (ret < 0)
  430. return ret;
  431. ret = spinand_read_from_cache_op(spinand, req);
  432. if (ret)
  433. return ret;
  434. if (!ecc_enabled)
  435. return 0;
  436. return spinand_check_ecc_status(spinand, status);
  437. }
  438. static int spinand_write_page(struct spinand_device *spinand,
  439. const struct nand_page_io_req *req)
  440. {
  441. u8 status;
  442. int ret;
  443. ret = spinand_write_enable_op(spinand);
  444. if (ret)
  445. return ret;
  446. ret = spinand_write_to_cache_op(spinand, req);
  447. if (ret)
  448. return ret;
  449. ret = spinand_program_op(spinand, req);
  450. if (ret)
  451. return ret;
  452. ret = spinand_wait(spinand, &status);
  453. if (!ret && (status & STATUS_PROG_FAILED))
  454. ret = -EIO;
  455. return ret;
  456. }
  457. static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
  458. struct mtd_oob_ops *ops)
  459. {
  460. struct spinand_device *spinand = mtd_to_spinand(mtd);
  461. struct nand_device *nand = mtd_to_nanddev(mtd);
  462. unsigned int max_bitflips = 0;
  463. struct nand_io_iter iter;
  464. bool enable_ecc = false;
  465. bool ecc_failed = false;
  466. int ret = 0;
  467. if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
  468. enable_ecc = true;
  469. #ifndef __UBOOT__
  470. mutex_lock(&spinand->lock);
  471. #endif
  472. nanddev_io_for_each_page(nand, from, ops, &iter) {
  473. ret = spinand_select_target(spinand, iter.req.pos.target);
  474. if (ret)
  475. break;
  476. ret = spinand_ecc_enable(spinand, enable_ecc);
  477. if (ret)
  478. break;
  479. ret = spinand_read_page(spinand, &iter.req, enable_ecc);
  480. if (ret < 0 && ret != -EBADMSG)
  481. break;
  482. if (ret == -EBADMSG) {
  483. ecc_failed = true;
  484. mtd->ecc_stats.failed++;
  485. ret = 0;
  486. } else {
  487. mtd->ecc_stats.corrected += ret;
  488. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  489. }
  490. ops->retlen += iter.req.datalen;
  491. ops->oobretlen += iter.req.ooblen;
  492. }
  493. #ifndef __UBOOT__
  494. mutex_unlock(&spinand->lock);
  495. #endif
  496. if (ecc_failed && !ret)
  497. ret = -EBADMSG;
  498. return ret ? ret : max_bitflips;
  499. }
  500. static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
  501. struct mtd_oob_ops *ops)
  502. {
  503. struct spinand_device *spinand = mtd_to_spinand(mtd);
  504. struct nand_device *nand = mtd_to_nanddev(mtd);
  505. struct nand_io_iter iter;
  506. bool enable_ecc = false;
  507. int ret = 0;
  508. if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
  509. enable_ecc = true;
  510. #ifndef __UBOOT__
  511. mutex_lock(&spinand->lock);
  512. #endif
  513. nanddev_io_for_each_page(nand, to, ops, &iter) {
  514. ret = spinand_select_target(spinand, iter.req.pos.target);
  515. if (ret)
  516. break;
  517. ret = spinand_ecc_enable(spinand, enable_ecc);
  518. if (ret)
  519. break;
  520. ret = spinand_write_page(spinand, &iter.req);
  521. if (ret)
  522. break;
  523. ops->retlen += iter.req.datalen;
  524. ops->oobretlen += iter.req.ooblen;
  525. }
  526. #ifndef __UBOOT__
  527. mutex_unlock(&spinand->lock);
  528. #endif
  529. return ret;
  530. }
  531. static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
  532. {
  533. struct spinand_device *spinand = nand_to_spinand(nand);
  534. struct nand_page_io_req req = {
  535. .pos = *pos,
  536. .ooblen = 2,
  537. .ooboffs = 0,
  538. .oobbuf.in = spinand->oobbuf,
  539. .mode = MTD_OPS_RAW,
  540. };
  541. int ret;
  542. memset(spinand->oobbuf, 0, 2);
  543. ret = spinand_select_target(spinand, pos->target);
  544. if (ret)
  545. return ret;
  546. ret = spinand_read_page(spinand, &req, false);
  547. if (ret)
  548. return ret;
  549. if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
  550. return true;
  551. return false;
  552. }
  553. static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
  554. {
  555. struct nand_device *nand = mtd_to_nanddev(mtd);
  556. #ifndef __UBOOT__
  557. struct spinand_device *spinand = nand_to_spinand(nand);
  558. #endif
  559. struct nand_pos pos;
  560. int ret;
  561. nanddev_offs_to_pos(nand, offs, &pos);
  562. #ifndef __UBOOT__
  563. mutex_lock(&spinand->lock);
  564. #endif
  565. ret = nanddev_isbad(nand, &pos);
  566. #ifndef __UBOOT__
  567. mutex_unlock(&spinand->lock);
  568. #endif
  569. return ret;
  570. }
  571. static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
  572. {
  573. struct spinand_device *spinand = nand_to_spinand(nand);
  574. struct nand_page_io_req req = {
  575. .pos = *pos,
  576. .ooboffs = 0,
  577. .ooblen = 2,
  578. .oobbuf.out = spinand->oobbuf,
  579. };
  580. int ret;
  581. /* Erase block before marking it bad. */
  582. ret = spinand_select_target(spinand, pos->target);
  583. if (ret)
  584. return ret;
  585. ret = spinand_write_enable_op(spinand);
  586. if (ret)
  587. return ret;
  588. ret = spinand_erase_op(spinand, pos);
  589. if (ret)
  590. return ret;
  591. memset(spinand->oobbuf, 0, 2);
  592. return spinand_write_page(spinand, &req);
  593. }
  594. static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
  595. {
  596. struct nand_device *nand = mtd_to_nanddev(mtd);
  597. #ifndef __UBOOT__
  598. struct spinand_device *spinand = nand_to_spinand(nand);
  599. #endif
  600. struct nand_pos pos;
  601. int ret;
  602. nanddev_offs_to_pos(nand, offs, &pos);
  603. #ifndef __UBOOT__
  604. mutex_lock(&spinand->lock);
  605. #endif
  606. ret = nanddev_markbad(nand, &pos);
  607. #ifndef __UBOOT__
  608. mutex_unlock(&spinand->lock);
  609. #endif
  610. return ret;
  611. }
  612. static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos)
  613. {
  614. struct spinand_device *spinand = nand_to_spinand(nand);
  615. u8 status;
  616. int ret;
  617. ret = spinand_select_target(spinand, pos->target);
  618. if (ret)
  619. return ret;
  620. ret = spinand_write_enable_op(spinand);
  621. if (ret)
  622. return ret;
  623. ret = spinand_erase_op(spinand, pos);
  624. if (ret)
  625. return ret;
  626. ret = spinand_wait(spinand, &status);
  627. if (!ret && (status & STATUS_ERASE_FAILED))
  628. ret = -EIO;
  629. return ret;
  630. }
  631. static int spinand_mtd_erase(struct mtd_info *mtd,
  632. struct erase_info *einfo)
  633. {
  634. #ifndef __UBOOT__
  635. struct spinand_device *spinand = mtd_to_spinand(mtd);
  636. #endif
  637. int ret;
  638. #ifndef __UBOOT__
  639. mutex_lock(&spinand->lock);
  640. #endif
  641. ret = nanddev_mtd_erase(mtd, einfo);
  642. #ifndef __UBOOT__
  643. mutex_unlock(&spinand->lock);
  644. #endif
  645. return ret;
  646. }
  647. static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
  648. {
  649. #ifndef __UBOOT__
  650. struct spinand_device *spinand = mtd_to_spinand(mtd);
  651. #endif
  652. struct nand_device *nand = mtd_to_nanddev(mtd);
  653. struct nand_pos pos;
  654. int ret;
  655. nanddev_offs_to_pos(nand, offs, &pos);
  656. #ifndef __UBOOT__
  657. mutex_lock(&spinand->lock);
  658. #endif
  659. ret = nanddev_isreserved(nand, &pos);
  660. #ifndef __UBOOT__
  661. mutex_unlock(&spinand->lock);
  662. #endif
  663. return ret;
  664. }
  665. const struct spi_mem_op *
  666. spinand_find_supported_op(struct spinand_device *spinand,
  667. const struct spi_mem_op *ops,
  668. unsigned int nops)
  669. {
  670. unsigned int i;
  671. for (i = 0; i < nops; i++) {
  672. if (spi_mem_supports_op(spinand->slave, &ops[i]))
  673. return &ops[i];
  674. }
  675. return NULL;
  676. }
  677. static const struct nand_ops spinand_ops = {
  678. .erase = spinand_erase,
  679. .markbad = spinand_markbad,
  680. .isbad = spinand_isbad,
  681. };
  682. static const struct spinand_manufacturer *spinand_manufacturers[] = {
  683. &gigadevice_spinand_manufacturer,
  684. &macronix_spinand_manufacturer,
  685. &micron_spinand_manufacturer,
  686. &toshiba_spinand_manufacturer,
  687. &winbond_spinand_manufacturer,
  688. };
  689. static int spinand_manufacturer_detect(struct spinand_device *spinand)
  690. {
  691. unsigned int i;
  692. int ret;
  693. for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
  694. ret = spinand_manufacturers[i]->ops->detect(spinand);
  695. if (ret > 0) {
  696. spinand->manufacturer = spinand_manufacturers[i];
  697. return 0;
  698. } else if (ret < 0) {
  699. return ret;
  700. }
  701. }
  702. return -ENOTSUPP;
  703. }
  704. static int spinand_manufacturer_init(struct spinand_device *spinand)
  705. {
  706. if (spinand->manufacturer->ops->init)
  707. return spinand->manufacturer->ops->init(spinand);
  708. return 0;
  709. }
  710. static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
  711. {
  712. /* Release manufacturer private data */
  713. if (spinand->manufacturer->ops->cleanup)
  714. return spinand->manufacturer->ops->cleanup(spinand);
  715. }
  716. static const struct spi_mem_op *
  717. spinand_select_op_variant(struct spinand_device *spinand,
  718. const struct spinand_op_variants *variants)
  719. {
  720. struct nand_device *nand = spinand_to_nand(spinand);
  721. unsigned int i;
  722. for (i = 0; i < variants->nops; i++) {
  723. struct spi_mem_op op = variants->ops[i];
  724. unsigned int nbytes;
  725. int ret;
  726. nbytes = nanddev_per_page_oobsize(nand) +
  727. nanddev_page_size(nand);
  728. while (nbytes) {
  729. op.data.nbytes = nbytes;
  730. ret = spi_mem_adjust_op_size(spinand->slave, &op);
  731. if (ret)
  732. break;
  733. if (!spi_mem_supports_op(spinand->slave, &op))
  734. break;
  735. nbytes -= op.data.nbytes;
  736. }
  737. if (!nbytes)
  738. return &variants->ops[i];
  739. }
  740. return NULL;
  741. }
  742. /**
  743. * spinand_match_and_init() - Try to find a match between a device ID and an
  744. * entry in a spinand_info table
  745. * @spinand: SPI NAND object
  746. * @table: SPI NAND device description table
  747. * @table_size: size of the device description table
  748. *
  749. * Should be used by SPI NAND manufacturer drivers when they want to find a
  750. * match between a device ID retrieved through the READ_ID command and an
  751. * entry in the SPI NAND description table. If a match is found, the spinand
  752. * object will be initialized with information provided by the matching
  753. * spinand_info entry.
  754. *
  755. * Return: 0 on success, a negative error code otherwise.
  756. */
  757. int spinand_match_and_init(struct spinand_device *spinand,
  758. const struct spinand_info *table,
  759. unsigned int table_size, u8 devid)
  760. {
  761. struct nand_device *nand = spinand_to_nand(spinand);
  762. unsigned int i;
  763. for (i = 0; i < table_size; i++) {
  764. const struct spinand_info *info = &table[i];
  765. const struct spi_mem_op *op;
  766. if (devid != info->devid)
  767. continue;
  768. nand->memorg = table[i].memorg;
  769. nand->eccreq = table[i].eccreq;
  770. spinand->eccinfo = table[i].eccinfo;
  771. spinand->flags = table[i].flags;
  772. spinand->select_target = table[i].select_target;
  773. op = spinand_select_op_variant(spinand,
  774. info->op_variants.read_cache);
  775. if (!op)
  776. return -ENOTSUPP;
  777. spinand->op_templates.read_cache = op;
  778. op = spinand_select_op_variant(spinand,
  779. info->op_variants.write_cache);
  780. if (!op)
  781. return -ENOTSUPP;
  782. spinand->op_templates.write_cache = op;
  783. op = spinand_select_op_variant(spinand,
  784. info->op_variants.update_cache);
  785. spinand->op_templates.update_cache = op;
  786. return 0;
  787. }
  788. return -ENOTSUPP;
  789. }
  790. static int spinand_detect(struct spinand_device *spinand)
  791. {
  792. struct nand_device *nand = spinand_to_nand(spinand);
  793. int ret;
  794. ret = spinand_reset_op(spinand);
  795. if (ret)
  796. return ret;
  797. ret = spinand_read_id_op(spinand, spinand->id.data);
  798. if (ret)
  799. return ret;
  800. spinand->id.len = SPINAND_MAX_ID_LEN;
  801. ret = spinand_manufacturer_detect(spinand);
  802. if (ret) {
  803. dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
  804. spinand->id.data);
  805. return ret;
  806. }
  807. if (nand->memorg.ntargets > 1 && !spinand->select_target) {
  808. dev_err(dev,
  809. "SPI NANDs with more than one die must implement ->select_target()\n");
  810. return -EINVAL;
  811. }
  812. dev_info(spinand->slave->dev,
  813. "%s SPI NAND was found.\n", spinand->manufacturer->name);
  814. dev_info(spinand->slave->dev,
  815. "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
  816. nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
  817. nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
  818. return 0;
  819. }
  820. static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
  821. struct mtd_oob_region *region)
  822. {
  823. return -ERANGE;
  824. }
  825. static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
  826. struct mtd_oob_region *region)
  827. {
  828. if (section)
  829. return -ERANGE;
  830. /* Reserve 2 bytes for the BBM. */
  831. region->offset = 2;
  832. region->length = 62;
  833. return 0;
  834. }
  835. static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
  836. .ecc = spinand_noecc_ooblayout_ecc,
  837. .rfree = spinand_noecc_ooblayout_free,
  838. };
  839. static int spinand_init(struct spinand_device *spinand)
  840. {
  841. struct mtd_info *mtd = spinand_to_mtd(spinand);
  842. struct nand_device *nand = mtd_to_nanddev(mtd);
  843. int ret, i;
  844. /*
  845. * We need a scratch buffer because the spi_mem interface requires that
  846. * buf passed in spi_mem_op->data.buf be DMA-able.
  847. */
  848. spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
  849. if (!spinand->scratchbuf)
  850. return -ENOMEM;
  851. ret = spinand_detect(spinand);
  852. if (ret)
  853. goto err_free_bufs;
  854. /*
  855. * Use kzalloc() instead of devm_kzalloc() here, because some drivers
  856. * may use this buffer for DMA access.
  857. * Memory allocated by devm_ does not guarantee DMA-safe alignment.
  858. */
  859. spinand->databuf = kzalloc(nanddev_page_size(nand) +
  860. nanddev_per_page_oobsize(nand),
  861. GFP_KERNEL);
  862. if (!spinand->databuf) {
  863. ret = -ENOMEM;
  864. goto err_free_bufs;
  865. }
  866. spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
  867. ret = spinand_init_cfg_cache(spinand);
  868. if (ret)
  869. goto err_free_bufs;
  870. ret = spinand_init_quad_enable(spinand);
  871. if (ret)
  872. goto err_free_bufs;
  873. ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0);
  874. if (ret)
  875. goto err_free_bufs;
  876. ret = spinand_manufacturer_init(spinand);
  877. if (ret) {
  878. dev_err(dev,
  879. "Failed to initialize the SPI NAND chip (err = %d)\n",
  880. ret);
  881. goto err_free_bufs;
  882. }
  883. /* After power up, all blocks are locked, so unlock them here. */
  884. for (i = 0; i < nand->memorg.ntargets; i++) {
  885. ret = spinand_select_target(spinand, i);
  886. if (ret)
  887. goto err_free_bufs;
  888. ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
  889. if (ret)
  890. goto err_free_bufs;
  891. }
  892. ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
  893. if (ret)
  894. goto err_manuf_cleanup;
  895. /*
  896. * Right now, we don't support ECC, so let the whole oob
  897. * area is available for user.
  898. */
  899. mtd->_read_oob = spinand_mtd_read;
  900. mtd->_write_oob = spinand_mtd_write;
  901. mtd->_block_isbad = spinand_mtd_block_isbad;
  902. mtd->_block_markbad = spinand_mtd_block_markbad;
  903. mtd->_block_isreserved = spinand_mtd_block_isreserved;
  904. mtd->_erase = spinand_mtd_erase;
  905. if (spinand->eccinfo.ooblayout)
  906. mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
  907. else
  908. mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
  909. ret = mtd_ooblayout_count_freebytes(mtd);
  910. if (ret < 0)
  911. goto err_cleanup_nanddev;
  912. mtd->oobavail = ret;
  913. return 0;
  914. err_cleanup_nanddev:
  915. nanddev_cleanup(nand);
  916. err_manuf_cleanup:
  917. spinand_manufacturer_cleanup(spinand);
  918. err_free_bufs:
  919. kfree(spinand->databuf);
  920. kfree(spinand->scratchbuf);
  921. return ret;
  922. }
  923. static void spinand_cleanup(struct spinand_device *spinand)
  924. {
  925. struct nand_device *nand = spinand_to_nand(spinand);
  926. nanddev_cleanup(nand);
  927. spinand_manufacturer_cleanup(spinand);
  928. kfree(spinand->databuf);
  929. kfree(spinand->scratchbuf);
  930. }
  931. static int spinand_probe(struct udevice *dev)
  932. {
  933. struct spinand_device *spinand = dev_get_priv(dev);
  934. struct spi_slave *slave = dev_get_parent_priv(dev);
  935. struct mtd_info *mtd = dev_get_uclass_priv(dev);
  936. struct nand_device *nand = spinand_to_nand(spinand);
  937. int ret;
  938. #ifndef __UBOOT__
  939. spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
  940. GFP_KERNEL);
  941. if (!spinand)
  942. return -ENOMEM;
  943. spinand->spimem = mem;
  944. spi_mem_set_drvdata(mem, spinand);
  945. spinand_set_of_node(spinand, mem->spi->dev.of_node);
  946. mutex_init(&spinand->lock);
  947. mtd = spinand_to_mtd(spinand);
  948. mtd->dev.parent = &mem->spi->dev;
  949. #else
  950. nand->mtd = mtd;
  951. mtd->priv = nand;
  952. mtd->dev = dev;
  953. mtd->name = malloc(20);
  954. if (!mtd->name)
  955. return -ENOMEM;
  956. sprintf(mtd->name, "spi-nand%d", spi_nand_idx++);
  957. spinand->slave = slave;
  958. spinand_set_of_node(spinand, dev->node.np);
  959. #endif
  960. ret = spinand_init(spinand);
  961. if (ret)
  962. return ret;
  963. #ifndef __UBOOT__
  964. ret = mtd_device_register(mtd, NULL, 0);
  965. #else
  966. ret = add_mtd_device(mtd);
  967. #endif
  968. if (ret)
  969. goto err_spinand_cleanup;
  970. return 0;
  971. err_spinand_cleanup:
  972. spinand_cleanup(spinand);
  973. return ret;
  974. }
  975. #ifndef __UBOOT__
  976. static int spinand_remove(struct udevice *slave)
  977. {
  978. struct spinand_device *spinand;
  979. struct mtd_info *mtd;
  980. int ret;
  981. spinand = spi_mem_get_drvdata(slave);
  982. mtd = spinand_to_mtd(spinand);
  983. free(mtd->name);
  984. ret = mtd_device_unregister(mtd);
  985. if (ret)
  986. return ret;
  987. spinand_cleanup(spinand);
  988. return 0;
  989. }
  990. static const struct spi_device_id spinand_ids[] = {
  991. { .name = "spi-nand" },
  992. { /* sentinel */ },
  993. };
  994. #ifdef CONFIG_OF
  995. static const struct of_device_id spinand_of_ids[] = {
  996. { .compatible = "spi-nand" },
  997. { /* sentinel */ },
  998. };
  999. #endif
  1000. static struct spi_mem_driver spinand_drv = {
  1001. .spidrv = {
  1002. .id_table = spinand_ids,
  1003. .driver = {
  1004. .name = "spi-nand",
  1005. .of_match_table = of_match_ptr(spinand_of_ids),
  1006. },
  1007. },
  1008. .probe = spinand_probe,
  1009. .remove = spinand_remove,
  1010. };
  1011. module_spi_mem_driver(spinand_drv);
  1012. MODULE_DESCRIPTION("SPI NAND framework");
  1013. MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>");
  1014. MODULE_LICENSE("GPL v2");
  1015. #endif /* __UBOOT__ */
  1016. static const struct udevice_id spinand_ids[] = {
  1017. { .compatible = "spi-nand" },
  1018. { /* sentinel */ },
  1019. };
  1020. U_BOOT_DRIVER(spinand) = {
  1021. .name = "spi_nand",
  1022. .id = UCLASS_MTD,
  1023. .of_match = spinand_ids,
  1024. .priv_auto_alloc_size = sizeof(struct spinand_device),
  1025. .probe = spinand_probe,
  1026. };