tegra_nand.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
  5. * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  6. * (C) Copyright 2006 DENX Software Engineering
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <memalign.h>
  12. #include <nand.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/funcmux.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bug.h>
  18. #include <linux/errno.h>
  19. #include <asm/gpio.h>
  20. #include <fdtdec.h>
  21. #include <bouncebuf.h>
  22. #include <dm.h>
  23. #include "tegra_nand.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define NAND_CMD_TIMEOUT_MS 10
  26. #define SKIPPED_SPARE_BYTES 4
  27. /* ECC bytes to be generated for tag data */
  28. #define TAG_ECC_BYTES 4
  29. static const struct udevice_id tegra_nand_dt_ids[] = {
  30. {
  31. .compatible = "nvidia,tegra20-nand",
  32. },
  33. { /* sentinel */ }
  34. };
  35. /* 64 byte oob block info for large page (== 2KB) device
  36. *
  37. * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  38. * Skipped bytes(4)
  39. * Main area Ecc(36)
  40. * Tag data(20)
  41. * Tag data Ecc(4)
  42. *
  43. * Yaffs2 will use 16 tag bytes.
  44. */
  45. static struct nand_ecclayout eccoob = {
  46. .eccbytes = 36,
  47. .eccpos = {
  48. 4, 5, 6, 7, 8, 9, 10, 11, 12,
  49. 13, 14, 15, 16, 17, 18, 19, 20, 21,
  50. 22, 23, 24, 25, 26, 27, 28, 29, 30,
  51. 31, 32, 33, 34, 35, 36, 37, 38, 39,
  52. },
  53. .oobavail = 20,
  54. .oobfree = {
  55. {
  56. .offset = 40,
  57. .length = 20,
  58. },
  59. }
  60. };
  61. enum {
  62. ECC_OK,
  63. ECC_TAG_ERROR = 1 << 0,
  64. ECC_DATA_ERROR = 1 << 1
  65. };
  66. /* Timing parameters */
  67. enum {
  68. FDT_NAND_MAX_TRP_TREA,
  69. FDT_NAND_TWB,
  70. FDT_NAND_MAX_TCR_TAR_TRR,
  71. FDT_NAND_TWHR,
  72. FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  73. FDT_NAND_TWH,
  74. FDT_NAND_TWP,
  75. FDT_NAND_TRH,
  76. FDT_NAND_TADL,
  77. FDT_NAND_TIMING_COUNT
  78. };
  79. /* Information about an attached NAND chip */
  80. struct fdt_nand {
  81. struct nand_ctlr *reg;
  82. int enabled; /* 1 to enable, 0 to disable */
  83. struct gpio_desc wp_gpio; /* write-protect GPIO */
  84. s32 width; /* bit width, normally 8 */
  85. u32 timing[FDT_NAND_TIMING_COUNT];
  86. };
  87. struct nand_drv {
  88. struct nand_ctlr *reg;
  89. struct fdt_nand config;
  90. };
  91. struct tegra_nand_info {
  92. struct udevice *dev;
  93. struct nand_drv nand_ctrl;
  94. struct nand_chip nand_chip;
  95. };
  96. /**
  97. * Wait for command completion
  98. *
  99. * @param reg nand_ctlr structure
  100. * @return
  101. * 1 - Command completed
  102. * 0 - Timeout
  103. */
  104. static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  105. {
  106. u32 reg_val;
  107. int running;
  108. int i;
  109. for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
  110. if ((readl(&reg->command) & CMD_GO) ||
  111. !(readl(&reg->status) & STATUS_RBSY0) ||
  112. !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
  113. udelay(1);
  114. continue;
  115. }
  116. reg_val = readl(&reg->dma_mst_ctrl);
  117. /*
  118. * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
  119. * is set, that means DMA engine is running.
  120. *
  121. * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
  122. * is cleared, indicating DMA transfer completion.
  123. */
  124. running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
  125. DMA_MST_CTRL_EN_B_ENABLE);
  126. if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
  127. return 1;
  128. udelay(1);
  129. }
  130. return 0;
  131. }
  132. /**
  133. * Read one byte from the chip
  134. *
  135. * @param mtd MTD device structure
  136. * @return data byte
  137. *
  138. * Read function for 8bit bus-width
  139. */
  140. static uint8_t read_byte(struct mtd_info *mtd)
  141. {
  142. struct nand_chip *chip = mtd_to_nand(mtd);
  143. struct nand_drv *info;
  144. info = (struct nand_drv *)nand_get_controller_data(chip);
  145. writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
  146. &info->reg->command);
  147. if (!nand_waitfor_cmd_completion(info->reg))
  148. printf("Command timeout\n");
  149. return (uint8_t)readl(&info->reg->resp);
  150. }
  151. /**
  152. * Read len bytes from the chip into a buffer
  153. *
  154. * @param mtd MTD device structure
  155. * @param buf buffer to store data to
  156. * @param len number of bytes to read
  157. *
  158. * Read function for 8bit bus-width
  159. */
  160. static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  161. {
  162. int i, s;
  163. unsigned int reg;
  164. struct nand_chip *chip = mtd_to_nand(mtd);
  165. struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
  166. for (i = 0; i < len; i += 4) {
  167. s = (len - i) > 4 ? 4 : len - i;
  168. writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
  169. ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
  170. &info->reg->command);
  171. if (!nand_waitfor_cmd_completion(info->reg))
  172. puts("Command timeout during read_buf\n");
  173. reg = readl(&info->reg->resp);
  174. memcpy(buf + i, &reg, s);
  175. }
  176. }
  177. /**
  178. * Check NAND status to see if it is ready or not
  179. *
  180. * @param mtd MTD device structure
  181. * @return
  182. * 1 - ready
  183. * 0 - not ready
  184. */
  185. static int nand_dev_ready(struct mtd_info *mtd)
  186. {
  187. struct nand_chip *chip = mtd_to_nand(mtd);
  188. int reg_val;
  189. struct nand_drv *info;
  190. info = (struct nand_drv *)nand_get_controller_data(chip);
  191. reg_val = readl(&info->reg->status);
  192. if (reg_val & STATUS_RBSY0)
  193. return 1;
  194. else
  195. return 0;
  196. }
  197. /* Dummy implementation: we don't support multiple chips */
  198. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  199. {
  200. switch (chipnr) {
  201. case -1:
  202. case 0:
  203. break;
  204. default:
  205. BUG();
  206. }
  207. }
  208. /**
  209. * Clear all interrupt status bits
  210. *
  211. * @param reg nand_ctlr structure
  212. */
  213. static void nand_clear_interrupt_status(struct nand_ctlr *reg)
  214. {
  215. u32 reg_val;
  216. /* Clear interrupt status */
  217. reg_val = readl(&reg->isr);
  218. writel(reg_val, &reg->isr);
  219. }
  220. /**
  221. * Send command to NAND device
  222. *
  223. * @param mtd MTD device structure
  224. * @param command the command to be sent
  225. * @param column the column address for this command, -1 if none
  226. * @param page_addr the page address for this command, -1 if none
  227. */
  228. static void nand_command(struct mtd_info *mtd, unsigned int command,
  229. int column, int page_addr)
  230. {
  231. struct nand_chip *chip = mtd_to_nand(mtd);
  232. struct nand_drv *info;
  233. info = (struct nand_drv *)nand_get_controller_data(chip);
  234. /*
  235. * Write out the command to the device.
  236. *
  237. * Only command NAND_CMD_RESET or NAND_CMD_READID will come
  238. * here before mtd->writesize is initialized.
  239. */
  240. /* Emulate NAND_CMD_READOOB */
  241. if (command == NAND_CMD_READOOB) {
  242. assert(mtd->writesize != 0);
  243. column += mtd->writesize;
  244. command = NAND_CMD_READ0;
  245. }
  246. /* Adjust columns for 16 bit bus-width */
  247. if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
  248. column >>= 1;
  249. nand_clear_interrupt_status(info->reg);
  250. /* Stop DMA engine, clear DMA completion status */
  251. writel(DMA_MST_CTRL_EN_A_DISABLE
  252. | DMA_MST_CTRL_EN_B_DISABLE
  253. | DMA_MST_CTRL_IS_DMA_DONE,
  254. &info->reg->dma_mst_ctrl);
  255. /*
  256. * Program and erase have their own busy handlers
  257. * status and sequential in needs no delay
  258. */
  259. switch (command) {
  260. case NAND_CMD_READID:
  261. writel(NAND_CMD_READID, &info->reg->cmd_reg1);
  262. writel(column & 0xFF, &info->reg->addr_reg1);
  263. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  264. &info->reg->command);
  265. break;
  266. case NAND_CMD_PARAM:
  267. writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
  268. writel(column & 0xFF, &info->reg->addr_reg1);
  269. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  270. &info->reg->command);
  271. break;
  272. case NAND_CMD_READ0:
  273. writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
  274. writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
  275. writel((page_addr << 16) | (column & 0xFFFF),
  276. &info->reg->addr_reg1);
  277. writel(page_addr >> 16, &info->reg->addr_reg2);
  278. return;
  279. case NAND_CMD_SEQIN:
  280. writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
  281. writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
  282. writel((page_addr << 16) | (column & 0xFFFF),
  283. &info->reg->addr_reg1);
  284. writel(page_addr >> 16,
  285. &info->reg->addr_reg2);
  286. return;
  287. case NAND_CMD_PAGEPROG:
  288. return;
  289. case NAND_CMD_ERASE1:
  290. writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
  291. writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
  292. writel(page_addr, &info->reg->addr_reg1);
  293. writel(CMD_GO | CMD_CLE | CMD_ALE |
  294. CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
  295. &info->reg->command);
  296. break;
  297. case NAND_CMD_ERASE2:
  298. return;
  299. case NAND_CMD_STATUS:
  300. writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
  301. writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
  302. | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
  303. | CMD_CE0,
  304. &info->reg->command);
  305. break;
  306. case NAND_CMD_RESET:
  307. writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
  308. writel(CMD_GO | CMD_CLE | CMD_CE0,
  309. &info->reg->command);
  310. break;
  311. case NAND_CMD_RNDOUT:
  312. default:
  313. printf("%s: Unsupported command %d\n", __func__, command);
  314. return;
  315. }
  316. if (!nand_waitfor_cmd_completion(info->reg))
  317. printf("Command 0x%02X timeout\n", command);
  318. }
  319. /**
  320. * Check whether the pointed buffer are all 0xff (blank).
  321. *
  322. * @param buf data buffer for blank check
  323. * @param len length of the buffer in byte
  324. * @return
  325. * 1 - blank
  326. * 0 - non-blank
  327. */
  328. static int blank_check(u8 *buf, int len)
  329. {
  330. int i;
  331. for (i = 0; i < len; i++)
  332. if (buf[i] != 0xFF)
  333. return 0;
  334. return 1;
  335. }
  336. /**
  337. * After a DMA transfer for read, we call this function to see whether there
  338. * is any uncorrectable error on the pointed data buffer or oob buffer.
  339. *
  340. * @param reg nand_ctlr structure
  341. * @param databuf data buffer
  342. * @param a_len data buffer length
  343. * @param oobbuf oob buffer
  344. * @param b_len oob buffer length
  345. * @return
  346. * ECC_OK - no ECC error or correctable ECC error
  347. * ECC_TAG_ERROR - uncorrectable tag ECC error
  348. * ECC_DATA_ERROR - uncorrectable data ECC error
  349. * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
  350. */
  351. static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
  352. int a_len, u8 *oobbuf, int b_len)
  353. {
  354. int return_val = ECC_OK;
  355. u32 reg_val;
  356. if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
  357. return ECC_OK;
  358. /*
  359. * Area A is used for the data block (databuf). Area B is used for
  360. * the spare block (oobbuf)
  361. */
  362. reg_val = readl(&reg->dec_status);
  363. if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
  364. reg_val = readl(&reg->bch_dec_status_buf);
  365. /*
  366. * If uncorrectable error occurs on data area, then see whether
  367. * they are all FF. If all are FF, it's a blank page.
  368. * Not error.
  369. */
  370. if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
  371. !blank_check(databuf, a_len))
  372. return_val |= ECC_DATA_ERROR;
  373. }
  374. if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
  375. reg_val = readl(&reg->bch_dec_status_buf);
  376. /*
  377. * If uncorrectable error occurs on tag area, then see whether
  378. * they are all FF. If all are FF, it's a blank page.
  379. * Not error.
  380. */
  381. if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
  382. !blank_check(oobbuf, b_len))
  383. return_val |= ECC_TAG_ERROR;
  384. }
  385. return return_val;
  386. }
  387. /**
  388. * Set GO bit to send command to device
  389. *
  390. * @param reg nand_ctlr structure
  391. */
  392. static void start_command(struct nand_ctlr *reg)
  393. {
  394. u32 reg_val;
  395. reg_val = readl(&reg->command);
  396. reg_val |= CMD_GO;
  397. writel(reg_val, &reg->command);
  398. }
  399. /**
  400. * Clear command GO bit, DMA GO bit, and DMA completion status
  401. *
  402. * @param reg nand_ctlr structure
  403. */
  404. static void stop_command(struct nand_ctlr *reg)
  405. {
  406. /* Stop command */
  407. writel(0, &reg->command);
  408. /* Stop DMA engine and clear DMA completion status */
  409. writel(DMA_MST_CTRL_GO_DISABLE
  410. | DMA_MST_CTRL_IS_DMA_DONE,
  411. &reg->dma_mst_ctrl);
  412. }
  413. /**
  414. * Set up NAND bus width and page size
  415. *
  416. * @param info nand_info structure
  417. * @param *reg_val address of reg_val
  418. * @return 0 if ok, -1 on error
  419. */
  420. static int set_bus_width_page_size(struct mtd_info *our_mtd,
  421. struct fdt_nand *config, u32 *reg_val)
  422. {
  423. if (config->width == 8)
  424. *reg_val = CFG_BUS_WIDTH_8BIT;
  425. else if (config->width == 16)
  426. *reg_val = CFG_BUS_WIDTH_16BIT;
  427. else {
  428. debug("%s: Unsupported bus width %d\n", __func__,
  429. config->width);
  430. return -1;
  431. }
  432. if (our_mtd->writesize == 512)
  433. *reg_val |= CFG_PAGE_SIZE_512;
  434. else if (our_mtd->writesize == 2048)
  435. *reg_val |= CFG_PAGE_SIZE_2048;
  436. else if (our_mtd->writesize == 4096)
  437. *reg_val |= CFG_PAGE_SIZE_4096;
  438. else {
  439. debug("%s: Unsupported page size %d\n", __func__,
  440. our_mtd->writesize);
  441. return -1;
  442. }
  443. return 0;
  444. }
  445. /**
  446. * Page read/write function
  447. *
  448. * @param mtd mtd info structure
  449. * @param chip nand chip info structure
  450. * @param buf data buffer
  451. * @param page page number
  452. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  453. * @param is_writing 0 for read, 1 for write
  454. * @return 0 when successfully completed
  455. * -EIO when command timeout
  456. */
  457. static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
  458. uint8_t *buf, int page, int with_ecc, int is_writing)
  459. {
  460. u32 reg_val;
  461. int tag_size;
  462. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  463. /* 4*128=512 (byte) is the value that our HW can support. */
  464. ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
  465. char *tag_ptr;
  466. struct nand_drv *info;
  467. struct fdt_nand *config;
  468. unsigned int bbflags;
  469. struct bounce_buffer bbstate, bbstate_oob;
  470. if ((uintptr_t)buf & 0x03) {
  471. printf("buf %p has to be 4-byte aligned\n", buf);
  472. return -EINVAL;
  473. }
  474. info = (struct nand_drv *)nand_get_controller_data(chip);
  475. config = &info->config;
  476. if (set_bus_width_page_size(mtd, config, &reg_val))
  477. return -EINVAL;
  478. /* Need to be 4-byte aligned */
  479. tag_ptr = (char *)tag_buf;
  480. stop_command(info->reg);
  481. if (is_writing)
  482. bbflags = GEN_BB_READ;
  483. else
  484. bbflags = GEN_BB_WRITE;
  485. bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
  486. bbflags);
  487. writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
  488. writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
  489. /* Set ECC selection, configure ECC settings */
  490. if (with_ecc) {
  491. if (is_writing)
  492. memcpy(tag_ptr, chip->oob_poi + free->offset,
  493. chip->ecc.layout->oobavail + TAG_ECC_BYTES);
  494. tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
  495. reg_val |= (CFG_SKIP_SPARE_SEL_4
  496. | CFG_SKIP_SPARE_ENABLE
  497. | CFG_HW_ECC_CORRECTION_ENABLE
  498. | CFG_ECC_EN_TAG_DISABLE
  499. | CFG_HW_ECC_SEL_RS
  500. | CFG_HW_ECC_ENABLE
  501. | CFG_TVAL4
  502. | (tag_size - 1));
  503. if (!is_writing)
  504. tag_size += SKIPPED_SPARE_BYTES;
  505. bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
  506. bbflags);
  507. } else {
  508. tag_size = mtd->oobsize;
  509. reg_val |= (CFG_SKIP_SPARE_DISABLE
  510. | CFG_HW_ECC_CORRECTION_DISABLE
  511. | CFG_ECC_EN_TAG_DISABLE
  512. | CFG_HW_ECC_DISABLE
  513. | (tag_size - 1));
  514. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
  515. tag_size, bbflags);
  516. }
  517. writel(reg_val, &info->reg->config);
  518. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  519. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  520. writel(tag_size - 1, &info->reg->dma_cfg_b);
  521. nand_clear_interrupt_status(info->reg);
  522. reg_val = CMD_CLE | CMD_ALE
  523. | CMD_SEC_CMD
  524. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  525. | CMD_A_VALID
  526. | CMD_B_VALID
  527. | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
  528. | CMD_CE0;
  529. if (!is_writing)
  530. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  531. else
  532. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  533. writel(reg_val, &info->reg->command);
  534. /* Setup DMA engine */
  535. reg_val = DMA_MST_CTRL_GO_ENABLE
  536. | DMA_MST_CTRL_BURST_8WORDS
  537. | DMA_MST_CTRL_EN_A_ENABLE
  538. | DMA_MST_CTRL_EN_B_ENABLE;
  539. if (!is_writing)
  540. reg_val |= DMA_MST_CTRL_DIR_READ;
  541. else
  542. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  543. writel(reg_val, &info->reg->dma_mst_ctrl);
  544. start_command(info->reg);
  545. if (!nand_waitfor_cmd_completion(info->reg)) {
  546. if (!is_writing)
  547. printf("Read Page 0x%X timeout ", page);
  548. else
  549. printf("Write Page 0x%X timeout ", page);
  550. if (with_ecc)
  551. printf("with ECC");
  552. else
  553. printf("without ECC");
  554. printf("\n");
  555. return -EIO;
  556. }
  557. bounce_buffer_stop(&bbstate_oob);
  558. bounce_buffer_stop(&bbstate);
  559. if (with_ecc && !is_writing) {
  560. memcpy(chip->oob_poi, tag_ptr,
  561. SKIPPED_SPARE_BYTES);
  562. memcpy(chip->oob_poi + free->offset,
  563. tag_ptr + SKIPPED_SPARE_BYTES,
  564. chip->ecc.layout->oobavail);
  565. reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
  566. 1 << chip->page_shift,
  567. (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
  568. chip->ecc.layout->oobavail);
  569. if (reg_val & ECC_TAG_ERROR)
  570. printf("Read Page 0x%X tag ECC error\n", page);
  571. if (reg_val & ECC_DATA_ERROR)
  572. printf("Read Page 0x%X data ECC error\n",
  573. page);
  574. if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
  575. return -EIO;
  576. }
  577. return 0;
  578. }
  579. /**
  580. * Hardware ecc based page read function
  581. *
  582. * @param mtd mtd info structure
  583. * @param chip nand chip info structure
  584. * @param buf buffer to store read data
  585. * @param page page number to read
  586. * @return 0 when successfully completed
  587. * -EIO when command timeout
  588. */
  589. static int nand_read_page_hwecc(struct mtd_info *mtd,
  590. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  591. {
  592. return nand_rw_page(mtd, chip, buf, page, 1, 0);
  593. }
  594. /**
  595. * Hardware ecc based page write function
  596. *
  597. * @param mtd mtd info structure
  598. * @param chip nand chip info structure
  599. * @param buf data buffer
  600. */
  601. static int nand_write_page_hwecc(struct mtd_info *mtd,
  602. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  603. int page)
  604. {
  605. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
  606. return 0;
  607. }
  608. /**
  609. * Read raw page data without ecc
  610. *
  611. * @param mtd mtd info structure
  612. * @param chip nand chip info structure
  613. * @param buf buffer to store read data
  614. * @param page page number to read
  615. * @return 0 when successfully completed
  616. * -EINVAL when chip->oob_poi is not double-word aligned
  617. * -EIO when command timeout
  618. */
  619. static int nand_read_page_raw(struct mtd_info *mtd,
  620. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  621. {
  622. return nand_rw_page(mtd, chip, buf, page, 0, 0);
  623. }
  624. /**
  625. * Raw page write function
  626. *
  627. * @param mtd mtd info structure
  628. * @param chip nand chip info structure
  629. * @param buf data buffer
  630. */
  631. static int nand_write_page_raw(struct mtd_info *mtd,
  632. struct nand_chip *chip, const uint8_t *buf,
  633. int oob_required, int page)
  634. {
  635. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
  636. return 0;
  637. }
  638. /**
  639. * OOB data read/write function
  640. *
  641. * @param mtd mtd info structure
  642. * @param chip nand chip info structure
  643. * @param page page number to read
  644. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  645. * @param is_writing 0 for read, 1 for write
  646. * @return 0 when successfully completed
  647. * -EINVAL when chip->oob_poi is not double-word aligned
  648. * -EIO when command timeout
  649. */
  650. static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
  651. int page, int with_ecc, int is_writing)
  652. {
  653. u32 reg_val;
  654. int tag_size;
  655. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  656. struct nand_drv *info;
  657. unsigned int bbflags;
  658. struct bounce_buffer bbstate_oob;
  659. if (((int)chip->oob_poi) & 0x03)
  660. return -EINVAL;
  661. info = (struct nand_drv *)nand_get_controller_data(chip);
  662. if (set_bus_width_page_size(mtd, &info->config, &reg_val))
  663. return -EINVAL;
  664. stop_command(info->reg);
  665. /* Set ECC selection */
  666. tag_size = mtd->oobsize;
  667. if (with_ecc)
  668. reg_val |= CFG_ECC_EN_TAG_ENABLE;
  669. else
  670. reg_val |= (CFG_ECC_EN_TAG_DISABLE);
  671. reg_val |= ((tag_size - 1) |
  672. CFG_SKIP_SPARE_DISABLE |
  673. CFG_HW_ECC_CORRECTION_DISABLE |
  674. CFG_HW_ECC_DISABLE);
  675. writel(reg_val, &info->reg->config);
  676. if (is_writing && with_ecc)
  677. tag_size -= TAG_ECC_BYTES;
  678. if (is_writing)
  679. bbflags = GEN_BB_READ;
  680. else
  681. bbflags = GEN_BB_WRITE;
  682. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
  683. bbflags);
  684. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  685. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  686. writel(tag_size - 1, &info->reg->dma_cfg_b);
  687. nand_clear_interrupt_status(info->reg);
  688. reg_val = CMD_CLE | CMD_ALE
  689. | CMD_SEC_CMD
  690. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  691. | CMD_B_VALID
  692. | CMD_CE0;
  693. if (!is_writing)
  694. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  695. else
  696. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  697. writel(reg_val, &info->reg->command);
  698. /* Setup DMA engine */
  699. reg_val = DMA_MST_CTRL_GO_ENABLE
  700. | DMA_MST_CTRL_BURST_8WORDS
  701. | DMA_MST_CTRL_EN_B_ENABLE;
  702. if (!is_writing)
  703. reg_val |= DMA_MST_CTRL_DIR_READ;
  704. else
  705. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  706. writel(reg_val, &info->reg->dma_mst_ctrl);
  707. start_command(info->reg);
  708. if (!nand_waitfor_cmd_completion(info->reg)) {
  709. if (!is_writing)
  710. printf("Read OOB of Page 0x%X timeout\n", page);
  711. else
  712. printf("Write OOB of Page 0x%X timeout\n", page);
  713. return -EIO;
  714. }
  715. bounce_buffer_stop(&bbstate_oob);
  716. if (with_ecc && !is_writing) {
  717. reg_val = (u32)check_ecc_error(info->reg, 0, 0,
  718. (u8 *)(chip->oob_poi + free->offset),
  719. chip->ecc.layout->oobavail);
  720. if (reg_val & ECC_TAG_ERROR)
  721. printf("Read OOB of Page 0x%X tag ECC error\n", page);
  722. }
  723. return 0;
  724. }
  725. /**
  726. * OOB data read function
  727. *
  728. * @param mtd mtd info structure
  729. * @param chip nand chip info structure
  730. * @param page page number to read
  731. */
  732. static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  733. int page)
  734. {
  735. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  736. nand_rw_oob(mtd, chip, page, 0, 0);
  737. return 0;
  738. }
  739. /**
  740. * OOB data write function
  741. *
  742. * @param mtd mtd info structure
  743. * @param chip nand chip info structure
  744. * @param page page number to write
  745. * @return 0 when successfully completed
  746. * -EINVAL when chip->oob_poi is not double-word aligned
  747. * -EIO when command timeout
  748. */
  749. static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  750. int page)
  751. {
  752. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  753. return nand_rw_oob(mtd, chip, page, 0, 1);
  754. }
  755. /**
  756. * Set up NAND memory timings according to the provided parameters
  757. *
  758. * @param timing Timing parameters
  759. * @param reg NAND controller register address
  760. */
  761. static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
  762. struct nand_ctlr *reg)
  763. {
  764. u32 reg_val, clk_rate, clk_period, time_val;
  765. clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
  766. CLOCK_ID_PERIPH) / 1000000;
  767. clk_period = 1000 / clk_rate;
  768. reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  769. TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
  770. reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
  771. TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
  772. time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
  773. if (time_val > 2)
  774. reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
  775. TIMING_TCR_TAR_TRR_CNT_MASK;
  776. reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
  777. TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
  778. time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
  779. if (time_val > 1)
  780. reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
  781. TIMING_TCS_CNT_MASK;
  782. reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
  783. TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
  784. reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
  785. TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
  786. reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
  787. TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
  788. reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  789. TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
  790. writel(reg_val, &reg->timing);
  791. reg_val = 0;
  792. time_val = timing[FDT_NAND_TADL] / clk_period;
  793. if (time_val > 2)
  794. reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
  795. writel(reg_val, &reg->timing2);
  796. }
  797. /**
  798. * Decode NAND parameters from the device tree
  799. *
  800. * @param dev Driver model device
  801. * @param config Device tree NAND configuration
  802. * @return 0 if ok, -ve on error (FDT_ERR_...)
  803. */
  804. static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
  805. {
  806. int err;
  807. config->reg = (struct nand_ctlr *)dev_read_addr(dev);
  808. config->enabled = dev_read_enabled(dev);
  809. config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
  810. err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
  811. GPIOD_IS_OUT);
  812. if (err)
  813. return err;
  814. err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
  815. FDT_NAND_TIMING_COUNT);
  816. if (err < 0)
  817. return err;
  818. return 0;
  819. }
  820. static int tegra_probe(struct udevice *dev)
  821. {
  822. struct tegra_nand_info *tegra = dev_get_priv(dev);
  823. struct nand_chip *nand = &tegra->nand_chip;
  824. struct nand_drv *info = &tegra->nand_ctrl;
  825. struct fdt_nand *config = &info->config;
  826. struct mtd_info *our_mtd;
  827. int ret;
  828. if (fdt_decode_nand(dev, config)) {
  829. printf("Could not decode nand-flash in device tree\n");
  830. return -1;
  831. }
  832. if (!config->enabled)
  833. return -1;
  834. info->reg = config->reg;
  835. nand->ecc.mode = NAND_ECC_HW;
  836. nand->ecc.layout = &eccoob;
  837. nand->options = LP_OPTIONS;
  838. nand->cmdfunc = nand_command;
  839. nand->read_byte = read_byte;
  840. nand->read_buf = read_buf;
  841. nand->ecc.read_page = nand_read_page_hwecc;
  842. nand->ecc.write_page = nand_write_page_hwecc;
  843. nand->ecc.read_page_raw = nand_read_page_raw;
  844. nand->ecc.write_page_raw = nand_write_page_raw;
  845. nand->ecc.read_oob = nand_read_oob;
  846. nand->ecc.write_oob = nand_write_oob;
  847. nand->ecc.strength = 1;
  848. nand->select_chip = nand_select_chip;
  849. nand->dev_ready = nand_dev_ready;
  850. nand_set_controller_data(nand, &tegra->nand_ctrl);
  851. /* Disable subpage writes as we do not provide ecc->hwctl */
  852. nand->options |= NAND_NO_SUBPAGE_WRITE;
  853. /* Adjust controller clock rate */
  854. clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
  855. /* Adjust timing for NAND device */
  856. setup_timing(config->timing, info->reg);
  857. dm_gpio_set_value(&config->wp_gpio, 1);
  858. our_mtd = nand_to_mtd(nand);
  859. ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  860. if (ret)
  861. return ret;
  862. nand->ecc.size = our_mtd->writesize;
  863. nand->ecc.bytes = our_mtd->oobsize;
  864. ret = nand_scan_tail(our_mtd);
  865. if (ret)
  866. return ret;
  867. ret = nand_register(0, our_mtd);
  868. if (ret) {
  869. dev_err(dev, "Failed to register MTD: %d\n", ret);
  870. return ret;
  871. }
  872. return 0;
  873. }
  874. U_BOOT_DRIVER(tegra_nand) = {
  875. .name = "tegra-nand",
  876. .id = UCLASS_MTD,
  877. .of_match = tegra_nand_dt_ids,
  878. .probe = tegra_probe,
  879. .priv_auto_alloc_size = sizeof(struct tegra_nand_info),
  880. };
  881. void board_nand_init(void)
  882. {
  883. struct udevice *dev;
  884. int ret;
  885. ret = uclass_get_device_by_driver(UCLASS_MTD,
  886. DM_GET_DRIVER(tegra_nand), &dev);
  887. if (ret && ret != -ENODEV)
  888. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  889. ret);
  890. }