pxa3xx_nand.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/mtd/nand/raw/pxa3xx_nand.c
  4. *
  5. * Copyright © 2005 Intel Corporation
  6. * Copyright © 2006 Marvell International Ltd.
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <fdtdec.h>
  11. #include <nand.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/bug.h>
  15. #include <linux/err.h>
  16. #include <linux/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/cpu.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/rawnand.h>
  21. #include <linux/types.h>
  22. #include "pxa3xx_nand.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  25. #define CHIP_DELAY_TIMEOUT 200
  26. #define NAND_STOP_DELAY 40
  27. /*
  28. * Define a buffer size for the initial command that detects the flash device:
  29. * STATUS, READID and PARAM.
  30. * ONFI param page is 256 bytes, and there are three redundant copies
  31. * to be read. JEDEC param page is 512 bytes, and there are also three
  32. * redundant copies to be read.
  33. * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  34. */
  35. #define INIT_BUFFER_SIZE 2048
  36. /* registers and bit definitions */
  37. #define NDCR (0x00) /* Control register */
  38. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  39. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  40. #define NDSR (0x14) /* Status Register */
  41. #define NDPCR (0x18) /* Page Count Register */
  42. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  43. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  44. #define NDECCCTRL (0x28) /* ECC control */
  45. #define NDDB (0x40) /* Data Buffer */
  46. #define NDCB0 (0x48) /* Command Buffer0 */
  47. #define NDCB1 (0x4C) /* Command Buffer1 */
  48. #define NDCB2 (0x50) /* Command Buffer2 */
  49. #define NDCR_SPARE_EN (0x1 << 31)
  50. #define NDCR_ECC_EN (0x1 << 30)
  51. #define NDCR_DMA_EN (0x1 << 29)
  52. #define NDCR_ND_RUN (0x1 << 28)
  53. #define NDCR_DWIDTH_C (0x1 << 27)
  54. #define NDCR_DWIDTH_M (0x1 << 26)
  55. #define NDCR_PAGE_SZ (0x1 << 24)
  56. #define NDCR_NCSX (0x1 << 23)
  57. #define NDCR_ND_MODE (0x3 << 21)
  58. #define NDCR_NAND_MODE (0x0)
  59. #define NDCR_CLR_PG_CNT (0x1 << 20)
  60. #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
  61. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  62. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  63. #define NDCR_RA_START (0x1 << 15)
  64. #define NDCR_PG_PER_BLK (0x1 << 14)
  65. #define NDCR_ND_ARB_EN (0x1 << 12)
  66. #define NDCR_INT_MASK (0xFFF)
  67. #define NDSR_MASK (0xfff)
  68. #define NDSR_ERR_CNT_OFF (16)
  69. #define NDSR_ERR_CNT_MASK (0x1f)
  70. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  71. #define NDSR_RDY (0x1 << 12)
  72. #define NDSR_FLASH_RDY (0x1 << 11)
  73. #define NDSR_CS0_PAGED (0x1 << 10)
  74. #define NDSR_CS1_PAGED (0x1 << 9)
  75. #define NDSR_CS0_CMDD (0x1 << 8)
  76. #define NDSR_CS1_CMDD (0x1 << 7)
  77. #define NDSR_CS0_BBD (0x1 << 6)
  78. #define NDSR_CS1_BBD (0x1 << 5)
  79. #define NDSR_UNCORERR (0x1 << 4)
  80. #define NDSR_CORERR (0x1 << 3)
  81. #define NDSR_WRDREQ (0x1 << 2)
  82. #define NDSR_RDDREQ (0x1 << 1)
  83. #define NDSR_WRCMDREQ (0x1)
  84. #define NDCB0_LEN_OVRD (0x1 << 28)
  85. #define NDCB0_ST_ROW_EN (0x1 << 26)
  86. #define NDCB0_AUTO_RS (0x1 << 25)
  87. #define NDCB0_CSEL (0x1 << 24)
  88. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  89. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  90. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  91. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  92. #define NDCB0_NC (0x1 << 20)
  93. #define NDCB0_DBC (0x1 << 19)
  94. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  95. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  96. #define NDCB0_CMD2_MASK (0xff << 8)
  97. #define NDCB0_CMD1_MASK (0xff)
  98. #define NDCB0_ADDR_CYC_SHIFT (16)
  99. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  100. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  101. #define EXT_CMD_TYPE_READ 4 /* Read */
  102. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  103. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  104. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  105. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  106. /*
  107. * This should be large enough to read 'ONFI' and 'JEDEC'.
  108. * Let's use 7 bytes, which is the maximum ID count supported
  109. * by the controller (see NDCR_RD_ID_CNT_MASK).
  110. */
  111. #define READ_ID_BYTES 7
  112. /* macros for registers read/write */
  113. #define nand_writel(info, off, val) \
  114. writel((val), (info)->mmio_base + (off))
  115. #define nand_readl(info, off) \
  116. readl((info)->mmio_base + (off))
  117. /* error code and state */
  118. enum {
  119. ERR_NONE = 0,
  120. ERR_DMABUSERR = -1,
  121. ERR_SENDCMD = -2,
  122. ERR_UNCORERR = -3,
  123. ERR_BBERR = -4,
  124. ERR_CORERR = -5,
  125. };
  126. enum {
  127. STATE_IDLE = 0,
  128. STATE_PREPARED,
  129. STATE_CMD_HANDLE,
  130. STATE_DMA_READING,
  131. STATE_DMA_WRITING,
  132. STATE_DMA_DONE,
  133. STATE_PIO_READING,
  134. STATE_PIO_WRITING,
  135. STATE_CMD_DONE,
  136. STATE_READY,
  137. };
  138. enum pxa3xx_nand_variant {
  139. PXA3XX_NAND_VARIANT_PXA,
  140. PXA3XX_NAND_VARIANT_ARMADA370,
  141. };
  142. struct pxa3xx_nand_host {
  143. struct nand_chip chip;
  144. void *info_data;
  145. /* page size of attached chip */
  146. int use_ecc;
  147. int cs;
  148. /* calculated from pxa3xx_nand_flash data */
  149. unsigned int col_addr_cycles;
  150. unsigned int row_addr_cycles;
  151. };
  152. struct pxa3xx_nand_info {
  153. struct nand_hw_control controller;
  154. struct pxa3xx_nand_platform_data *pdata;
  155. struct clk *clk;
  156. void __iomem *mmio_base;
  157. unsigned long mmio_phys;
  158. int cmd_complete, dev_ready;
  159. unsigned int buf_start;
  160. unsigned int buf_count;
  161. unsigned int buf_size;
  162. unsigned int data_buff_pos;
  163. unsigned int oob_buff_pos;
  164. unsigned char *data_buff;
  165. unsigned char *oob_buff;
  166. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  167. unsigned int state;
  168. /*
  169. * This driver supports NFCv1 (as found in PXA SoC)
  170. * and NFCv2 (as found in Armada 370/XP SoC).
  171. */
  172. enum pxa3xx_nand_variant variant;
  173. int cs;
  174. int use_ecc; /* use HW ECC ? */
  175. int force_raw; /* prevent use_ecc to be set */
  176. int ecc_bch; /* using BCH ECC? */
  177. int use_spare; /* use spare ? */
  178. int need_wait;
  179. /* Amount of real data per full chunk */
  180. unsigned int chunk_size;
  181. /* Amount of spare data per full chunk */
  182. unsigned int spare_size;
  183. /* Number of full chunks (i.e chunk_size + spare_size) */
  184. unsigned int nfullchunks;
  185. /*
  186. * Total number of chunks. If equal to nfullchunks, then there
  187. * are only full chunks. Otherwise, there is one last chunk of
  188. * size (last_chunk_size + last_spare_size)
  189. */
  190. unsigned int ntotalchunks;
  191. /* Amount of real data in the last chunk */
  192. unsigned int last_chunk_size;
  193. /* Amount of spare data in the last chunk */
  194. unsigned int last_spare_size;
  195. unsigned int ecc_size;
  196. unsigned int ecc_err_cnt;
  197. unsigned int max_bitflips;
  198. int retcode;
  199. /*
  200. * Variables only valid during command
  201. * execution. step_chunk_size and step_spare_size is the
  202. * amount of real data and spare data in the current
  203. * chunk. cur_chunk is the current chunk being
  204. * read/programmed.
  205. */
  206. unsigned int step_chunk_size;
  207. unsigned int step_spare_size;
  208. unsigned int cur_chunk;
  209. /* cached register value */
  210. uint32_t reg_ndcr;
  211. uint32_t ndtr0cs0;
  212. uint32_t ndtr1cs0;
  213. /* generated NDCBx register values */
  214. uint32_t ndcb0;
  215. uint32_t ndcb1;
  216. uint32_t ndcb2;
  217. uint32_t ndcb3;
  218. };
  219. static struct pxa3xx_nand_timing timing[] = {
  220. /*
  221. * tCH Enable signal hold time
  222. * tCS Enable signal setup time
  223. * tWH ND_nWE high duration
  224. * tWP ND_nWE pulse time
  225. * tRH ND_nRE high duration
  226. * tRP ND_nRE pulse width
  227. * tR ND_nWE high to ND_nRE low for read
  228. * tWHR ND_nWE high to ND_nRE low for status read
  229. * tAR ND_ALE low to ND_nRE low delay
  230. */
  231. /*ch cs wh wp rh rp r whr ar */
  232. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  233. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  234. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  235. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  236. { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
  237. };
  238. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  239. /*
  240. * chip_id
  241. * flash_width Width of Flash memory (DWIDTH_M)
  242. * dfc_width Width of flash controller(DWIDTH_C)
  243. * *timing
  244. * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
  245. */
  246. { 0x46ec, 16, 16, &timing[1] },
  247. { 0xdaec, 8, 8, &timing[1] },
  248. { 0xd7ec, 8, 8, &timing[1] },
  249. { 0xa12c, 8, 8, &timing[2] },
  250. { 0xb12c, 16, 16, &timing[2] },
  251. { 0xdc2c, 8, 8, &timing[2] },
  252. { 0xcc2c, 16, 16, &timing[2] },
  253. { 0xba20, 16, 16, &timing[3] },
  254. { 0xda98, 8, 8, &timing[4] },
  255. };
  256. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  257. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  258. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  259. static struct nand_bbt_descr bbt_main_descr = {
  260. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  261. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  262. .offs = 8,
  263. .len = 6,
  264. .veroffs = 14,
  265. .maxblocks = 8, /* Last 8 blocks in each chip */
  266. .pattern = bbt_pattern
  267. };
  268. static struct nand_bbt_descr bbt_mirror_descr = {
  269. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  270. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  271. .offs = 8,
  272. .len = 6,
  273. .veroffs = 14,
  274. .maxblocks = 8, /* Last 8 blocks in each chip */
  275. .pattern = bbt_mirror_pattern
  276. };
  277. #endif
  278. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  279. .eccbytes = 32,
  280. .eccpos = {
  281. 32, 33, 34, 35, 36, 37, 38, 39,
  282. 40, 41, 42, 43, 44, 45, 46, 47,
  283. 48, 49, 50, 51, 52, 53, 54, 55,
  284. 56, 57, 58, 59, 60, 61, 62, 63},
  285. .oobfree = { {2, 30} }
  286. };
  287. static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
  288. .eccbytes = 64,
  289. .eccpos = {
  290. 32, 33, 34, 35, 36, 37, 38, 39,
  291. 40, 41, 42, 43, 44, 45, 46, 47,
  292. 48, 49, 50, 51, 52, 53, 54, 55,
  293. 56, 57, 58, 59, 60, 61, 62, 63,
  294. 64, 65, 66, 67, 68, 69, 70, 71,
  295. 72, 73, 74, 75, 76, 77, 78, 79,
  296. 80, 81, 82, 83, 84, 85, 86, 87,
  297. 88, 89, 90, 91, 92, 93, 94, 95},
  298. .oobfree = { {1, 4}, {6, 26} }
  299. };
  300. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  301. .eccbytes = 64,
  302. .eccpos = {
  303. 32, 33, 34, 35, 36, 37, 38, 39,
  304. 40, 41, 42, 43, 44, 45, 46, 47,
  305. 48, 49, 50, 51, 52, 53, 54, 55,
  306. 56, 57, 58, 59, 60, 61, 62, 63,
  307. 96, 97, 98, 99, 100, 101, 102, 103,
  308. 104, 105, 106, 107, 108, 109, 110, 111,
  309. 112, 113, 114, 115, 116, 117, 118, 119,
  310. 120, 121, 122, 123, 124, 125, 126, 127},
  311. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  312. .oobfree = { {6, 26}, { 64, 32} }
  313. };
  314. static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
  315. .eccbytes = 128,
  316. .eccpos = {
  317. 32, 33, 34, 35, 36, 37, 38, 39,
  318. 40, 41, 42, 43, 44, 45, 46, 47,
  319. 48, 49, 50, 51, 52, 53, 54, 55,
  320. 56, 57, 58, 59, 60, 61, 62, 63,
  321. 96, 97, 98, 99, 100, 101, 102, 103,
  322. 104, 105, 106, 107, 108, 109, 110, 111,
  323. 112, 113, 114, 115, 116, 117, 118, 119,
  324. 120, 121, 122, 123, 124, 125, 126, 127,
  325. 160, 161, 162, 163, 164, 165, 166, 167,
  326. 168, 169, 170, 171, 172, 173, 174, 175,
  327. 176, 177, 178, 179, 180, 181, 182, 183,
  328. 184, 185, 186, 187, 188, 189, 190, 191,
  329. 224, 225, 226, 227, 228, 229, 230, 231,
  330. 232, 233, 234, 235, 236, 237, 238, 239,
  331. 240, 241, 242, 243, 244, 245, 246, 247,
  332. 248, 249, 250, 251, 252, 253, 254, 255},
  333. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  334. .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
  335. };
  336. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  337. .eccbytes = 128,
  338. .eccpos = {
  339. 32, 33, 34, 35, 36, 37, 38, 39,
  340. 40, 41, 42, 43, 44, 45, 46, 47,
  341. 48, 49, 50, 51, 52, 53, 54, 55,
  342. 56, 57, 58, 59, 60, 61, 62, 63},
  343. .oobfree = { }
  344. };
  345. static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
  346. .eccbytes = 256,
  347. .eccpos = {},
  348. /* HW ECC handles all ECC data and all spare area is free for OOB */
  349. .oobfree = {{0, 160} }
  350. };
  351. #define NDTR0_tCH(c) (min((c), 7) << 19)
  352. #define NDTR0_tCS(c) (min((c), 7) << 16)
  353. #define NDTR0_tWH(c) (min((c), 7) << 11)
  354. #define NDTR0_tWP(c) (min((c), 7) << 8)
  355. #define NDTR0_tRH(c) (min((c), 7) << 3)
  356. #define NDTR0_tRP(c) (min((c), 7) << 0)
  357. #define NDTR1_tR(c) (min((c), 65535) << 16)
  358. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  359. #define NDTR1_tAR(c) (min((c), 15) << 0)
  360. /* convert nano-seconds to nand flash controller clock cycles */
  361. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  362. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
  363. {
  364. /* We only support the Armada 370/XP/38x for now */
  365. return PXA3XX_NAND_VARIANT_ARMADA370;
  366. }
  367. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  368. const struct pxa3xx_nand_timing *t)
  369. {
  370. struct pxa3xx_nand_info *info = host->info_data;
  371. unsigned long nand_clk = mvebu_get_nand_clock();
  372. uint32_t ndtr0, ndtr1;
  373. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  374. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  375. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  376. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  377. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  378. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  379. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  380. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  381. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  382. info->ndtr0cs0 = ndtr0;
  383. info->ndtr1cs0 = ndtr1;
  384. nand_writel(info, NDTR0CS0, ndtr0);
  385. nand_writel(info, NDTR1CS0, ndtr1);
  386. }
  387. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  388. const struct nand_sdr_timings *t)
  389. {
  390. struct pxa3xx_nand_info *info = host->info_data;
  391. struct nand_chip *chip = &host->chip;
  392. unsigned long nand_clk = mvebu_get_nand_clock();
  393. uint32_t ndtr0, ndtr1;
  394. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  395. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  396. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  397. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
  398. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  399. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
  400. u32 tR = chip->chip_delay * 1000;
  401. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  402. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  403. /* fallback to a default value if tR = 0 */
  404. if (!tR)
  405. tR = 20000;
  406. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  407. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  408. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  409. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  410. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  411. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  412. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  413. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  414. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  415. info->ndtr0cs0 = ndtr0;
  416. info->ndtr1cs0 = ndtr1;
  417. nand_writel(info, NDTR0CS0, ndtr0);
  418. nand_writel(info, NDTR1CS0, ndtr1);
  419. }
  420. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  421. {
  422. const struct nand_sdr_timings *timings;
  423. struct nand_chip *chip = &host->chip;
  424. struct pxa3xx_nand_info *info = host->info_data;
  425. const struct pxa3xx_nand_flash *f = NULL;
  426. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  427. int mode, id, ntypes, i;
  428. mode = onfi_get_async_timing_mode(chip);
  429. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  430. ntypes = ARRAY_SIZE(builtin_flash_types);
  431. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  432. id = chip->read_byte(mtd);
  433. id |= chip->read_byte(mtd) << 0x8;
  434. for (i = 0; i < ntypes; i++) {
  435. f = &builtin_flash_types[i];
  436. if (f->chip_id == id)
  437. break;
  438. }
  439. if (i == ntypes) {
  440. dev_err(&info->pdev->dev, "Error: timings not found\n");
  441. return -EINVAL;
  442. }
  443. pxa3xx_nand_set_timing(host, f->timing);
  444. if (f->flash_width == 16) {
  445. info->reg_ndcr |= NDCR_DWIDTH_M;
  446. chip->options |= NAND_BUSWIDTH_16;
  447. }
  448. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  449. } else {
  450. mode = fls(mode) - 1;
  451. if (mode < 0)
  452. mode = 0;
  453. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  454. if (IS_ERR(timings))
  455. return PTR_ERR(timings);
  456. pxa3xx_nand_set_sdr_timing(host, timings);
  457. }
  458. return 0;
  459. }
  460. /**
  461. * NOTE: it is a must to set ND_RUN first, then write
  462. * command buffer, otherwise, it does not work.
  463. * We enable all the interrupt at the same time, and
  464. * let pxa3xx_nand_irq to handle all logic.
  465. */
  466. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  467. {
  468. uint32_t ndcr;
  469. ndcr = info->reg_ndcr;
  470. if (info->use_ecc) {
  471. ndcr |= NDCR_ECC_EN;
  472. if (info->ecc_bch)
  473. nand_writel(info, NDECCCTRL, 0x1);
  474. } else {
  475. ndcr &= ~NDCR_ECC_EN;
  476. if (info->ecc_bch)
  477. nand_writel(info, NDECCCTRL, 0x0);
  478. }
  479. ndcr &= ~NDCR_DMA_EN;
  480. if (info->use_spare)
  481. ndcr |= NDCR_SPARE_EN;
  482. else
  483. ndcr &= ~NDCR_SPARE_EN;
  484. ndcr |= NDCR_ND_RUN;
  485. /* clear status bits and run */
  486. nand_writel(info, NDSR, NDSR_MASK);
  487. nand_writel(info, NDCR, 0);
  488. nand_writel(info, NDCR, ndcr);
  489. }
  490. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  491. {
  492. uint32_t ndcr;
  493. ndcr = nand_readl(info, NDCR);
  494. nand_writel(info, NDCR, ndcr | int_mask);
  495. }
  496. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  497. {
  498. if (info->ecc_bch && !info->force_raw) {
  499. u32 ts;
  500. /*
  501. * According to the datasheet, when reading from NDDB
  502. * with BCH enabled, after each 32 bytes reads, we
  503. * have to make sure that the NDSR.RDDREQ bit is set.
  504. *
  505. * Drain the FIFO 8 32 bits reads at a time, and skip
  506. * the polling on the last read.
  507. */
  508. while (len > 8) {
  509. readsl(info->mmio_base + NDDB, data, 8);
  510. ts = get_timer(0);
  511. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  512. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  513. dev_err(&info->pdev->dev,
  514. "Timeout on RDDREQ while draining the FIFO\n");
  515. return;
  516. }
  517. }
  518. data += 32;
  519. len -= 8;
  520. }
  521. }
  522. readsl(info->mmio_base + NDDB, data, len);
  523. }
  524. static void handle_data_pio(struct pxa3xx_nand_info *info)
  525. {
  526. int data_len = info->step_chunk_size;
  527. /*
  528. * In raw mode, include the spare area and the ECC bytes that are not
  529. * consumed by the controller in the data section. Do not reorganize
  530. * here, do it in the ->read_page_raw() handler instead.
  531. */
  532. if (info->force_raw)
  533. data_len += info->step_spare_size + info->ecc_size;
  534. switch (info->state) {
  535. case STATE_PIO_WRITING:
  536. if (info->step_chunk_size)
  537. writesl(info->mmio_base + NDDB,
  538. info->data_buff + info->data_buff_pos,
  539. DIV_ROUND_UP(data_len, 4));
  540. if (info->step_spare_size)
  541. writesl(info->mmio_base + NDDB,
  542. info->oob_buff + info->oob_buff_pos,
  543. DIV_ROUND_UP(info->step_spare_size, 4));
  544. break;
  545. case STATE_PIO_READING:
  546. if (data_len)
  547. drain_fifo(info,
  548. info->data_buff + info->data_buff_pos,
  549. DIV_ROUND_UP(data_len, 4));
  550. if (info->force_raw)
  551. break;
  552. if (info->step_spare_size)
  553. drain_fifo(info,
  554. info->oob_buff + info->oob_buff_pos,
  555. DIV_ROUND_UP(info->step_spare_size, 4));
  556. break;
  557. default:
  558. dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
  559. info->state);
  560. BUG();
  561. }
  562. /* Update buffer pointers for multi-page read/write */
  563. info->data_buff_pos += data_len;
  564. info->oob_buff_pos += info->step_spare_size;
  565. }
  566. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  567. {
  568. handle_data_pio(info);
  569. info->state = STATE_CMD_DONE;
  570. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  571. }
  572. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  573. {
  574. unsigned int status, is_completed = 0, is_ready = 0;
  575. unsigned int ready, cmd_done;
  576. irqreturn_t ret = IRQ_HANDLED;
  577. if (info->cs == 0) {
  578. ready = NDSR_FLASH_RDY;
  579. cmd_done = NDSR_CS0_CMDD;
  580. } else {
  581. ready = NDSR_RDY;
  582. cmd_done = NDSR_CS1_CMDD;
  583. }
  584. /* TODO - find out why we need the delay during write operation. */
  585. ndelay(1);
  586. status = nand_readl(info, NDSR);
  587. if (status & NDSR_UNCORERR)
  588. info->retcode = ERR_UNCORERR;
  589. if (status & NDSR_CORERR) {
  590. info->retcode = ERR_CORERR;
  591. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
  592. info->ecc_bch)
  593. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  594. else
  595. info->ecc_err_cnt = 1;
  596. /*
  597. * Each chunk composing a page is corrected independently,
  598. * and we need to store maximum number of corrected bitflips
  599. * to return it to the MTD layer in ecc.read_page().
  600. */
  601. info->max_bitflips = max_t(unsigned int,
  602. info->max_bitflips,
  603. info->ecc_err_cnt);
  604. }
  605. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  606. info->state = (status & NDSR_RDDREQ) ?
  607. STATE_PIO_READING : STATE_PIO_WRITING;
  608. /* Call the IRQ thread in U-Boot directly */
  609. pxa3xx_nand_irq_thread(info);
  610. return 0;
  611. }
  612. if (status & cmd_done) {
  613. info->state = STATE_CMD_DONE;
  614. is_completed = 1;
  615. }
  616. if (status & ready) {
  617. info->state = STATE_READY;
  618. is_ready = 1;
  619. }
  620. /*
  621. * Clear all status bit before issuing the next command, which
  622. * can and will alter the status bits and will deserve a new
  623. * interrupt on its own. This lets the controller exit the IRQ
  624. */
  625. nand_writel(info, NDSR, status);
  626. if (status & NDSR_WRCMDREQ) {
  627. status &= ~NDSR_WRCMDREQ;
  628. info->state = STATE_CMD_HANDLE;
  629. /*
  630. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  631. * must be loaded by writing directly either 12 or 16
  632. * bytes directly to NDCB0, four bytes at a time.
  633. *
  634. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  635. * but each NDCBx register can be read.
  636. */
  637. nand_writel(info, NDCB0, info->ndcb0);
  638. nand_writel(info, NDCB0, info->ndcb1);
  639. nand_writel(info, NDCB0, info->ndcb2);
  640. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  641. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  642. nand_writel(info, NDCB0, info->ndcb3);
  643. }
  644. if (is_completed)
  645. info->cmd_complete = 1;
  646. if (is_ready)
  647. info->dev_ready = 1;
  648. return ret;
  649. }
  650. static inline int is_buf_blank(uint8_t *buf, size_t len)
  651. {
  652. for (; len > 0; len--)
  653. if (*buf++ != 0xff)
  654. return 0;
  655. return 1;
  656. }
  657. static void set_command_address(struct pxa3xx_nand_info *info,
  658. unsigned int page_size, uint16_t column, int page_addr)
  659. {
  660. /* small page addr setting */
  661. if (page_size < info->chunk_size) {
  662. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  663. | (column & 0xFF);
  664. info->ndcb2 = 0;
  665. } else {
  666. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  667. | (column & 0xFFFF);
  668. if (page_addr & 0xFF0000)
  669. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  670. else
  671. info->ndcb2 = 0;
  672. }
  673. }
  674. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  675. {
  676. struct pxa3xx_nand_host *host = info->host[info->cs];
  677. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  678. /* reset data and oob column point to handle data */
  679. info->buf_start = 0;
  680. info->buf_count = 0;
  681. info->data_buff_pos = 0;
  682. info->oob_buff_pos = 0;
  683. info->step_chunk_size = 0;
  684. info->step_spare_size = 0;
  685. info->cur_chunk = 0;
  686. info->use_ecc = 0;
  687. info->use_spare = 1;
  688. info->retcode = ERR_NONE;
  689. info->ecc_err_cnt = 0;
  690. info->ndcb3 = 0;
  691. info->need_wait = 0;
  692. switch (command) {
  693. case NAND_CMD_READ0:
  694. case NAND_CMD_READOOB:
  695. case NAND_CMD_PAGEPROG:
  696. if (!info->force_raw)
  697. info->use_ecc = 1;
  698. break;
  699. case NAND_CMD_PARAM:
  700. info->use_spare = 0;
  701. break;
  702. default:
  703. info->ndcb1 = 0;
  704. info->ndcb2 = 0;
  705. break;
  706. }
  707. /*
  708. * If we are about to issue a read command, or about to set
  709. * the write address, then clean the data buffer.
  710. */
  711. if (command == NAND_CMD_READ0 ||
  712. command == NAND_CMD_READOOB ||
  713. command == NAND_CMD_SEQIN) {
  714. info->buf_count = mtd->writesize + mtd->oobsize;
  715. memset(info->data_buff, 0xFF, info->buf_count);
  716. }
  717. }
  718. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  719. int ext_cmd_type, uint16_t column, int page_addr)
  720. {
  721. int addr_cycle, exec_cmd;
  722. struct pxa3xx_nand_host *host;
  723. struct mtd_info *mtd;
  724. host = info->host[info->cs];
  725. mtd = nand_to_mtd(&host->chip);
  726. addr_cycle = 0;
  727. exec_cmd = 1;
  728. if (info->cs != 0)
  729. info->ndcb0 = NDCB0_CSEL;
  730. else
  731. info->ndcb0 = 0;
  732. if (command == NAND_CMD_SEQIN)
  733. exec_cmd = 0;
  734. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  735. + host->col_addr_cycles);
  736. switch (command) {
  737. case NAND_CMD_READOOB:
  738. case NAND_CMD_READ0:
  739. info->buf_start = column;
  740. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  741. | addr_cycle
  742. | NAND_CMD_READ0;
  743. if (command == NAND_CMD_READOOB)
  744. info->buf_start += mtd->writesize;
  745. if (info->cur_chunk < info->nfullchunks) {
  746. info->step_chunk_size = info->chunk_size;
  747. info->step_spare_size = info->spare_size;
  748. } else {
  749. info->step_chunk_size = info->last_chunk_size;
  750. info->step_spare_size = info->last_spare_size;
  751. }
  752. /*
  753. * Multiple page read needs an 'extended command type' field,
  754. * which is either naked-read or last-read according to the
  755. * state.
  756. */
  757. if (info->force_raw) {
  758. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) |
  759. NDCB0_LEN_OVRD |
  760. NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  761. info->ndcb3 = info->step_chunk_size +
  762. info->step_spare_size + info->ecc_size;
  763. } else if (mtd->writesize == info->chunk_size) {
  764. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  765. } else if (mtd->writesize > info->chunk_size) {
  766. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  767. | NDCB0_LEN_OVRD
  768. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  769. info->ndcb3 = info->step_chunk_size +
  770. info->step_spare_size;
  771. }
  772. set_command_address(info, mtd->writesize, column, page_addr);
  773. break;
  774. case NAND_CMD_SEQIN:
  775. info->buf_start = column;
  776. set_command_address(info, mtd->writesize, 0, page_addr);
  777. /*
  778. * Multiple page programming needs to execute the initial
  779. * SEQIN command that sets the page address.
  780. */
  781. if (mtd->writesize > info->chunk_size) {
  782. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  783. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  784. | addr_cycle
  785. | command;
  786. exec_cmd = 1;
  787. }
  788. break;
  789. case NAND_CMD_PAGEPROG:
  790. if (is_buf_blank(info->data_buff,
  791. (mtd->writesize + mtd->oobsize))) {
  792. exec_cmd = 0;
  793. break;
  794. }
  795. if (info->cur_chunk < info->nfullchunks) {
  796. info->step_chunk_size = info->chunk_size;
  797. info->step_spare_size = info->spare_size;
  798. } else {
  799. info->step_chunk_size = info->last_chunk_size;
  800. info->step_spare_size = info->last_spare_size;
  801. }
  802. /* Second command setting for large pages */
  803. if (mtd->writesize > info->chunk_size) {
  804. /*
  805. * Multiple page write uses the 'extended command'
  806. * field. This can be used to issue a command dispatch
  807. * or a naked-write depending on the current stage.
  808. */
  809. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  810. | NDCB0_LEN_OVRD
  811. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  812. info->ndcb3 = info->step_chunk_size +
  813. info->step_spare_size;
  814. /*
  815. * This is the command dispatch that completes a chunked
  816. * page program operation.
  817. */
  818. if (info->cur_chunk == info->ntotalchunks) {
  819. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  820. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  821. | command;
  822. info->ndcb1 = 0;
  823. info->ndcb2 = 0;
  824. info->ndcb3 = 0;
  825. }
  826. } else {
  827. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  828. | NDCB0_AUTO_RS
  829. | NDCB0_ST_ROW_EN
  830. | NDCB0_DBC
  831. | (NAND_CMD_PAGEPROG << 8)
  832. | NAND_CMD_SEQIN
  833. | addr_cycle;
  834. }
  835. break;
  836. case NAND_CMD_PARAM:
  837. info->buf_count = INIT_BUFFER_SIZE;
  838. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  839. | NDCB0_ADDR_CYC(1)
  840. | NDCB0_LEN_OVRD
  841. | command;
  842. info->ndcb1 = (column & 0xFF);
  843. info->ndcb3 = INIT_BUFFER_SIZE;
  844. info->step_chunk_size = INIT_BUFFER_SIZE;
  845. break;
  846. case NAND_CMD_READID:
  847. info->buf_count = READ_ID_BYTES;
  848. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  849. | NDCB0_ADDR_CYC(1)
  850. | command;
  851. info->ndcb1 = (column & 0xFF);
  852. info->step_chunk_size = 8;
  853. break;
  854. case NAND_CMD_STATUS:
  855. info->buf_count = 1;
  856. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  857. | NDCB0_ADDR_CYC(1)
  858. | command;
  859. info->step_chunk_size = 8;
  860. break;
  861. case NAND_CMD_ERASE1:
  862. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  863. | NDCB0_AUTO_RS
  864. | NDCB0_ADDR_CYC(3)
  865. | NDCB0_DBC
  866. | (NAND_CMD_ERASE2 << 8)
  867. | NAND_CMD_ERASE1;
  868. info->ndcb1 = page_addr;
  869. info->ndcb2 = 0;
  870. break;
  871. case NAND_CMD_RESET:
  872. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  873. | command;
  874. break;
  875. case NAND_CMD_ERASE2:
  876. exec_cmd = 0;
  877. break;
  878. default:
  879. exec_cmd = 0;
  880. dev_err(&info->pdev->dev, "non-supported command %x\n",
  881. command);
  882. break;
  883. }
  884. return exec_cmd;
  885. }
  886. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  887. int column, int page_addr)
  888. {
  889. struct nand_chip *chip = mtd_to_nand(mtd);
  890. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  891. struct pxa3xx_nand_info *info = host->info_data;
  892. int exec_cmd;
  893. /*
  894. * if this is a x16 device ,then convert the input
  895. * "byte" address into a "word" address appropriate
  896. * for indexing a word-oriented device
  897. */
  898. if (info->reg_ndcr & NDCR_DWIDTH_M)
  899. column /= 2;
  900. /*
  901. * There may be different NAND chip hooked to
  902. * different chip select, so check whether
  903. * chip select has been changed, if yes, reset the timing
  904. */
  905. if (info->cs != host->cs) {
  906. info->cs = host->cs;
  907. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  908. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  909. }
  910. prepare_start_command(info, command);
  911. info->state = STATE_PREPARED;
  912. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  913. if (exec_cmd) {
  914. u32 ts;
  915. info->cmd_complete = 0;
  916. info->dev_ready = 0;
  917. info->need_wait = 1;
  918. pxa3xx_nand_start(info);
  919. ts = get_timer(0);
  920. while (1) {
  921. u32 status;
  922. status = nand_readl(info, NDSR);
  923. if (status)
  924. pxa3xx_nand_irq(info);
  925. if (info->cmd_complete)
  926. break;
  927. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  928. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  929. return;
  930. }
  931. }
  932. }
  933. info->state = STATE_IDLE;
  934. }
  935. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  936. const unsigned command,
  937. int column, int page_addr)
  938. {
  939. struct nand_chip *chip = mtd_to_nand(mtd);
  940. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  941. struct pxa3xx_nand_info *info = host->info_data;
  942. int exec_cmd, ext_cmd_type;
  943. /*
  944. * if this is a x16 device then convert the input
  945. * "byte" address into a "word" address appropriate
  946. * for indexing a word-oriented device
  947. */
  948. if (info->reg_ndcr & NDCR_DWIDTH_M)
  949. column /= 2;
  950. /*
  951. * There may be different NAND chip hooked to
  952. * different chip select, so check whether
  953. * chip select has been changed, if yes, reset the timing
  954. */
  955. if (info->cs != host->cs) {
  956. info->cs = host->cs;
  957. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  958. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  959. }
  960. /* Select the extended command for the first command */
  961. switch (command) {
  962. case NAND_CMD_READ0:
  963. case NAND_CMD_READOOB:
  964. ext_cmd_type = EXT_CMD_TYPE_MONO;
  965. break;
  966. case NAND_CMD_SEQIN:
  967. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  968. break;
  969. case NAND_CMD_PAGEPROG:
  970. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  971. break;
  972. default:
  973. ext_cmd_type = 0;
  974. break;
  975. }
  976. prepare_start_command(info, command);
  977. /*
  978. * Prepare the "is ready" completion before starting a command
  979. * transaction sequence. If the command is not executed the
  980. * completion will be completed, see below.
  981. *
  982. * We can do that inside the loop because the command variable
  983. * is invariant and thus so is the exec_cmd.
  984. */
  985. info->need_wait = 1;
  986. info->dev_ready = 0;
  987. do {
  988. u32 ts;
  989. info->state = STATE_PREPARED;
  990. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  991. column, page_addr);
  992. if (!exec_cmd) {
  993. info->need_wait = 0;
  994. info->dev_ready = 1;
  995. break;
  996. }
  997. info->cmd_complete = 0;
  998. pxa3xx_nand_start(info);
  999. ts = get_timer(0);
  1000. while (1) {
  1001. u32 status;
  1002. status = nand_readl(info, NDSR);
  1003. if (status)
  1004. pxa3xx_nand_irq(info);
  1005. if (info->cmd_complete)
  1006. break;
  1007. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1008. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  1009. return;
  1010. }
  1011. }
  1012. /* Only a few commands need several steps */
  1013. if (command != NAND_CMD_PAGEPROG &&
  1014. command != NAND_CMD_READ0 &&
  1015. command != NAND_CMD_READOOB)
  1016. break;
  1017. info->cur_chunk++;
  1018. /* Check if the sequence is complete */
  1019. if (info->cur_chunk == info->ntotalchunks &&
  1020. command != NAND_CMD_PAGEPROG)
  1021. break;
  1022. /*
  1023. * After a splitted program command sequence has issued
  1024. * the command dispatch, the command sequence is complete.
  1025. */
  1026. if (info->cur_chunk == (info->ntotalchunks + 1) &&
  1027. command == NAND_CMD_PAGEPROG &&
  1028. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  1029. break;
  1030. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  1031. /* Last read: issue a 'last naked read' */
  1032. if (info->cur_chunk == info->ntotalchunks - 1)
  1033. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  1034. else
  1035. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  1036. /*
  1037. * If a splitted program command has no more data to transfer,
  1038. * the command dispatch must be issued to complete.
  1039. */
  1040. } else if (command == NAND_CMD_PAGEPROG &&
  1041. info->cur_chunk == info->ntotalchunks) {
  1042. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  1043. }
  1044. } while (1);
  1045. info->state = STATE_IDLE;
  1046. }
  1047. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  1048. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  1049. int page)
  1050. {
  1051. chip->write_buf(mtd, buf, mtd->writesize);
  1052. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1053. return 0;
  1054. }
  1055. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  1056. struct nand_chip *chip, uint8_t *buf, int oob_required,
  1057. int page)
  1058. {
  1059. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1060. struct pxa3xx_nand_info *info = host->info_data;
  1061. int bf;
  1062. chip->read_buf(mtd, buf, mtd->writesize);
  1063. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1064. if (info->retcode == ERR_CORERR && info->use_ecc) {
  1065. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  1066. } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) {
  1067. /*
  1068. * Empty pages will trigger uncorrectable errors. Re-read the
  1069. * entire page in raw mode and check for bits not being "1".
  1070. * If there are more than the supported strength, then it means
  1071. * this is an actual uncorrectable error.
  1072. */
  1073. chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page);
  1074. bf = nand_check_erased_ecc_chunk(buf, mtd->writesize,
  1075. chip->oob_poi, mtd->oobsize,
  1076. NULL, 0, chip->ecc.strength);
  1077. if (bf < 0) {
  1078. mtd->ecc_stats.failed++;
  1079. } else if (bf) {
  1080. mtd->ecc_stats.corrected += bf;
  1081. info->max_bitflips = max_t(unsigned int,
  1082. info->max_bitflips, bf);
  1083. info->retcode = ERR_CORERR;
  1084. } else {
  1085. info->retcode = ERR_NONE;
  1086. }
  1087. } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) {
  1088. /* Raw read is not supported with Hamming ECC engine */
  1089. if (is_buf_blank(buf, mtd->writesize))
  1090. info->retcode = ERR_NONE;
  1091. else
  1092. mtd->ecc_stats.failed++;
  1093. }
  1094. return info->max_bitflips;
  1095. }
  1096. static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd,
  1097. struct nand_chip *chip, uint8_t *buf,
  1098. int oob_required, int page)
  1099. {
  1100. struct pxa3xx_nand_host *host = chip->priv;
  1101. struct pxa3xx_nand_info *info = host->info_data;
  1102. int chunk, ecc_off_buf;
  1103. if (!info->ecc_bch)
  1104. return -ENOTSUPP;
  1105. /*
  1106. * Set the force_raw boolean, then re-call ->cmdfunc() that will run
  1107. * pxa3xx_nand_start(), which will actually disable the ECC engine.
  1108. */
  1109. info->force_raw = true;
  1110. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1111. ecc_off_buf = (info->nfullchunks * info->spare_size) +
  1112. info->last_spare_size;
  1113. for (chunk = 0; chunk < info->nfullchunks; chunk++) {
  1114. chip->read_buf(mtd,
  1115. buf + (chunk * info->chunk_size),
  1116. info->chunk_size);
  1117. chip->read_buf(mtd,
  1118. chip->oob_poi +
  1119. (chunk * (info->spare_size)),
  1120. info->spare_size);
  1121. chip->read_buf(mtd,
  1122. chip->oob_poi + ecc_off_buf +
  1123. (chunk * (info->ecc_size)),
  1124. info->ecc_size - 2);
  1125. }
  1126. if (info->ntotalchunks > info->nfullchunks) {
  1127. chip->read_buf(mtd,
  1128. buf + (info->nfullchunks * info->chunk_size),
  1129. info->last_chunk_size);
  1130. chip->read_buf(mtd,
  1131. chip->oob_poi +
  1132. (info->nfullchunks * (info->spare_size)),
  1133. info->last_spare_size);
  1134. chip->read_buf(mtd,
  1135. chip->oob_poi + ecc_off_buf +
  1136. (info->nfullchunks * (info->ecc_size)),
  1137. info->ecc_size - 2);
  1138. }
  1139. info->force_raw = false;
  1140. return 0;
  1141. }
  1142. static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd,
  1143. struct nand_chip *chip, int page)
  1144. {
  1145. /* Invalidate page cache */
  1146. chip->pagebuf = -1;
  1147. return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true,
  1148. page);
  1149. }
  1150. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  1151. {
  1152. struct nand_chip *chip = mtd_to_nand(mtd);
  1153. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1154. struct pxa3xx_nand_info *info = host->info_data;
  1155. char retval = 0xFF;
  1156. if (info->buf_start < info->buf_count)
  1157. /* Has just send a new command? */
  1158. retval = info->data_buff[info->buf_start++];
  1159. return retval;
  1160. }
  1161. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  1162. {
  1163. struct nand_chip *chip = mtd_to_nand(mtd);
  1164. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1165. struct pxa3xx_nand_info *info = host->info_data;
  1166. u16 retval = 0xFFFF;
  1167. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  1168. retval = *((u16 *)(info->data_buff+info->buf_start));
  1169. info->buf_start += 2;
  1170. }
  1171. return retval;
  1172. }
  1173. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1174. {
  1175. struct nand_chip *chip = mtd_to_nand(mtd);
  1176. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1177. struct pxa3xx_nand_info *info = host->info_data;
  1178. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1179. memcpy(buf, info->data_buff + info->buf_start, real_len);
  1180. info->buf_start += real_len;
  1181. }
  1182. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  1183. const uint8_t *buf, int len)
  1184. {
  1185. struct nand_chip *chip = mtd_to_nand(mtd);
  1186. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1187. struct pxa3xx_nand_info *info = host->info_data;
  1188. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1189. memcpy(info->data_buff + info->buf_start, buf, real_len);
  1190. info->buf_start += real_len;
  1191. }
  1192. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  1193. {
  1194. return;
  1195. }
  1196. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1197. {
  1198. struct nand_chip *chip = mtd_to_nand(mtd);
  1199. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1200. struct pxa3xx_nand_info *info = host->info_data;
  1201. if (info->need_wait) {
  1202. u32 ts;
  1203. info->need_wait = 0;
  1204. ts = get_timer(0);
  1205. while (1) {
  1206. u32 status;
  1207. status = nand_readl(info, NDSR);
  1208. if (status)
  1209. pxa3xx_nand_irq(info);
  1210. if (info->dev_ready)
  1211. break;
  1212. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1213. dev_err(&info->pdev->dev, "Ready timeout!!!\n");
  1214. return NAND_STATUS_FAIL;
  1215. }
  1216. }
  1217. }
  1218. /* pxa3xx_nand_send_command has waited for command complete */
  1219. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1220. if (info->retcode == ERR_NONE)
  1221. return 0;
  1222. else
  1223. return NAND_STATUS_FAIL;
  1224. }
  1225. return NAND_STATUS_READY;
  1226. }
  1227. static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
  1228. {
  1229. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1230. /* Configure default flash values */
  1231. info->reg_ndcr = 0x0; /* enable all interrupts */
  1232. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1233. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1234. info->reg_ndcr |= NDCR_SPARE_EN;
  1235. return 0;
  1236. }
  1237. static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
  1238. {
  1239. struct pxa3xx_nand_host *host = info->host[info->cs];
  1240. struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1241. struct nand_chip *chip = mtd_to_nand(mtd);
  1242. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1243. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1244. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1245. }
  1246. static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1247. {
  1248. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1249. uint32_t ndcr = nand_readl(info, NDCR);
  1250. /* Set an initial chunk size */
  1251. info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
  1252. info->reg_ndcr = ndcr &
  1253. ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
  1254. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1255. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1256. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1257. }
  1258. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1259. {
  1260. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1261. if (info->data_buff == NULL)
  1262. return -ENOMEM;
  1263. return 0;
  1264. }
  1265. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1266. {
  1267. struct pxa3xx_nand_info *info = host->info_data;
  1268. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1269. struct mtd_info *mtd;
  1270. struct nand_chip *chip;
  1271. const struct nand_sdr_timings *timings;
  1272. int ret;
  1273. mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1274. chip = mtd_to_nand(mtd);
  1275. /* configure default flash values */
  1276. info->reg_ndcr = 0x0; /* enable all interrupts */
  1277. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1278. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1279. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1280. /* use the common timing to make a try */
  1281. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1282. if (IS_ERR(timings))
  1283. return PTR_ERR(timings);
  1284. pxa3xx_nand_set_sdr_timing(host, timings);
  1285. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1286. ret = chip->waitfunc(mtd, chip);
  1287. if (ret & NAND_STATUS_FAIL)
  1288. return -ENODEV;
  1289. return 0;
  1290. }
  1291. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1292. struct nand_ecc_ctrl *ecc,
  1293. int strength, int ecc_stepsize, int page_size)
  1294. {
  1295. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1296. info->nfullchunks = 1;
  1297. info->ntotalchunks = 1;
  1298. info->chunk_size = 2048;
  1299. info->spare_size = 40;
  1300. info->ecc_size = 24;
  1301. ecc->mode = NAND_ECC_HW;
  1302. ecc->size = 512;
  1303. ecc->strength = 1;
  1304. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1305. info->nfullchunks = 1;
  1306. info->ntotalchunks = 1;
  1307. info->chunk_size = 512;
  1308. info->spare_size = 8;
  1309. info->ecc_size = 8;
  1310. ecc->mode = NAND_ECC_HW;
  1311. ecc->size = 512;
  1312. ecc->strength = 1;
  1313. /*
  1314. * Required ECC: 4-bit correction per 512 bytes
  1315. * Select: 16-bit correction per 2048 bytes
  1316. */
  1317. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1318. info->ecc_bch = 1;
  1319. info->nfullchunks = 1;
  1320. info->ntotalchunks = 1;
  1321. info->chunk_size = 2048;
  1322. info->spare_size = 32;
  1323. info->ecc_size = 32;
  1324. ecc->mode = NAND_ECC_HW;
  1325. ecc->size = info->chunk_size;
  1326. ecc->layout = &ecc_layout_2KB_bch4bit;
  1327. ecc->strength = 16;
  1328. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1329. info->ecc_bch = 1;
  1330. info->nfullchunks = 2;
  1331. info->ntotalchunks = 2;
  1332. info->chunk_size = 2048;
  1333. info->spare_size = 32;
  1334. info->ecc_size = 32;
  1335. ecc->mode = NAND_ECC_HW;
  1336. ecc->size = info->chunk_size;
  1337. ecc->layout = &ecc_layout_4KB_bch4bit;
  1338. ecc->strength = 16;
  1339. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
  1340. info->ecc_bch = 1;
  1341. info->nfullchunks = 4;
  1342. info->ntotalchunks = 4;
  1343. info->chunk_size = 2048;
  1344. info->spare_size = 32;
  1345. info->ecc_size = 32;
  1346. ecc->mode = NAND_ECC_HW;
  1347. ecc->size = info->chunk_size;
  1348. ecc->layout = &ecc_layout_8KB_bch4bit;
  1349. ecc->strength = 16;
  1350. /*
  1351. * Required ECC: 8-bit correction per 512 bytes
  1352. * Select: 16-bit correction per 1024 bytes
  1353. */
  1354. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
  1355. info->ecc_bch = 1;
  1356. info->nfullchunks = 1;
  1357. info->ntotalchunks = 2;
  1358. info->chunk_size = 1024;
  1359. info->spare_size = 0;
  1360. info->last_chunk_size = 1024;
  1361. info->last_spare_size = 32;
  1362. info->ecc_size = 32;
  1363. ecc->mode = NAND_ECC_HW;
  1364. ecc->size = info->chunk_size;
  1365. ecc->layout = &ecc_layout_2KB_bch8bit;
  1366. ecc->strength = 16;
  1367. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1368. info->ecc_bch = 1;
  1369. info->nfullchunks = 4;
  1370. info->ntotalchunks = 5;
  1371. info->chunk_size = 1024;
  1372. info->spare_size = 0;
  1373. info->last_chunk_size = 0;
  1374. info->last_spare_size = 64;
  1375. info->ecc_size = 32;
  1376. ecc->mode = NAND_ECC_HW;
  1377. ecc->size = info->chunk_size;
  1378. ecc->layout = &ecc_layout_4KB_bch8bit;
  1379. ecc->strength = 16;
  1380. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
  1381. info->ecc_bch = 1;
  1382. info->nfullchunks = 8;
  1383. info->ntotalchunks = 9;
  1384. info->chunk_size = 1024;
  1385. info->spare_size = 0;
  1386. info->last_chunk_size = 0;
  1387. info->last_spare_size = 160;
  1388. info->ecc_size = 32;
  1389. ecc->mode = NAND_ECC_HW;
  1390. ecc->size = info->chunk_size;
  1391. ecc->layout = &ecc_layout_8KB_bch8bit;
  1392. ecc->strength = 16;
  1393. } else {
  1394. dev_err(&info->pdev->dev,
  1395. "ECC strength %d at page size %d is not supported\n",
  1396. strength, page_size);
  1397. return -ENODEV;
  1398. }
  1399. return 0;
  1400. }
  1401. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1402. {
  1403. struct nand_chip *chip = mtd_to_nand(mtd);
  1404. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1405. struct pxa3xx_nand_info *info = host->info_data;
  1406. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1407. int ret;
  1408. uint16_t ecc_strength, ecc_step;
  1409. if (pdata->keep_config) {
  1410. pxa3xx_nand_detect_config(info);
  1411. } else {
  1412. ret = pxa3xx_nand_config_ident(info);
  1413. if (ret)
  1414. return ret;
  1415. ret = pxa3xx_nand_sensing(host);
  1416. if (ret) {
  1417. dev_info(&info->pdev->dev,
  1418. "There is no chip on cs %d!\n",
  1419. info->cs);
  1420. return ret;
  1421. }
  1422. }
  1423. /* Device detection must be done with ECC disabled */
  1424. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  1425. nand_writel(info, NDECCCTRL, 0x0);
  1426. if (nand_scan_ident(mtd, 1, NULL))
  1427. return -ENODEV;
  1428. if (!pdata->keep_config) {
  1429. ret = pxa3xx_nand_init_timings(host);
  1430. if (ret) {
  1431. dev_err(&info->pdev->dev,
  1432. "Failed to set timings: %d\n", ret);
  1433. return ret;
  1434. }
  1435. }
  1436. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1437. /*
  1438. * We'll use a bad block table stored in-flash and don't
  1439. * allow writing the bad block marker to the flash.
  1440. */
  1441. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1442. chip->bbt_td = &bbt_main_descr;
  1443. chip->bbt_md = &bbt_mirror_descr;
  1444. #endif
  1445. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1446. ecc_strength = pdata->ecc_strength;
  1447. ecc_step = pdata->ecc_step_size;
  1448. } else {
  1449. ecc_strength = chip->ecc_strength_ds;
  1450. ecc_step = chip->ecc_step_ds;
  1451. }
  1452. /* Set default ECC strength requirements on non-ONFI devices */
  1453. if (ecc_strength < 1 && ecc_step < 1) {
  1454. ecc_strength = 1;
  1455. ecc_step = 512;
  1456. }
  1457. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1458. ecc_step, mtd->writesize);
  1459. if (ret)
  1460. return ret;
  1461. /*
  1462. * If the page size is bigger than the FIFO size, let's check
  1463. * we are given the right variant and then switch to the extended
  1464. * (aka split) command handling,
  1465. */
  1466. if (mtd->writesize > info->chunk_size) {
  1467. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
  1468. chip->cmdfunc = nand_cmdfunc_extended;
  1469. } else {
  1470. dev_err(&info->pdev->dev,
  1471. "unsupported page size on this variant\n");
  1472. return -ENODEV;
  1473. }
  1474. }
  1475. /* calculate addressing information */
  1476. if (mtd->writesize >= 2048)
  1477. host->col_addr_cycles = 2;
  1478. else
  1479. host->col_addr_cycles = 1;
  1480. /* release the initial buffer */
  1481. kfree(info->data_buff);
  1482. /* allocate the real data + oob buffer */
  1483. info->buf_size = mtd->writesize + mtd->oobsize;
  1484. ret = pxa3xx_nand_init_buff(info);
  1485. if (ret)
  1486. return ret;
  1487. info->oob_buff = info->data_buff + mtd->writesize;
  1488. if ((mtd->size >> chip->page_shift) > 65536)
  1489. host->row_addr_cycles = 3;
  1490. else
  1491. host->row_addr_cycles = 2;
  1492. if (!pdata->keep_config)
  1493. pxa3xx_nand_config_tail(info);
  1494. return nand_scan_tail(mtd);
  1495. }
  1496. static int alloc_nand_resource(struct pxa3xx_nand_info *info)
  1497. {
  1498. struct pxa3xx_nand_platform_data *pdata;
  1499. struct pxa3xx_nand_host *host;
  1500. struct nand_chip *chip = NULL;
  1501. struct mtd_info *mtd;
  1502. int ret, cs;
  1503. pdata = info->pdata;
  1504. if (pdata->num_cs <= 0)
  1505. return -ENODEV;
  1506. info->variant = pxa3xx_nand_get_variant();
  1507. for (cs = 0; cs < pdata->num_cs; cs++) {
  1508. chip = (struct nand_chip *)
  1509. ((u8 *)&info[1] + sizeof(*host) * cs);
  1510. mtd = nand_to_mtd(chip);
  1511. host = (struct pxa3xx_nand_host *)chip;
  1512. info->host[cs] = host;
  1513. host->cs = cs;
  1514. host->info_data = info;
  1515. mtd->owner = THIS_MODULE;
  1516. nand_set_controller_data(chip, host);
  1517. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1518. chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw;
  1519. chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw;
  1520. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1521. chip->controller = &info->controller;
  1522. chip->waitfunc = pxa3xx_nand_waitfunc;
  1523. chip->select_chip = pxa3xx_nand_select_chip;
  1524. chip->read_word = pxa3xx_nand_read_word;
  1525. chip->read_byte = pxa3xx_nand_read_byte;
  1526. chip->read_buf = pxa3xx_nand_read_buf;
  1527. chip->write_buf = pxa3xx_nand_write_buf;
  1528. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1529. chip->cmdfunc = nand_cmdfunc;
  1530. }
  1531. /* Allocate a buffer to allow flash detection */
  1532. info->buf_size = INIT_BUFFER_SIZE;
  1533. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1534. if (info->data_buff == NULL) {
  1535. ret = -ENOMEM;
  1536. goto fail_disable_clk;
  1537. }
  1538. /* initialize all interrupts to be disabled */
  1539. disable_int(info, NDSR_MASK);
  1540. return 0;
  1541. kfree(info->data_buff);
  1542. fail_disable_clk:
  1543. return ret;
  1544. }
  1545. static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
  1546. {
  1547. struct pxa3xx_nand_platform_data *pdata;
  1548. const void *blob = gd->fdt_blob;
  1549. int node = -1;
  1550. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1551. if (!pdata)
  1552. return -ENOMEM;
  1553. /* Get address decoding nodes from the FDT blob */
  1554. do {
  1555. node = fdt_node_offset_by_compatible(blob, node,
  1556. "marvell,mvebu-pxa3xx-nand");
  1557. if (node < 0)
  1558. break;
  1559. /* Bypass disabeld nodes */
  1560. if (!fdtdec_get_is_enabled(blob, node))
  1561. continue;
  1562. /* Get the first enabled NAND controler base address */
  1563. info->mmio_base =
  1564. (void __iomem *)fdtdec_get_addr_size_auto_noparent(
  1565. blob, node, "reg", 0, NULL, true);
  1566. pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
  1567. if (pdata->num_cs != 1) {
  1568. pr_err("pxa3xx driver supports single CS only\n");
  1569. break;
  1570. }
  1571. if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
  1572. pdata->enable_arbiter = 1;
  1573. if (fdtdec_get_bool(blob, node, "nand-keep-config"))
  1574. pdata->keep_config = 1;
  1575. /*
  1576. * ECC parameters.
  1577. * If these are not set, they will be selected according
  1578. * to the detected flash type.
  1579. */
  1580. /* ECC strength */
  1581. pdata->ecc_strength = fdtdec_get_int(blob, node,
  1582. "nand-ecc-strength", 0);
  1583. /* ECC step size */
  1584. pdata->ecc_step_size = fdtdec_get_int(blob, node,
  1585. "nand-ecc-step-size", 0);
  1586. info->pdata = pdata;
  1587. /* Currently support only a single NAND controller */
  1588. return 0;
  1589. } while (node >= 0);
  1590. return -EINVAL;
  1591. }
  1592. static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
  1593. {
  1594. struct pxa3xx_nand_platform_data *pdata;
  1595. int ret, cs, probe_success;
  1596. ret = pxa3xx_nand_probe_dt(info);
  1597. if (ret)
  1598. return ret;
  1599. pdata = info->pdata;
  1600. ret = alloc_nand_resource(info);
  1601. if (ret) {
  1602. dev_err(&pdev->dev, "alloc nand resource failed\n");
  1603. return ret;
  1604. }
  1605. probe_success = 0;
  1606. for (cs = 0; cs < pdata->num_cs; cs++) {
  1607. struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
  1608. /*
  1609. * The mtd name matches the one used in 'mtdparts' kernel
  1610. * parameter. This name cannot be changed or otherwise
  1611. * user's mtd partitions configuration would get broken.
  1612. */
  1613. mtd->name = "pxa3xx_nand-0";
  1614. info->cs = cs;
  1615. ret = pxa3xx_nand_scan(mtd);
  1616. if (ret) {
  1617. dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
  1618. cs);
  1619. continue;
  1620. }
  1621. if (nand_register(cs, mtd))
  1622. continue;
  1623. probe_success = 1;
  1624. }
  1625. if (!probe_success)
  1626. return -ENODEV;
  1627. return 0;
  1628. }
  1629. /*
  1630. * Main initialization routine
  1631. */
  1632. void board_nand_init(void)
  1633. {
  1634. struct pxa3xx_nand_info *info;
  1635. struct pxa3xx_nand_host *host;
  1636. int ret;
  1637. info = kzalloc(sizeof(*info) +
  1638. sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1639. GFP_KERNEL);
  1640. if (!info)
  1641. return;
  1642. ret = pxa3xx_nand_probe(info);
  1643. if (ret)
  1644. return;
  1645. }