lpc32xx_nand_slc.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx SLC NAND flash controller driver
  4. *
  5. * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com>
  6. * Copyright (c) 2015 Tyco Fire Protection Products.
  7. *
  8. * Hardware ECC support original source code
  9. * Copyright (C) 2008 by NXP Semiconductors
  10. * Author: Kevin Wells
  11. */
  12. #include <common.h>
  13. #include <log.h>
  14. #include <nand.h>
  15. #include <linux/bug.h>
  16. #include <linux/mtd/nand_ecc.h>
  17. #include <linux/errno.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/config.h>
  20. #include <asm/arch/clk.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/dma.h>
  23. #include <asm/arch/cpu.h>
  24. struct lpc32xx_nand_slc_regs {
  25. u32 data;
  26. u32 addr;
  27. u32 cmd;
  28. u32 stop;
  29. u32 ctrl;
  30. u32 cfg;
  31. u32 stat;
  32. u32 int_stat;
  33. u32 ien;
  34. u32 isr;
  35. u32 icr;
  36. u32 tac;
  37. u32 tc;
  38. u32 ecc;
  39. u32 dma_data;
  40. };
  41. /* CFG register */
  42. #define CFG_CE_LOW (1 << 5)
  43. #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
  44. #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
  45. #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
  46. #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
  47. /* CTRL register */
  48. #define CTRL_SW_RESET (1 << 2)
  49. #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
  50. #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
  51. /* STAT register */
  52. #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
  53. #define STAT_NAND_READY (1 << 0)
  54. /* INT_STAT register */
  55. #define INT_STAT_TC (1 << 1)
  56. #define INT_STAT_RDY (1 << 0)
  57. /* TAC register bits, be aware of overflows */
  58. #define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
  59. #define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
  60. #define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
  61. #define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
  62. #define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
  63. #define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
  64. #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
  65. #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
  66. /* NAND ECC Layout for small page NAND devices
  67. * Note: For large page devices, the default layouts are used. */
  68. static struct nand_ecclayout lpc32xx_nand_oob_16 = {
  69. .eccbytes = 6,
  70. .eccpos = { 10, 11, 12, 13, 14, 15, },
  71. .oobfree = {
  72. { .offset = 0, .length = 4, },
  73. { .offset = 6, .length = 4, },
  74. }
  75. };
  76. #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
  77. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  78. /*
  79. * DMA Descriptors
  80. * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
  81. * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
  82. */
  83. static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1];
  84. static u32 ecc_buffer[8]; /* MAX ECC size */
  85. static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */
  86. /*
  87. * Helper macro for the DMA client (i.e. NAND SLC):
  88. * - to write the next DMA linked list item address
  89. * (see arch/include/asm/arch-lpc32xx/dma.h).
  90. * - to assign the DMA data register to DMA source or destination address.
  91. * - to assign the ECC register to DMA source or destination address.
  92. */
  93. #define lpc32xx_dmac_next_lli(x) ((u32)x)
  94. #define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data)
  95. #define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
  96. #endif
  97. static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
  98. = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
  99. static void lpc32xx_nand_init(void)
  100. {
  101. uint32_t hclk = get_hclk_clk_rate();
  102. /* Reset SLC NAND controller */
  103. writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
  104. /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
  105. writel(0, &lpc32xx_nand_slc_regs->cfg);
  106. /* Interrupts disabled and cleared */
  107. writel(0, &lpc32xx_nand_slc_regs->ien);
  108. writel(INT_STAT_TC | INT_STAT_RDY,
  109. &lpc32xx_nand_slc_regs->icr);
  110. /* Configure NAND flash timings */
  111. writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
  112. TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
  113. TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
  114. TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
  115. TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
  116. TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
  117. TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
  118. TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
  119. &lpc32xx_nand_slc_regs->tac);
  120. }
  121. static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
  122. int cmd, unsigned int ctrl)
  123. {
  124. debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
  125. if (ctrl & NAND_NCE)
  126. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
  127. else
  128. clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
  129. if (cmd == NAND_CMD_NONE)
  130. return;
  131. if (ctrl & NAND_CLE)
  132. writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
  133. else if (ctrl & NAND_ALE)
  134. writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
  135. }
  136. static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
  137. {
  138. return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
  139. }
  140. #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
  141. /*
  142. * Prepares DMA descriptors for NAND RD/WR operations
  143. * If the size is < 256 Bytes then it is assumed to be
  144. * an OOB transfer
  145. */
  146. static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
  147. const u8 *buffer, int size,
  148. int read)
  149. {
  150. u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
  151. struct lpc32xx_dmac_ll *dmalist_cur;
  152. struct lpc32xx_dmac_ll *dmalist_cur_ecc;
  153. /*
  154. * CTRL descriptor entry for reading ECC
  155. * Copy Multiple times to sync DMA with Flash Controller
  156. */
  157. ecc_ctrl = 0x5 |
  158. DMAC_CHAN_SRC_BURST_1 |
  159. DMAC_CHAN_DEST_BURST_1 |
  160. DMAC_CHAN_SRC_WIDTH_32 |
  161. DMAC_CHAN_DEST_WIDTH_32 |
  162. DMAC_CHAN_DEST_AHB1;
  163. /* CTRL descriptor entry for reading/writing Data */
  164. ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
  165. DMAC_CHAN_SRC_BURST_4 |
  166. DMAC_CHAN_DEST_BURST_4 |
  167. DMAC_CHAN_SRC_WIDTH_32 |
  168. DMAC_CHAN_DEST_WIDTH_32 |
  169. DMAC_CHAN_DEST_AHB1;
  170. /* CTRL descriptor entry for reading/writing Spare Area */
  171. oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) |
  172. DMAC_CHAN_SRC_BURST_4 |
  173. DMAC_CHAN_DEST_BURST_4 |
  174. DMAC_CHAN_SRC_WIDTH_32 |
  175. DMAC_CHAN_DEST_WIDTH_32 |
  176. DMAC_CHAN_DEST_AHB1;
  177. if (read) {
  178. dmasrc = lpc32xx_dmac_set_dma_data();
  179. dmadst = (u32)buffer;
  180. ctrl |= DMAC_CHAN_DEST_AUTOINC;
  181. } else {
  182. dmadst = lpc32xx_dmac_set_dma_data();
  183. dmasrc = (u32)buffer;
  184. ctrl |= DMAC_CHAN_SRC_AUTOINC;
  185. }
  186. /*
  187. * Write Operation Sequence for Small Block NAND
  188. * ----------------------------------------------------------
  189. * 1. X'fer 256 bytes of data from Memory to Flash.
  190. * 2. Copy generated ECC data from Register to Spare Area
  191. * 3. X'fer next 256 bytes of data from Memory to Flash.
  192. * 4. Copy generated ECC data from Register to Spare Area.
  193. * 5. X'fer 16 byets of Spare area from Memory to Flash.
  194. * Read Operation Sequence for Small Block NAND
  195. * ----------------------------------------------------------
  196. * 1. X'fer 256 bytes of data from Flash to Memory.
  197. * 2. Copy generated ECC data from Register to ECC calc Buffer.
  198. * 3. X'fer next 256 bytes of data from Flash to Memory.
  199. * 4. Copy generated ECC data from Register to ECC calc Buffer.
  200. * 5. X'fer 16 bytes of Spare area from Flash to Memory.
  201. * Write Operation Sequence for Large Block NAND
  202. * ----------------------------------------------------------
  203. * 1. Steps(1-4) of Write Operations repeate for four times
  204. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  205. * data & 32 bytes of ECC data.
  206. * 2. X'fer 64 bytes of Spare area from Memory to Flash.
  207. * Read Operation Sequence for Large Block NAND
  208. * ----------------------------------------------------------
  209. * 1. Steps(1-4) of Read Operations repeate for four times
  210. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  211. * data & 32 bytes of ECC data.
  212. * 2. X'fer 64 bytes of Spare area from Flash to Memory.
  213. */
  214. for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
  215. dmalist_cur = &dmalist[i * 2];
  216. dmalist_cur_ecc = &dmalist[(i * 2) + 1];
  217. dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
  218. dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst);
  219. dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc);
  220. dmalist_cur->next_ctrl = ctrl;
  221. dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc();
  222. dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i];
  223. dmalist_cur_ecc->next_lli =
  224. lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]);
  225. dmalist_cur_ecc->next_ctrl = ecc_ctrl;
  226. }
  227. if (i) { /* Data only transfer */
  228. dmalist_cur_ecc = &dmalist[(i * 2) - 1];
  229. dmalist_cur_ecc->next_lli = 0;
  230. dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN;
  231. return;
  232. }
  233. /* OOB only transfer */
  234. if (read) {
  235. dmasrc = lpc32xx_dmac_set_dma_data();
  236. dmadst = (u32)buffer;
  237. oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
  238. } else {
  239. dmadst = lpc32xx_dmac_set_dma_data();
  240. dmasrc = (u32)buffer;
  241. oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
  242. }
  243. /* Read/ Write Spare Area Data To/From Flash */
  244. dmalist_cur = &dmalist[i * 2];
  245. dmalist_cur->dma_src = dmasrc;
  246. dmalist_cur->dma_dest = dmadst;
  247. dmalist_cur->next_lli = 0;
  248. dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
  249. }
  250. static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
  251. int len, int read)
  252. {
  253. struct nand_chip *chip = mtd_to_nand(mtd);
  254. u32 config;
  255. int ret;
  256. /* DMA Channel Configuration */
  257. config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) |
  258. (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) |
  259. (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) |
  260. DMAC_CHAN_ENABLE;
  261. /* Prepare DMA descriptors */
  262. lpc32xx_nand_dma_configure(chip, buf, len, read);
  263. /* Setup SLC controller and start transfer */
  264. if (read)
  265. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
  266. else /* NAND_ECC_WRITE */
  267. clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
  268. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST);
  269. /* Write length for new transfers */
  270. if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) |
  271. readl(&lpc32xx_nand_slc_regs->tc))) {
  272. int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0;
  273. writel(len + tmp, &lpc32xx_nand_slc_regs->tc);
  274. }
  275. setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
  276. /* Start DMA transfers */
  277. ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config);
  278. if (unlikely(ret < 0))
  279. BUG();
  280. /* Wait for NAND to be ready */
  281. while (!lpc32xx_nand_dev_ready(mtd))
  282. ;
  283. /* Wait till DMA transfer is DONE */
  284. if (lpc32xx_dma_wait_status(dmachan))
  285. pr_err("NAND DMA transfer error!\r\n");
  286. /* Stop DMA & HW ECC */
  287. clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
  288. clrbits_le32(&lpc32xx_nand_slc_regs->cfg,
  289. CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC);
  290. }
  291. static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
  292. {
  293. int i;
  294. for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
  295. i += CONFIG_SYS_NAND_ECCBYTES) {
  296. u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
  297. ce = ~(ce << 2) & 0xFFFFFF;
  298. spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
  299. spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
  300. spare[i] = (u8)(ce & 0xFF);
  301. }
  302. return 0;
  303. }
  304. static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
  305. uint8_t *ecc_code)
  306. {
  307. return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS);
  308. }
  309. /*
  310. * Enables and prepares SLC NAND controller
  311. * for doing data transfers with H/W ECC enabled.
  312. */
  313. static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode)
  314. {
  315. /* Clear ECC */
  316. writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl);
  317. /* Setup SLC controller for H/W ECC operations */
  318. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC);
  319. }
  320. /*
  321. * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s)
  322. * mtd: MTD block structure
  323. * dat: raw data read from the chip
  324. * read_ecc: ECC from the chip
  325. * calc_ecc: the ECC calculated from raw data
  326. *
  327. * Detect and correct a 1 bit error for 256 byte block
  328. */
  329. int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
  330. u_char *read_ecc, u_char *calc_ecc)
  331. {
  332. unsigned int i;
  333. int ret1, ret2 = 0;
  334. u_char *r = read_ecc;
  335. u_char *c = calc_ecc;
  336. u16 data_offset = 0;
  337. for (i = 0 ; i < ECCSTEPS ; i++) {
  338. r += CONFIG_SYS_NAND_ECCBYTES;
  339. c += CONFIG_SYS_NAND_ECCBYTES;
  340. data_offset += CONFIG_SYS_NAND_ECCSIZE;
  341. ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
  342. if (ret1 < 0)
  343. return -EBADMSG;
  344. else
  345. ret2 += ret1;
  346. }
  347. return ret2;
  348. }
  349. static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  350. {
  351. lpc32xx_nand_xfer(mtd, buf, len, 1);
  352. }
  353. static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  354. int len)
  355. {
  356. lpc32xx_nand_xfer(mtd, buf, len, 0);
  357. }
  358. /* Reuse the logic from "nand_read_page_hwecc()" */
  359. static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  360. uint8_t *buf, int oob_required, int page)
  361. {
  362. int i;
  363. int stat;
  364. uint8_t *p = buf;
  365. uint8_t *ecc_calc = chip->buffers->ecccalc;
  366. uint8_t *ecc_code = chip->buffers->ecccode;
  367. uint32_t *eccpos = chip->ecc.layout->eccpos;
  368. unsigned int max_bitflips = 0;
  369. /*
  370. * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
  371. * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
  372. * of a page size using DMA controller scatter/gather mode through
  373. * linked list; the ECC read is done without any software intervention.
  374. */
  375. lpc32xx_hwecc_enable(mtd, NAND_ECC_READ);
  376. lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
  377. lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
  378. lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  379. for (i = 0; i < chip->ecc.total; i++)
  380. ecc_code[i] = chip->oob_poi[eccpos[i]];
  381. stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]);
  382. if (stat < 0)
  383. mtd->ecc_stats.failed++;
  384. else {
  385. mtd->ecc_stats.corrected += stat;
  386. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  387. }
  388. return max_bitflips;
  389. }
  390. /* Reuse the logic from "nand_write_page_hwecc()" */
  391. static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
  392. struct nand_chip *chip,
  393. const uint8_t *buf, int oob_required,
  394. int page)
  395. {
  396. int i;
  397. uint8_t *ecc_calc = chip->buffers->ecccalc;
  398. const uint8_t *p = buf;
  399. uint32_t *eccpos = chip->ecc.layout->eccpos;
  400. /*
  401. * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
  402. * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
  403. * of a page size using DMA controller scatter/gather mode through
  404. * linked list; the ECC read is done without any software intervention.
  405. */
  406. lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE);
  407. lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
  408. lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
  409. for (i = 0; i < chip->ecc.total; i++)
  410. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  411. lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  412. return 0;
  413. }
  414. #else
  415. static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  416. {
  417. while (len-- > 0)
  418. *buf++ = readl(&lpc32xx_nand_slc_regs->data);
  419. }
  420. static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  421. {
  422. while (len-- > 0)
  423. writel(*buf++, &lpc32xx_nand_slc_regs->data);
  424. }
  425. #endif
  426. static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
  427. {
  428. return readl(&lpc32xx_nand_slc_regs->data);
  429. }
  430. static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
  431. {
  432. writel(byte, &lpc32xx_nand_slc_regs->data);
  433. }
  434. /*
  435. * LPC32xx has only one SLC NAND controller, don't utilize
  436. * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
  437. * both in SPL NAND and U-Boot images.
  438. */
  439. int board_nand_init(struct nand_chip *lpc32xx_chip)
  440. {
  441. #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
  442. int ret;
  443. /* Acquire a channel for our use */
  444. ret = lpc32xx_dma_get_channel();
  445. if (unlikely(ret < 0)) {
  446. pr_info("Unable to get free DMA channel for NAND transfers\n");
  447. return -1;
  448. }
  449. dmachan = (unsigned int)ret;
  450. #endif
  451. lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
  452. lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
  453. /*
  454. * The implementation of these functions is quite common, but
  455. * they MUST be defined, because access to data register
  456. * is strictly 32-bit aligned.
  457. */
  458. lpc32xx_chip->read_byte = lpc32xx_read_byte;
  459. lpc32xx_chip->write_byte = lpc32xx_write_byte;
  460. #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
  461. /* Hardware ECC calculation is supported when DMA driver is selected */
  462. lpc32xx_chip->ecc.mode = NAND_ECC_HW;
  463. lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
  464. lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
  465. lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
  466. lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
  467. lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
  468. lpc32xx_chip->chip_delay = 2000;
  469. lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
  470. lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc;
  471. lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
  472. #else
  473. /*
  474. * Hardware ECC calculation is not supported by the driver,
  475. * because it requires DMA support, see LPC32x0 User Manual,
  476. * note after SLC_ECC register description (UM10326, p.198)
  477. */
  478. lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
  479. /*
  480. * The implementation of these functions is quite common, but
  481. * they MUST be defined, because access to data register
  482. * is strictly 32-bit aligned.
  483. */
  484. lpc32xx_chip->read_buf = lpc32xx_read_buf;
  485. lpc32xx_chip->write_buf = lpc32xx_write_buf;
  486. #endif
  487. /*
  488. * These values are predefined
  489. * for both small and large page NAND flash devices.
  490. */
  491. lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
  492. lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
  493. lpc32xx_chip->ecc.strength = 1;
  494. if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
  495. lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
  496. #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
  497. lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
  498. #endif
  499. /* Initialize NAND interface */
  500. lpc32xx_nand_init();
  501. return 0;
  502. }