pci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. *
  18. * (C) Copyright 2011
  19. * Linaro
  20. * Linus Walleij <linus.walleij@linaro.org>
  21. */
  22. #include <common.h>
  23. #include <init.h>
  24. #include <log.h>
  25. #include <pci.h>
  26. #include <asm/io.h>
  27. #include <linux/bug.h>
  28. #include "integrator-sc.h"
  29. #include "pci_v3.h"
  30. #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
  31. #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
  32. /*
  33. * These are in the physical addresses on the CPU side, i.e.
  34. * where we read and write stuff - you don't want to try to
  35. * move these around
  36. */
  37. #define PHYS_PCI_MEM_BASE 0x40000000
  38. #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
  39. #define PHYS_PCI_CONFIG_BASE 0x61000000
  40. #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
  41. #define SZ_256M 0x10000000
  42. /*
  43. * These are in the PCI BUS address space
  44. * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
  45. * we follow the example of the kernel, because that is the address
  46. * range that devices actually use - what would they be doing at
  47. * 0x40000000?
  48. */
  49. #define PCI_BUS_NONMEM_START 0x00000000
  50. #define PCI_BUS_NONMEM_SIZE SZ_256M
  51. #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
  52. #define PCI_BUS_PREMEM_SIZE SZ_256M
  53. #if PCI_BUS_NONMEM_START & 0x000fffff
  54. #error PCI_BUS_NONMEM_START must be megabyte aligned
  55. #endif
  56. #if PCI_BUS_PREMEM_START & 0x000fffff
  57. #error PCI_BUS_PREMEM_START must be megabyte aligned
  58. #endif
  59. /*
  60. * Initialize PCI Devices, report devices found.
  61. */
  62. #ifndef CONFIG_PCI_PNP
  63. #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
  64. #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
  65. static struct pci_config_table pci_integrator_config_table[] = {
  66. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
  67. pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  68. PCI_ENET0_MEMADDR,
  69. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
  70. { }
  71. };
  72. #endif /* CONFIG_PCI_PNP */
  73. /* V3 access routines */
  74. #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  75. #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  76. #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  77. #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  78. #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  79. #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  80. static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
  81. {
  82. unsigned int address, mapaddress;
  83. unsigned int busnr = PCI_BUS(bdf);
  84. unsigned int devfn = PCI_FUNC(bdf);
  85. /*
  86. * Trap out illegal values
  87. */
  88. if (offset > 255)
  89. BUG();
  90. if (busnr > 255)
  91. BUG();
  92. if (devfn > 255)
  93. BUG();
  94. if (busnr == 0) {
  95. /*
  96. * Linux calls the thing U-Boot calls "DEV" "SLOT"
  97. * instead, but it's the same 5 bits
  98. */
  99. int slot = PCI_DEV(bdf);
  100. /*
  101. * local bus segment so need a type 0 config cycle
  102. *
  103. * build the PCI configuration "address" with one-hot in
  104. * A31-A11
  105. *
  106. * mapaddress:
  107. * 3:1 = config cycle (101)
  108. * 0 = PCI A1 & A0 are 0 (0)
  109. */
  110. address = PCI_FUNC(bdf) << 8;
  111. mapaddress = V3_LB_MAP_TYPE_CONFIG;
  112. if (slot > 12)
  113. /*
  114. * high order bits are handled by the MAP register
  115. */
  116. mapaddress |= 1 << (slot - 5);
  117. else
  118. /*
  119. * low order bits handled directly in the address
  120. */
  121. address |= 1 << (slot + 11);
  122. } else {
  123. /*
  124. * not the local bus segment so need a type 1 config cycle
  125. *
  126. * address:
  127. * 23:16 = bus number
  128. * 15:11 = slot number (7:3 of devfn)
  129. * 10:8 = func number (2:0 of devfn)
  130. *
  131. * mapaddress:
  132. * 3:1 = config cycle (101)
  133. * 0 = PCI A1 & A0 from host bus (1)
  134. */
  135. mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
  136. address = (busnr << 16) | (devfn << 8);
  137. }
  138. /*
  139. * Set up base0 to see all 512Mbytes of memory space (not
  140. * prefetchable), this frees up base1 for re-use by
  141. * configuration memory
  142. */
  143. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  144. V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
  145. /*
  146. * Set up base1/map1 to point into configuration space.
  147. */
  148. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
  149. V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
  150. v3_writew(V3_LB_MAP1, mapaddress);
  151. return PHYS_PCI_CONFIG_BASE + address + offset;
  152. }
  153. static void v3_close_config_window(void)
  154. {
  155. /*
  156. * Reassign base1 for use by prefetchable PCI memory
  157. */
  158. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
  159. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
  160. V3_LB_BASE_ENABLE);
  161. v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
  162. V3_LB_MAP_TYPE_MEM_MULTIPLE);
  163. /*
  164. * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
  165. */
  166. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  167. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
  168. }
  169. static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
  170. int offset, unsigned char *val)
  171. {
  172. unsigned long addr;
  173. addr = v3_open_config_window(bdf, offset);
  174. *val = __raw_readb(addr);
  175. v3_close_config_window();
  176. return 0;
  177. }
  178. static int pci_integrator_read__word(struct pci_controller *hose,
  179. pci_dev_t bdf, int offset,
  180. unsigned short *val)
  181. {
  182. unsigned long addr;
  183. addr = v3_open_config_window(bdf, offset);
  184. *val = __raw_readw(addr);
  185. v3_close_config_window();
  186. return 0;
  187. }
  188. static int pci_integrator_read_dword(struct pci_controller *hose,
  189. pci_dev_t bdf, int offset,
  190. unsigned int *val)
  191. {
  192. unsigned long addr;
  193. addr = v3_open_config_window(bdf, offset);
  194. *val = __raw_readl(addr);
  195. v3_close_config_window();
  196. return 0;
  197. }
  198. static int pci_integrator_write_byte(struct pci_controller *hose,
  199. pci_dev_t bdf, int offset,
  200. unsigned char val)
  201. {
  202. unsigned long addr;
  203. addr = v3_open_config_window(bdf, offset);
  204. __raw_writeb((u8)val, addr);
  205. __raw_readb(addr);
  206. v3_close_config_window();
  207. return 0;
  208. }
  209. static int pci_integrator_write_word(struct pci_controller *hose,
  210. pci_dev_t bdf, int offset,
  211. unsigned short val)
  212. {
  213. unsigned long addr;
  214. addr = v3_open_config_window(bdf, offset);
  215. __raw_writew((u8)val, addr);
  216. __raw_readw(addr);
  217. v3_close_config_window();
  218. return 0;
  219. }
  220. static int pci_integrator_write_dword(struct pci_controller *hose,
  221. pci_dev_t bdf, int offset,
  222. unsigned int val)
  223. {
  224. unsigned long addr;
  225. addr = v3_open_config_window(bdf, offset);
  226. __raw_writel((u8)val, addr);
  227. __raw_readl(addr);
  228. v3_close_config_window();
  229. return 0;
  230. }
  231. struct pci_controller integrator_hose = {
  232. #ifndef CONFIG_PCI_PNP
  233. config_table: pci_integrator_config_table,
  234. #endif
  235. };
  236. void pci_init_board(void)
  237. {
  238. struct pci_controller *hose = &integrator_hose;
  239. u16 val;
  240. /* setting this register will take the V3 out of reset */
  241. __raw_writel(SC_PCI_PCIEN, SC_PCI);
  242. /* Wait for 230 ms (from spec) before accessing any V3 registers */
  243. mdelay(230);
  244. /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
  245. v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
  246. /* Wait for the mailbox to settle */
  247. do {
  248. v3_writeb(V3_MAIL_DATA, 0xAA);
  249. v3_writeb(V3_MAIL_DATA + 4, 0x55);
  250. } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
  251. v3_readb(V3_MAIL_DATA + 4) != 0x55);
  252. /* Make sure that V3 register access is not locked, if it is, unlock it */
  253. if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
  254. v3_writew(V3_SYSTEM, 0xA05F);
  255. /*
  256. * Ensure that the slave accesses from PCI are disabled while we
  257. * setup memory windows
  258. */
  259. val = v3_readw(V3_PCI_CMD);
  260. val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
  261. v3_writew(V3_PCI_CMD, val);
  262. /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
  263. val = v3_readw(V3_SYSTEM);
  264. val &= ~V3_SYSTEM_M_RST_OUT;
  265. v3_writew(V3_SYSTEM, val);
  266. /* Make all accesses from PCI space retry until we're ready for them */
  267. val = v3_readw(V3_PCI_CFG);
  268. val |= V3_PCI_CFG_M_RETRY_EN;
  269. v3_writew(V3_PCI_CFG, val);
  270. /*
  271. * Set up any V3 PCI Configuration Registers that we absolutely have to.
  272. * LB_CFG controls Local Bus protocol.
  273. * Enable LocalBus byte strobes for READ accesses too.
  274. * set bit 7 BE_IMODE and bit 6 BE_OMODE
  275. */
  276. val = v3_readw(V3_LB_CFG);
  277. val |= 0x0C0;
  278. v3_writew(V3_LB_CFG, val);
  279. /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
  280. val = v3_readw(V3_PCI_CMD);
  281. val |= V3_COMMAND_M_MASTER_EN;
  282. v3_writew(V3_PCI_CMD, val);
  283. /*
  284. * PCI_MAP0 controls where the PCI to CPU memory window is on
  285. * Local Bus
  286. */
  287. v3_writel(V3_PCI_MAP0,
  288. (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
  289. V3_PCI_MAP_M_REG_EN |
  290. V3_PCI_MAP_M_ENABLE));
  291. /* PCI_BASE0 is the PCI address of the start of the window */
  292. v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
  293. /* PCI_MAP1 is LOCAL address of the start of the window */
  294. v3_writel(V3_PCI_MAP1,
  295. (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
  296. V3_PCI_MAP_M_REG_EN |
  297. V3_PCI_MAP_M_ENABLE));
  298. /* PCI_BASE1 is the PCI address of the start of the window */
  299. v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
  300. /*
  301. * Set up memory the windows from local bus memory into PCI
  302. * configuration, I/O and Memory regions.
  303. * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
  304. */
  305. v3_writew(V3_LB_BASE2,
  306. v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
  307. v3_writew(V3_LB_MAP2, 0);
  308. /* PCI Configuration, use LB_BASE1/LB_MAP1. */
  309. /*
  310. * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
  311. * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
  312. */
  313. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  314. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
  315. v3_writew(V3_LB_MAP0,
  316. v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
  317. /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
  318. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
  319. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
  320. V3_LB_BASE_ENABLE);
  321. v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
  322. V3_LB_MAP_TYPE_MEM_MULTIPLE);
  323. /* Dump PCI to local address space mappings */
  324. debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
  325. debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
  326. debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
  327. debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
  328. debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
  329. debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
  330. debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
  331. /*
  332. * Allow accesses to PCI Configuration space and set up A1, A0 for
  333. * type 1 config cycles
  334. */
  335. val = v3_readw(V3_PCI_CFG);
  336. val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
  337. val |= V3_PCI_CFG_M_AD_LOW0;
  338. v3_writew(V3_PCI_CFG, val);
  339. /* now we can allow incoming PCI MEMORY accesses */
  340. val = v3_readw(V3_PCI_CMD);
  341. val |= V3_COMMAND_M_MEM_EN;
  342. v3_writew(V3_PCI_CMD, val);
  343. /*
  344. * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
  345. * now initialise.
  346. */
  347. val = v3_readw(V3_SYSTEM);
  348. val |= V3_SYSTEM_M_RST_OUT;
  349. v3_writew(V3_SYSTEM, val);
  350. /* Lock the V3 system register so that no one else can play with it */
  351. val = v3_readw(V3_SYSTEM);
  352. val |= V3_SYSTEM_M_LOCK;
  353. v3_writew(V3_SYSTEM, val);
  354. /*
  355. * Configure and register the PCI hose
  356. */
  357. hose->first_busno = 0;
  358. hose->last_busno = 0xff;
  359. /* System memory space, window 0 256 MB non-prefetchable */
  360. pci_set_region(hose->regions + 0,
  361. PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
  362. SZ_256M,
  363. PCI_REGION_MEM);
  364. /* System memory space, window 1 256 MB prefetchable */
  365. pci_set_region(hose->regions + 1,
  366. PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
  367. SZ_256M,
  368. PCI_REGION_MEM |
  369. PCI_REGION_PREFETCH);
  370. /* PCI I/O space */
  371. pci_set_region(hose->regions + 2,
  372. 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
  373. PCI_REGION_IO);
  374. /* PCI Memory - config space */
  375. pci_set_region(hose->regions + 3,
  376. 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
  377. PCI_REGION_MEM);
  378. /* PCI V3 regs */
  379. pci_set_region(hose->regions + 4,
  380. 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
  381. PCI_REGION_MEM);
  382. hose->region_count = 5;
  383. pci_set_ops(hose,
  384. pci_integrator_read_byte,
  385. pci_integrator_read__word,
  386. pci_integrator_read_dword,
  387. pci_integrator_write_byte,
  388. pci_integrator_write_word,
  389. pci_integrator_write_dword);
  390. pci_register_hose(hose);
  391. pciauto_config_init(hose);
  392. pciauto_config_device(hose, 0);
  393. hose->last_busno = pci_hose_scan(hose);
  394. }