cache.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/cache.h>
  9. #include <asm/cacheops.h>
  10. #ifdef CONFIG_MIPS_L2_CACHE
  11. #include <asm/cm.h>
  12. #endif
  13. #include <asm/io.h>
  14. #include <asm/mipsregs.h>
  15. #include <asm/system.h>
  16. #include <linux/bug.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static void probe_l2(void)
  19. {
  20. #ifdef CONFIG_MIPS_L2_CACHE
  21. unsigned long conf2, sl;
  22. bool l2c = false;
  23. if (!(read_c0_config1() & MIPS_CONF_M))
  24. return;
  25. conf2 = read_c0_config2();
  26. if (__mips_isa_rev >= 6) {
  27. l2c = conf2 & MIPS_CONF_M;
  28. if (l2c)
  29. l2c = read_c0_config3() & MIPS_CONF_M;
  30. if (l2c)
  31. l2c = read_c0_config4() & MIPS_CONF_M;
  32. if (l2c)
  33. l2c = read_c0_config5() & MIPS_CONF5_L2C;
  34. }
  35. if (l2c && config_enabled(CONFIG_MIPS_CM)) {
  36. gd->arch.l2_line_size = mips_cm_l2_line_size();
  37. } else if (l2c) {
  38. /* We don't know how to retrieve L2 config on this system */
  39. BUG();
  40. } else {
  41. sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
  42. gd->arch.l2_line_size = sl ? (2 << sl) : 0;
  43. }
  44. #endif
  45. }
  46. void mips_cache_probe(void)
  47. {
  48. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  49. unsigned long conf1, il, dl;
  50. conf1 = read_c0_config1();
  51. il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
  52. dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
  53. gd->arch.l1i_line_size = il ? (2 << il) : 0;
  54. gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
  55. #endif
  56. probe_l2();
  57. }
  58. static inline unsigned long icache_line_size(void)
  59. {
  60. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  61. return gd->arch.l1i_line_size;
  62. #else
  63. return CONFIG_SYS_ICACHE_LINE_SIZE;
  64. #endif
  65. }
  66. static inline unsigned long dcache_line_size(void)
  67. {
  68. #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  69. return gd->arch.l1d_line_size;
  70. #else
  71. return CONFIG_SYS_DCACHE_LINE_SIZE;
  72. #endif
  73. }
  74. static inline unsigned long scache_line_size(void)
  75. {
  76. #ifdef CONFIG_MIPS_L2_CACHE
  77. return gd->arch.l2_line_size;
  78. #else
  79. return CONFIG_SYS_SCACHE_LINE_SIZE;
  80. #endif
  81. }
  82. #define cache_loop(start, end, lsize, ops...) do { \
  83. const void *addr = (const void *)(start & ~(lsize - 1)); \
  84. const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
  85. const unsigned int cache_ops[] = { ops }; \
  86. unsigned int i; \
  87. \
  88. if (!lsize) \
  89. break; \
  90. \
  91. for (; addr <= aend; addr += lsize) { \
  92. for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
  93. mips_cache(cache_ops[i], addr); \
  94. } \
  95. } while (0)
  96. void flush_cache(ulong start_addr, ulong size)
  97. {
  98. unsigned long ilsize = icache_line_size();
  99. unsigned long dlsize = dcache_line_size();
  100. unsigned long slsize = scache_line_size();
  101. /* aend will be miscalculated when size is zero, so we return here */
  102. if (size == 0)
  103. return;
  104. if ((ilsize == dlsize) && !slsize) {
  105. /* flush I-cache & D-cache simultaneously */
  106. cache_loop(start_addr, start_addr + size, ilsize,
  107. HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
  108. goto ops_done;
  109. }
  110. /* flush D-cache */
  111. cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
  112. /* flush L2 cache */
  113. cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
  114. /* flush I-cache */
  115. cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
  116. ops_done:
  117. /* ensure cache ops complete before any further memory accesses */
  118. sync();
  119. /* ensure the pipeline doesn't contain now-invalid instructions */
  120. instruction_hazard_barrier();
  121. }
  122. void __weak flush_dcache_range(ulong start_addr, ulong stop)
  123. {
  124. unsigned long lsize = dcache_line_size();
  125. unsigned long slsize = scache_line_size();
  126. /* aend will be miscalculated when size is zero, so we return here */
  127. if (start_addr == stop)
  128. return;
  129. cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
  130. /* flush L2 cache */
  131. cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
  132. /* ensure cache ops complete before any further memory accesses */
  133. sync();
  134. }
  135. void invalidate_dcache_range(ulong start_addr, ulong stop)
  136. {
  137. unsigned long lsize = dcache_line_size();
  138. unsigned long slsize = scache_line_size();
  139. /* aend will be miscalculated when size is zero, so we return here */
  140. if (start_addr == stop)
  141. return;
  142. /* invalidate L2 cache */
  143. cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
  144. cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
  145. /* ensure cache ops complete before any further memory accesses */
  146. sync();
  147. }
  148. int dcache_status(void)
  149. {
  150. unsigned int cca = read_c0_config() & CONF_CM_CMASK;
  151. return cca != CONF_CM_UNCACHED;
  152. }
  153. void dcache_enable(void)
  154. {
  155. puts("Not supported!\n");
  156. }
  157. void dcache_disable(void)
  158. {
  159. /* change CCA to uncached */
  160. change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
  161. /* ensure the pipeline doesn't contain now-invalid instructions */
  162. instruction_hazard_barrier();
  163. }