options.c 32 KB

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  1. /*
  2. * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <hwconfig.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr.h>
  10. /*
  11. * Use our own stack based buffer before relocation to allow accessing longer
  12. * hwconfig strings that might be in the environment before we've relocated.
  13. * This is pretty fragile on both the use of stack and if the buffer is big
  14. * enough. However we will get a warning from getenv_f for the later.
  15. */
  16. /* Board-specific functions defined in each board's ddr.c */
  17. extern void fsl_ddr_board_options(memctl_options_t *popts,
  18. dimm_params_t *pdimm,
  19. unsigned int ctrl_num);
  20. struct dynamic_odt {
  21. unsigned int odt_rd_cfg;
  22. unsigned int odt_wr_cfg;
  23. unsigned int odt_rtt_norm;
  24. unsigned int odt_rtt_wr;
  25. };
  26. #ifdef CONFIG_SYS_FSL_DDR4
  27. /* Quad rank is not verified yet due availability.
  28. * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
  29. */
  30. static const struct dynamic_odt single_Q[4] = {
  31. { /* cs0 */
  32. FSL_DDR_ODT_NEVER,
  33. FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  34. DDR4_RTT_34_OHM, /* unverified */
  35. DDR4_RTT_120_OHM
  36. },
  37. { /* cs1 */
  38. FSL_DDR_ODT_NEVER,
  39. FSL_DDR_ODT_NEVER,
  40. DDR4_RTT_OFF,
  41. DDR4_RTT_120_OHM
  42. },
  43. { /* cs2 */
  44. FSL_DDR_ODT_NEVER,
  45. FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  46. DDR4_RTT_34_OHM,
  47. DDR4_RTT_120_OHM
  48. },
  49. { /* cs3 */
  50. FSL_DDR_ODT_NEVER,
  51. FSL_DDR_ODT_NEVER, /* tied high */
  52. DDR4_RTT_OFF,
  53. DDR4_RTT_120_OHM
  54. }
  55. };
  56. static const struct dynamic_odt single_D[4] = {
  57. { /* cs0 */
  58. FSL_DDR_ODT_NEVER,
  59. FSL_DDR_ODT_ALL,
  60. DDR4_RTT_40_OHM,
  61. DDR4_RTT_OFF
  62. },
  63. { /* cs1 */
  64. FSL_DDR_ODT_NEVER,
  65. FSL_DDR_ODT_NEVER,
  66. DDR4_RTT_OFF,
  67. DDR4_RTT_OFF
  68. },
  69. {0, 0, 0, 0},
  70. {0, 0, 0, 0}
  71. };
  72. static const struct dynamic_odt single_S[4] = {
  73. { /* cs0 */
  74. FSL_DDR_ODT_NEVER,
  75. FSL_DDR_ODT_ALL,
  76. DDR4_RTT_40_OHM,
  77. DDR4_RTT_OFF
  78. },
  79. {0, 0, 0, 0},
  80. {0, 0, 0, 0},
  81. {0, 0, 0, 0},
  82. };
  83. static const struct dynamic_odt dual_DD[4] = {
  84. { /* cs0 */
  85. FSL_DDR_ODT_NEVER,
  86. FSL_DDR_ODT_SAME_DIMM,
  87. DDR4_RTT_120_OHM,
  88. DDR4_RTT_OFF
  89. },
  90. { /* cs1 */
  91. FSL_DDR_ODT_OTHER_DIMM,
  92. FSL_DDR_ODT_OTHER_DIMM,
  93. DDR4_RTT_34_OHM,
  94. DDR4_RTT_OFF
  95. },
  96. { /* cs2 */
  97. FSL_DDR_ODT_NEVER,
  98. FSL_DDR_ODT_SAME_DIMM,
  99. DDR4_RTT_120_OHM,
  100. DDR4_RTT_OFF
  101. },
  102. { /* cs3 */
  103. FSL_DDR_ODT_OTHER_DIMM,
  104. FSL_DDR_ODT_OTHER_DIMM,
  105. DDR4_RTT_34_OHM,
  106. DDR4_RTT_OFF
  107. }
  108. };
  109. static const struct dynamic_odt dual_DS[4] = {
  110. { /* cs0 */
  111. FSL_DDR_ODT_NEVER,
  112. FSL_DDR_ODT_SAME_DIMM,
  113. DDR4_RTT_120_OHM,
  114. DDR4_RTT_OFF
  115. },
  116. { /* cs1 */
  117. FSL_DDR_ODT_OTHER_DIMM,
  118. FSL_DDR_ODT_OTHER_DIMM,
  119. DDR4_RTT_34_OHM,
  120. DDR4_RTT_OFF
  121. },
  122. { /* cs2 */
  123. FSL_DDR_ODT_OTHER_DIMM,
  124. FSL_DDR_ODT_ALL,
  125. DDR4_RTT_34_OHM,
  126. DDR4_RTT_120_OHM
  127. },
  128. {0, 0, 0, 0}
  129. };
  130. static const struct dynamic_odt dual_SD[4] = {
  131. { /* cs0 */
  132. FSL_DDR_ODT_OTHER_DIMM,
  133. FSL_DDR_ODT_ALL,
  134. DDR4_RTT_34_OHM,
  135. DDR4_RTT_120_OHM
  136. },
  137. {0, 0, 0, 0},
  138. { /* cs2 */
  139. FSL_DDR_ODT_NEVER,
  140. FSL_DDR_ODT_SAME_DIMM,
  141. DDR4_RTT_120_OHM,
  142. DDR4_RTT_OFF
  143. },
  144. { /* cs3 */
  145. FSL_DDR_ODT_OTHER_DIMM,
  146. FSL_DDR_ODT_OTHER_DIMM,
  147. DDR4_RTT_34_OHM,
  148. DDR4_RTT_OFF
  149. }
  150. };
  151. static const struct dynamic_odt dual_SS[4] = {
  152. { /* cs0 */
  153. FSL_DDR_ODT_OTHER_DIMM,
  154. FSL_DDR_ODT_ALL,
  155. DDR4_RTT_34_OHM,
  156. DDR4_RTT_120_OHM
  157. },
  158. {0, 0, 0, 0},
  159. { /* cs2 */
  160. FSL_DDR_ODT_OTHER_DIMM,
  161. FSL_DDR_ODT_ALL,
  162. DDR4_RTT_34_OHM,
  163. DDR4_RTT_120_OHM
  164. },
  165. {0, 0, 0, 0}
  166. };
  167. static const struct dynamic_odt dual_D0[4] = {
  168. { /* cs0 */
  169. FSL_DDR_ODT_NEVER,
  170. FSL_DDR_ODT_SAME_DIMM,
  171. DDR4_RTT_40_OHM,
  172. DDR4_RTT_OFF
  173. },
  174. { /* cs1 */
  175. FSL_DDR_ODT_NEVER,
  176. FSL_DDR_ODT_NEVER,
  177. DDR4_RTT_OFF,
  178. DDR4_RTT_OFF
  179. },
  180. {0, 0, 0, 0},
  181. {0, 0, 0, 0}
  182. };
  183. static const struct dynamic_odt dual_0D[4] = {
  184. {0, 0, 0, 0},
  185. {0, 0, 0, 0},
  186. { /* cs2 */
  187. FSL_DDR_ODT_NEVER,
  188. FSL_DDR_ODT_SAME_DIMM,
  189. DDR4_RTT_40_OHM,
  190. DDR4_RTT_OFF
  191. },
  192. { /* cs3 */
  193. FSL_DDR_ODT_NEVER,
  194. FSL_DDR_ODT_NEVER,
  195. DDR4_RTT_OFF,
  196. DDR4_RTT_OFF
  197. }
  198. };
  199. static const struct dynamic_odt dual_S0[4] = {
  200. { /* cs0 */
  201. FSL_DDR_ODT_NEVER,
  202. FSL_DDR_ODT_CS,
  203. DDR4_RTT_40_OHM,
  204. DDR4_RTT_OFF
  205. },
  206. {0, 0, 0, 0},
  207. {0, 0, 0, 0},
  208. {0, 0, 0, 0}
  209. };
  210. static const struct dynamic_odt dual_0S[4] = {
  211. {0, 0, 0, 0},
  212. {0, 0, 0, 0},
  213. { /* cs2 */
  214. FSL_DDR_ODT_NEVER,
  215. FSL_DDR_ODT_CS,
  216. DDR4_RTT_40_OHM,
  217. DDR4_RTT_OFF
  218. },
  219. {0, 0, 0, 0}
  220. };
  221. static const struct dynamic_odt odt_unknown[4] = {
  222. { /* cs0 */
  223. FSL_DDR_ODT_NEVER,
  224. FSL_DDR_ODT_CS,
  225. DDR4_RTT_120_OHM,
  226. DDR4_RTT_OFF
  227. },
  228. { /* cs1 */
  229. FSL_DDR_ODT_NEVER,
  230. FSL_DDR_ODT_CS,
  231. DDR4_RTT_120_OHM,
  232. DDR4_RTT_OFF
  233. },
  234. { /* cs2 */
  235. FSL_DDR_ODT_NEVER,
  236. FSL_DDR_ODT_CS,
  237. DDR4_RTT_120_OHM,
  238. DDR4_RTT_OFF
  239. },
  240. { /* cs3 */
  241. FSL_DDR_ODT_NEVER,
  242. FSL_DDR_ODT_CS,
  243. DDR4_RTT_120_OHM,
  244. DDR4_RTT_OFF
  245. }
  246. };
  247. #elif defined(CONFIG_SYS_FSL_DDR3)
  248. static const struct dynamic_odt single_Q[4] = {
  249. { /* cs0 */
  250. FSL_DDR_ODT_NEVER,
  251. FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  252. DDR3_RTT_20_OHM,
  253. DDR3_RTT_120_OHM
  254. },
  255. { /* cs1 */
  256. FSL_DDR_ODT_NEVER,
  257. FSL_DDR_ODT_NEVER, /* tied high */
  258. DDR3_RTT_OFF,
  259. DDR3_RTT_120_OHM
  260. },
  261. { /* cs2 */
  262. FSL_DDR_ODT_NEVER,
  263. FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  264. DDR3_RTT_20_OHM,
  265. DDR3_RTT_120_OHM
  266. },
  267. { /* cs3 */
  268. FSL_DDR_ODT_NEVER,
  269. FSL_DDR_ODT_NEVER, /* tied high */
  270. DDR3_RTT_OFF,
  271. DDR3_RTT_120_OHM
  272. }
  273. };
  274. static const struct dynamic_odt single_D[4] = {
  275. { /* cs0 */
  276. FSL_DDR_ODT_NEVER,
  277. FSL_DDR_ODT_ALL,
  278. DDR3_RTT_40_OHM,
  279. DDR3_RTT_OFF
  280. },
  281. { /* cs1 */
  282. FSL_DDR_ODT_NEVER,
  283. FSL_DDR_ODT_NEVER,
  284. DDR3_RTT_OFF,
  285. DDR3_RTT_OFF
  286. },
  287. {0, 0, 0, 0},
  288. {0, 0, 0, 0}
  289. };
  290. static const struct dynamic_odt single_S[4] = {
  291. { /* cs0 */
  292. FSL_DDR_ODT_NEVER,
  293. FSL_DDR_ODT_ALL,
  294. DDR3_RTT_40_OHM,
  295. DDR3_RTT_OFF
  296. },
  297. {0, 0, 0, 0},
  298. {0, 0, 0, 0},
  299. {0, 0, 0, 0},
  300. };
  301. static const struct dynamic_odt dual_DD[4] = {
  302. { /* cs0 */
  303. FSL_DDR_ODT_NEVER,
  304. FSL_DDR_ODT_SAME_DIMM,
  305. DDR3_RTT_120_OHM,
  306. DDR3_RTT_OFF
  307. },
  308. { /* cs1 */
  309. FSL_DDR_ODT_OTHER_DIMM,
  310. FSL_DDR_ODT_OTHER_DIMM,
  311. DDR3_RTT_30_OHM,
  312. DDR3_RTT_OFF
  313. },
  314. { /* cs2 */
  315. FSL_DDR_ODT_NEVER,
  316. FSL_DDR_ODT_SAME_DIMM,
  317. DDR3_RTT_120_OHM,
  318. DDR3_RTT_OFF
  319. },
  320. { /* cs3 */
  321. FSL_DDR_ODT_OTHER_DIMM,
  322. FSL_DDR_ODT_OTHER_DIMM,
  323. DDR3_RTT_30_OHM,
  324. DDR3_RTT_OFF
  325. }
  326. };
  327. static const struct dynamic_odt dual_DS[4] = {
  328. { /* cs0 */
  329. FSL_DDR_ODT_NEVER,
  330. FSL_DDR_ODT_SAME_DIMM,
  331. DDR3_RTT_120_OHM,
  332. DDR3_RTT_OFF
  333. },
  334. { /* cs1 */
  335. FSL_DDR_ODT_OTHER_DIMM,
  336. FSL_DDR_ODT_OTHER_DIMM,
  337. DDR3_RTT_30_OHM,
  338. DDR3_RTT_OFF
  339. },
  340. { /* cs2 */
  341. FSL_DDR_ODT_OTHER_DIMM,
  342. FSL_DDR_ODT_ALL,
  343. DDR3_RTT_20_OHM,
  344. DDR3_RTT_120_OHM
  345. },
  346. {0, 0, 0, 0}
  347. };
  348. static const struct dynamic_odt dual_SD[4] = {
  349. { /* cs0 */
  350. FSL_DDR_ODT_OTHER_DIMM,
  351. FSL_DDR_ODT_ALL,
  352. DDR3_RTT_20_OHM,
  353. DDR3_RTT_120_OHM
  354. },
  355. {0, 0, 0, 0},
  356. { /* cs2 */
  357. FSL_DDR_ODT_NEVER,
  358. FSL_DDR_ODT_SAME_DIMM,
  359. DDR3_RTT_120_OHM,
  360. DDR3_RTT_OFF
  361. },
  362. { /* cs3 */
  363. FSL_DDR_ODT_OTHER_DIMM,
  364. FSL_DDR_ODT_OTHER_DIMM,
  365. DDR3_RTT_20_OHM,
  366. DDR3_RTT_OFF
  367. }
  368. };
  369. static const struct dynamic_odt dual_SS[4] = {
  370. { /* cs0 */
  371. FSL_DDR_ODT_OTHER_DIMM,
  372. FSL_DDR_ODT_ALL,
  373. DDR3_RTT_30_OHM,
  374. DDR3_RTT_120_OHM
  375. },
  376. {0, 0, 0, 0},
  377. { /* cs2 */
  378. FSL_DDR_ODT_OTHER_DIMM,
  379. FSL_DDR_ODT_ALL,
  380. DDR3_RTT_30_OHM,
  381. DDR3_RTT_120_OHM
  382. },
  383. {0, 0, 0, 0}
  384. };
  385. static const struct dynamic_odt dual_D0[4] = {
  386. { /* cs0 */
  387. FSL_DDR_ODT_NEVER,
  388. FSL_DDR_ODT_SAME_DIMM,
  389. DDR3_RTT_40_OHM,
  390. DDR3_RTT_OFF
  391. },
  392. { /* cs1 */
  393. FSL_DDR_ODT_NEVER,
  394. FSL_DDR_ODT_NEVER,
  395. DDR3_RTT_OFF,
  396. DDR3_RTT_OFF
  397. },
  398. {0, 0, 0, 0},
  399. {0, 0, 0, 0}
  400. };
  401. static const struct dynamic_odt dual_0D[4] = {
  402. {0, 0, 0, 0},
  403. {0, 0, 0, 0},
  404. { /* cs2 */
  405. FSL_DDR_ODT_NEVER,
  406. FSL_DDR_ODT_SAME_DIMM,
  407. DDR3_RTT_40_OHM,
  408. DDR3_RTT_OFF
  409. },
  410. { /* cs3 */
  411. FSL_DDR_ODT_NEVER,
  412. FSL_DDR_ODT_NEVER,
  413. DDR3_RTT_OFF,
  414. DDR3_RTT_OFF
  415. }
  416. };
  417. static const struct dynamic_odt dual_S0[4] = {
  418. { /* cs0 */
  419. FSL_DDR_ODT_NEVER,
  420. FSL_DDR_ODT_CS,
  421. DDR3_RTT_40_OHM,
  422. DDR3_RTT_OFF
  423. },
  424. {0, 0, 0, 0},
  425. {0, 0, 0, 0},
  426. {0, 0, 0, 0}
  427. };
  428. static const struct dynamic_odt dual_0S[4] = {
  429. {0, 0, 0, 0},
  430. {0, 0, 0, 0},
  431. { /* cs2 */
  432. FSL_DDR_ODT_NEVER,
  433. FSL_DDR_ODT_CS,
  434. DDR3_RTT_40_OHM,
  435. DDR3_RTT_OFF
  436. },
  437. {0, 0, 0, 0}
  438. };
  439. static const struct dynamic_odt odt_unknown[4] = {
  440. { /* cs0 */
  441. FSL_DDR_ODT_NEVER,
  442. FSL_DDR_ODT_CS,
  443. DDR3_RTT_120_OHM,
  444. DDR3_RTT_OFF
  445. },
  446. { /* cs1 */
  447. FSL_DDR_ODT_NEVER,
  448. FSL_DDR_ODT_CS,
  449. DDR3_RTT_120_OHM,
  450. DDR3_RTT_OFF
  451. },
  452. { /* cs2 */
  453. FSL_DDR_ODT_NEVER,
  454. FSL_DDR_ODT_CS,
  455. DDR3_RTT_120_OHM,
  456. DDR3_RTT_OFF
  457. },
  458. { /* cs3 */
  459. FSL_DDR_ODT_NEVER,
  460. FSL_DDR_ODT_CS,
  461. DDR3_RTT_120_OHM,
  462. DDR3_RTT_OFF
  463. }
  464. };
  465. #else /* CONFIG_SYS_FSL_DDR3 */
  466. static const struct dynamic_odt single_Q[4] = {
  467. {0, 0, 0, 0},
  468. {0, 0, 0, 0},
  469. {0, 0, 0, 0},
  470. {0, 0, 0, 0}
  471. };
  472. static const struct dynamic_odt single_D[4] = {
  473. { /* cs0 */
  474. FSL_DDR_ODT_NEVER,
  475. FSL_DDR_ODT_ALL,
  476. DDR2_RTT_150_OHM,
  477. DDR2_RTT_OFF
  478. },
  479. { /* cs1 */
  480. FSL_DDR_ODT_NEVER,
  481. FSL_DDR_ODT_NEVER,
  482. DDR2_RTT_OFF,
  483. DDR2_RTT_OFF
  484. },
  485. {0, 0, 0, 0},
  486. {0, 0, 0, 0}
  487. };
  488. static const struct dynamic_odt single_S[4] = {
  489. { /* cs0 */
  490. FSL_DDR_ODT_NEVER,
  491. FSL_DDR_ODT_ALL,
  492. DDR2_RTT_150_OHM,
  493. DDR2_RTT_OFF
  494. },
  495. {0, 0, 0, 0},
  496. {0, 0, 0, 0},
  497. {0, 0, 0, 0},
  498. };
  499. static const struct dynamic_odt dual_DD[4] = {
  500. { /* cs0 */
  501. FSL_DDR_ODT_OTHER_DIMM,
  502. FSL_DDR_ODT_OTHER_DIMM,
  503. DDR2_RTT_75_OHM,
  504. DDR2_RTT_OFF
  505. },
  506. { /* cs1 */
  507. FSL_DDR_ODT_NEVER,
  508. FSL_DDR_ODT_NEVER,
  509. DDR2_RTT_OFF,
  510. DDR2_RTT_OFF
  511. },
  512. { /* cs2 */
  513. FSL_DDR_ODT_OTHER_DIMM,
  514. FSL_DDR_ODT_OTHER_DIMM,
  515. DDR2_RTT_75_OHM,
  516. DDR2_RTT_OFF
  517. },
  518. { /* cs3 */
  519. FSL_DDR_ODT_NEVER,
  520. FSL_DDR_ODT_NEVER,
  521. DDR2_RTT_OFF,
  522. DDR2_RTT_OFF
  523. }
  524. };
  525. static const struct dynamic_odt dual_DS[4] = {
  526. { /* cs0 */
  527. FSL_DDR_ODT_OTHER_DIMM,
  528. FSL_DDR_ODT_OTHER_DIMM,
  529. DDR2_RTT_75_OHM,
  530. DDR2_RTT_OFF
  531. },
  532. { /* cs1 */
  533. FSL_DDR_ODT_NEVER,
  534. FSL_DDR_ODT_NEVER,
  535. DDR2_RTT_OFF,
  536. DDR2_RTT_OFF
  537. },
  538. { /* cs2 */
  539. FSL_DDR_ODT_OTHER_DIMM,
  540. FSL_DDR_ODT_OTHER_DIMM,
  541. DDR2_RTT_75_OHM,
  542. DDR2_RTT_OFF
  543. },
  544. {0, 0, 0, 0}
  545. };
  546. static const struct dynamic_odt dual_SD[4] = {
  547. { /* cs0 */
  548. FSL_DDR_ODT_OTHER_DIMM,
  549. FSL_DDR_ODT_OTHER_DIMM,
  550. DDR2_RTT_75_OHM,
  551. DDR2_RTT_OFF
  552. },
  553. {0, 0, 0, 0},
  554. { /* cs2 */
  555. FSL_DDR_ODT_OTHER_DIMM,
  556. FSL_DDR_ODT_OTHER_DIMM,
  557. DDR2_RTT_75_OHM,
  558. DDR2_RTT_OFF
  559. },
  560. { /* cs3 */
  561. FSL_DDR_ODT_NEVER,
  562. FSL_DDR_ODT_NEVER,
  563. DDR2_RTT_OFF,
  564. DDR2_RTT_OFF
  565. }
  566. };
  567. static const struct dynamic_odt dual_SS[4] = {
  568. { /* cs0 */
  569. FSL_DDR_ODT_OTHER_DIMM,
  570. FSL_DDR_ODT_OTHER_DIMM,
  571. DDR2_RTT_75_OHM,
  572. DDR2_RTT_OFF
  573. },
  574. {0, 0, 0, 0},
  575. { /* cs2 */
  576. FSL_DDR_ODT_OTHER_DIMM,
  577. FSL_DDR_ODT_OTHER_DIMM,
  578. DDR2_RTT_75_OHM,
  579. DDR2_RTT_OFF
  580. },
  581. {0, 0, 0, 0}
  582. };
  583. static const struct dynamic_odt dual_D0[4] = {
  584. { /* cs0 */
  585. FSL_DDR_ODT_NEVER,
  586. FSL_DDR_ODT_ALL,
  587. DDR2_RTT_150_OHM,
  588. DDR2_RTT_OFF
  589. },
  590. { /* cs1 */
  591. FSL_DDR_ODT_NEVER,
  592. FSL_DDR_ODT_NEVER,
  593. DDR2_RTT_OFF,
  594. DDR2_RTT_OFF
  595. },
  596. {0, 0, 0, 0},
  597. {0, 0, 0, 0}
  598. };
  599. static const struct dynamic_odt dual_0D[4] = {
  600. {0, 0, 0, 0},
  601. {0, 0, 0, 0},
  602. { /* cs2 */
  603. FSL_DDR_ODT_NEVER,
  604. FSL_DDR_ODT_ALL,
  605. DDR2_RTT_150_OHM,
  606. DDR2_RTT_OFF
  607. },
  608. { /* cs3 */
  609. FSL_DDR_ODT_NEVER,
  610. FSL_DDR_ODT_NEVER,
  611. DDR2_RTT_OFF,
  612. DDR2_RTT_OFF
  613. }
  614. };
  615. static const struct dynamic_odt dual_S0[4] = {
  616. { /* cs0 */
  617. FSL_DDR_ODT_NEVER,
  618. FSL_DDR_ODT_CS,
  619. DDR2_RTT_150_OHM,
  620. DDR2_RTT_OFF
  621. },
  622. {0, 0, 0, 0},
  623. {0, 0, 0, 0},
  624. {0, 0, 0, 0}
  625. };
  626. static const struct dynamic_odt dual_0S[4] = {
  627. {0, 0, 0, 0},
  628. {0, 0, 0, 0},
  629. { /* cs2 */
  630. FSL_DDR_ODT_NEVER,
  631. FSL_DDR_ODT_CS,
  632. DDR2_RTT_150_OHM,
  633. DDR2_RTT_OFF
  634. },
  635. {0, 0, 0, 0}
  636. };
  637. static const struct dynamic_odt odt_unknown[4] = {
  638. { /* cs0 */
  639. FSL_DDR_ODT_NEVER,
  640. FSL_DDR_ODT_CS,
  641. DDR2_RTT_75_OHM,
  642. DDR2_RTT_OFF
  643. },
  644. { /* cs1 */
  645. FSL_DDR_ODT_NEVER,
  646. FSL_DDR_ODT_NEVER,
  647. DDR2_RTT_OFF,
  648. DDR2_RTT_OFF
  649. },
  650. { /* cs2 */
  651. FSL_DDR_ODT_NEVER,
  652. FSL_DDR_ODT_CS,
  653. DDR2_RTT_75_OHM,
  654. DDR2_RTT_OFF
  655. },
  656. { /* cs3 */
  657. FSL_DDR_ODT_NEVER,
  658. FSL_DDR_ODT_NEVER,
  659. DDR2_RTT_OFF,
  660. DDR2_RTT_OFF
  661. }
  662. };
  663. #endif
  664. /*
  665. * Automatically seleect bank interleaving mode based on DIMMs
  666. * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
  667. * This function only deal with one or two slots per controller.
  668. */
  669. static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
  670. {
  671. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  672. if (pdimm[0].n_ranks == 4)
  673. return FSL_DDR_CS0_CS1_CS2_CS3;
  674. else if (pdimm[0].n_ranks == 2)
  675. return FSL_DDR_CS0_CS1;
  676. #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  677. #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  678. if (pdimm[0].n_ranks == 4)
  679. return FSL_DDR_CS0_CS1_CS2_CS3;
  680. #endif
  681. if (pdimm[0].n_ranks == 2) {
  682. if (pdimm[1].n_ranks == 2)
  683. return FSL_DDR_CS0_CS1_CS2_CS3;
  684. else
  685. return FSL_DDR_CS0_CS1;
  686. }
  687. #endif
  688. return 0;
  689. }
  690. unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  691. memctl_options_t *popts,
  692. dimm_params_t *pdimm,
  693. unsigned int ctrl_num)
  694. {
  695. unsigned int i;
  696. char buffer[HWCONFIG_BUFFER_SIZE];
  697. char *buf = NULL;
  698. #if defined(CONFIG_SYS_FSL_DDR3) || \
  699. defined(CONFIG_SYS_FSL_DDR2) || \
  700. defined(CONFIG_SYS_FSL_DDR4)
  701. const struct dynamic_odt *pdodt = odt_unknown;
  702. #endif
  703. ulong ddr_freq;
  704. /*
  705. * Extract hwconfig from environment since we have not properly setup
  706. * the environment but need it for ddr config params
  707. */
  708. if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
  709. buf = buffer;
  710. #if defined(CONFIG_SYS_FSL_DDR3) || \
  711. defined(CONFIG_SYS_FSL_DDR2) || \
  712. defined(CONFIG_SYS_FSL_DDR4)
  713. /* Chip select options. */
  714. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  715. switch (pdimm[0].n_ranks) {
  716. case 1:
  717. pdodt = single_S;
  718. break;
  719. case 2:
  720. pdodt = single_D;
  721. break;
  722. case 4:
  723. pdodt = single_Q;
  724. break;
  725. }
  726. #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  727. switch (pdimm[0].n_ranks) {
  728. #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  729. case 4:
  730. pdodt = single_Q;
  731. if (pdimm[1].n_ranks)
  732. printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
  733. break;
  734. #endif
  735. case 2:
  736. switch (pdimm[1].n_ranks) {
  737. case 2:
  738. pdodt = dual_DD;
  739. break;
  740. case 1:
  741. pdodt = dual_DS;
  742. break;
  743. case 0:
  744. pdodt = dual_D0;
  745. break;
  746. }
  747. break;
  748. case 1:
  749. switch (pdimm[1].n_ranks) {
  750. case 2:
  751. pdodt = dual_SD;
  752. break;
  753. case 1:
  754. pdodt = dual_SS;
  755. break;
  756. case 0:
  757. pdodt = dual_S0;
  758. break;
  759. }
  760. break;
  761. case 0:
  762. switch (pdimm[1].n_ranks) {
  763. case 2:
  764. pdodt = dual_0D;
  765. break;
  766. case 1:
  767. pdodt = dual_0S;
  768. break;
  769. }
  770. break;
  771. }
  772. #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
  773. #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
  774. /* Pick chip-select local options. */
  775. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  776. #if defined(CONFIG_SYS_FSL_DDR3) || \
  777. defined(CONFIG_SYS_FSL_DDR2) || \
  778. defined(CONFIG_SYS_FSL_DDR4)
  779. popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
  780. popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
  781. popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
  782. popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
  783. #else
  784. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  785. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  786. #endif
  787. popts->cs_local_opts[i].auto_precharge = 0;
  788. }
  789. /* Pick interleaving mode. */
  790. /*
  791. * 0 = no interleaving
  792. * 1 = interleaving between 2 controllers
  793. */
  794. popts->memctl_interleaving = 0;
  795. /*
  796. * 0 = cacheline
  797. * 1 = page
  798. * 2 = (logical) bank
  799. * 3 = superbank (only if CS interleaving is enabled)
  800. */
  801. popts->memctl_interleaving_mode = 0;
  802. /*
  803. * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  804. * 1: page: bit to the left of the column bits selects the memctl
  805. * 2: bank: bit to the left of the bank bits selects the memctl
  806. * 3: superbank: bit to the left of the chip select selects the memctl
  807. *
  808. * NOTE: ba_intlv (rank interleaving) is independent of memory
  809. * controller interleaving; it is only within a memory controller.
  810. * Must use superbank interleaving if rank interleaving is used and
  811. * memory controller interleaving is enabled.
  812. */
  813. /*
  814. * 0 = no
  815. * 0x40 = CS0,CS1
  816. * 0x20 = CS2,CS3
  817. * 0x60 = CS0,CS1 + CS2,CS3
  818. * 0x04 = CS0,CS1,CS2,CS3
  819. */
  820. popts->ba_intlv_ctl = 0;
  821. /* Memory Organization Parameters */
  822. popts->registered_dimm_en = common_dimm->all_dimms_registered;
  823. /* Operational Mode Paramters */
  824. /* Pick ECC modes */
  825. popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
  826. #ifdef CONFIG_DDR_ECC
  827. if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
  828. if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
  829. popts->ecc_mode = 1;
  830. } else
  831. popts->ecc_mode = 1;
  832. #endif
  833. popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
  834. /*
  835. * Choose DQS config
  836. * 0 for DDR1
  837. * 1 for DDR2
  838. */
  839. #if defined(CONFIG_SYS_FSL_DDR1)
  840. popts->dqs_config = 0;
  841. #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
  842. popts->dqs_config = 1;
  843. #endif
  844. /* Choose self-refresh during sleep. */
  845. popts->self_refresh_in_sleep = 1;
  846. /* Choose dynamic power management mode. */
  847. popts->dynamic_power = 0;
  848. /*
  849. * check first dimm for primary sdram width
  850. * presuming all dimms are similar
  851. * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
  852. */
  853. #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
  854. if (pdimm[0].n_ranks != 0) {
  855. if ((pdimm[0].data_width >= 64) && \
  856. (pdimm[0].data_width <= 72))
  857. popts->data_bus_width = 0;
  858. else if ((pdimm[0].data_width >= 32) || \
  859. (pdimm[0].data_width <= 40))
  860. popts->data_bus_width = 1;
  861. else {
  862. panic("Error: data width %u is invalid!\n",
  863. pdimm[0].data_width);
  864. }
  865. }
  866. #else
  867. if (pdimm[0].n_ranks != 0) {
  868. if (pdimm[0].primary_sdram_width == 64)
  869. popts->data_bus_width = 0;
  870. else if (pdimm[0].primary_sdram_width == 32)
  871. popts->data_bus_width = 1;
  872. else if (pdimm[0].primary_sdram_width == 16)
  873. popts->data_bus_width = 2;
  874. else {
  875. panic("Error: primary sdram width %u is invalid!\n",
  876. pdimm[0].primary_sdram_width);
  877. }
  878. }
  879. #endif
  880. popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
  881. /* Choose burst length. */
  882. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  883. #if defined(CONFIG_E500MC)
  884. popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
  885. popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
  886. #else
  887. if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
  888. /* 32-bit or 16-bit bus */
  889. popts->otf_burst_chop_en = 0;
  890. popts->burst_length = DDR_BL8;
  891. } else {
  892. popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
  893. popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
  894. }
  895. #endif
  896. #else
  897. popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
  898. #endif
  899. /* Choose ddr controller address mirror mode */
  900. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  901. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  902. if (pdimm[i].n_ranks) {
  903. popts->mirrored_dimm = pdimm[i].mirrored_dimm;
  904. break;
  905. }
  906. }
  907. #endif
  908. /* Global Timing Parameters. */
  909. debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
  910. /* Pick a caslat override. */
  911. popts->cas_latency_override = 0;
  912. popts->cas_latency_override_value = 3;
  913. if (popts->cas_latency_override) {
  914. debug("using caslat override value = %u\n",
  915. popts->cas_latency_override_value);
  916. }
  917. /* Decide whether to use the computed derated latency */
  918. popts->use_derated_caslat = 0;
  919. /* Choose an additive latency. */
  920. popts->additive_latency_override = 0;
  921. popts->additive_latency_override_value = 3;
  922. if (popts->additive_latency_override) {
  923. debug("using additive latency override value = %u\n",
  924. popts->additive_latency_override_value);
  925. }
  926. /*
  927. * 2T_EN setting
  928. *
  929. * Factors to consider for 2T_EN:
  930. * - number of DIMMs installed
  931. * - number of components, number of active ranks
  932. * - how much time you want to spend playing around
  933. */
  934. popts->twot_en = 0;
  935. popts->threet_en = 0;
  936. /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
  937. if (popts->registered_dimm_en)
  938. popts->ap_en = 1; /* 0 = disable, 1 = enable */
  939. else
  940. popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
  941. if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
  942. if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
  943. if (popts->registered_dimm_en ||
  944. (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
  945. popts->ap_en = 1;
  946. }
  947. }
  948. /*
  949. * BSTTOPRE precharge interval
  950. *
  951. * Set this to 0 for global auto precharge
  952. * The value of 0x100 has been used for DDR1, DDR2, DDR3.
  953. * It is not wrong. Any value should be OK. The performance depends on
  954. * applications. There is no one good value for all. One way to set
  955. * is to use 1/4 of refint value.
  956. */
  957. popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
  958. >> 2;
  959. /*
  960. * Window for four activates -- tFAW
  961. *
  962. * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
  963. * FIXME: varies depending upon number of column addresses or data
  964. * FIXME: width, was considering looking at pdimm->primary_sdram_width
  965. */
  966. #if defined(CONFIG_SYS_FSL_DDR1)
  967. popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
  968. #elif defined(CONFIG_SYS_FSL_DDR2)
  969. /*
  970. * x4/x8; some datasheets have 35000
  971. * x16 wide columns only? Use 50000?
  972. */
  973. popts->tfaw_window_four_activates_ps = 37500;
  974. #else
  975. popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
  976. #endif
  977. popts->zq_en = 0;
  978. popts->wrlvl_en = 0;
  979. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  980. /*
  981. * due to ddr3 dimm is fly-by topology
  982. * we suggest to enable write leveling to
  983. * meet the tQDSS under different loading.
  984. */
  985. popts->wrlvl_en = 1;
  986. popts->zq_en = 1;
  987. popts->wrlvl_override = 0;
  988. #endif
  989. /*
  990. * Check interleaving configuration from environment.
  991. * Please refer to doc/README.fsl-ddr for the detail.
  992. *
  993. * If memory controller interleaving is enabled, then the data
  994. * bus widths must be programmed identically for all memory controllers.
  995. *
  996. * Attempt to set all controllers to the same chip select
  997. * interleaving mode. It will do a best effort to get the
  998. * requested ranks interleaved together such that the result
  999. * should be a subset of the requested configuration.
  1000. *
  1001. * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
  1002. * with 256 Byte is enabled.
  1003. */
  1004. #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
  1005. if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
  1006. #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
  1007. ;
  1008. #else
  1009. goto done;
  1010. #endif
  1011. if (pdimm[0].n_ranks == 0) {
  1012. printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
  1013. popts->memctl_interleaving = 0;
  1014. goto done;
  1015. }
  1016. popts->memctl_interleaving = 1;
  1017. #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
  1018. popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
  1019. popts->memctl_interleaving = 1;
  1020. debug("256 Byte interleaving\n");
  1021. #else
  1022. /*
  1023. * test null first. if CONFIG_HWCONFIG is not defined
  1024. * hwconfig_arg_cmp returns non-zero
  1025. */
  1026. if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
  1027. "null", buf)) {
  1028. popts->memctl_interleaving = 0;
  1029. debug("memory controller interleaving disabled.\n");
  1030. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1031. "ctlr_intlv",
  1032. "cacheline", buf)) {
  1033. popts->memctl_interleaving_mode =
  1034. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1035. 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
  1036. popts->memctl_interleaving =
  1037. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1038. 0 : 1;
  1039. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1040. "ctlr_intlv",
  1041. "page", buf)) {
  1042. popts->memctl_interleaving_mode =
  1043. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1044. 0 : FSL_DDR_PAGE_INTERLEAVING;
  1045. popts->memctl_interleaving =
  1046. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1047. 0 : 1;
  1048. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1049. "ctlr_intlv",
  1050. "bank", buf)) {
  1051. popts->memctl_interleaving_mode =
  1052. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1053. 0 : FSL_DDR_BANK_INTERLEAVING;
  1054. popts->memctl_interleaving =
  1055. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1056. 0 : 1;
  1057. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1058. "ctlr_intlv",
  1059. "superbank", buf)) {
  1060. popts->memctl_interleaving_mode =
  1061. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1062. 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
  1063. popts->memctl_interleaving =
  1064. ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
  1065. 0 : 1;
  1066. #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
  1067. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1068. "ctlr_intlv",
  1069. "3way_1KB", buf)) {
  1070. popts->memctl_interleaving_mode =
  1071. FSL_DDR_3WAY_1KB_INTERLEAVING;
  1072. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1073. "ctlr_intlv",
  1074. "3way_4KB", buf)) {
  1075. popts->memctl_interleaving_mode =
  1076. FSL_DDR_3WAY_4KB_INTERLEAVING;
  1077. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1078. "ctlr_intlv",
  1079. "3way_8KB", buf)) {
  1080. popts->memctl_interleaving_mode =
  1081. FSL_DDR_3WAY_8KB_INTERLEAVING;
  1082. #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
  1083. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1084. "ctlr_intlv",
  1085. "4way_1KB", buf)) {
  1086. popts->memctl_interleaving_mode =
  1087. FSL_DDR_4WAY_1KB_INTERLEAVING;
  1088. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1089. "ctlr_intlv",
  1090. "4way_4KB", buf)) {
  1091. popts->memctl_interleaving_mode =
  1092. FSL_DDR_4WAY_4KB_INTERLEAVING;
  1093. } else if (hwconfig_subarg_cmp_f("fsl_ddr",
  1094. "ctlr_intlv",
  1095. "4way_8KB", buf)) {
  1096. popts->memctl_interleaving_mode =
  1097. FSL_DDR_4WAY_8KB_INTERLEAVING;
  1098. #endif
  1099. } else {
  1100. popts->memctl_interleaving = 0;
  1101. printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
  1102. }
  1103. #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
  1104. done:
  1105. #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
  1106. if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
  1107. (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
  1108. /* test null first. if CONFIG_HWCONFIG is not defined,
  1109. * hwconfig_subarg_cmp_f returns non-zero */
  1110. if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1111. "null", buf))
  1112. debug("bank interleaving disabled.\n");
  1113. else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1114. "cs0_cs1", buf))
  1115. popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
  1116. else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1117. "cs2_cs3", buf))
  1118. popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
  1119. else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1120. "cs0_cs1_and_cs2_cs3", buf))
  1121. popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
  1122. else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1123. "cs0_cs1_cs2_cs3", buf))
  1124. popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
  1125. else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
  1126. "auto", buf))
  1127. popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
  1128. else
  1129. printf("hwconfig has unrecognized parameter for bank_intlv.\n");
  1130. switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
  1131. case FSL_DDR_CS0_CS1_CS2_CS3:
  1132. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  1133. if (pdimm[0].n_ranks < 4) {
  1134. popts->ba_intlv_ctl = 0;
  1135. printf("Not enough bank(chip-select) for "
  1136. "CS0+CS1+CS2+CS3 on controller %d, "
  1137. "interleaving disabled!\n", ctrl_num);
  1138. }
  1139. #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  1140. #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  1141. if (pdimm[0].n_ranks == 4)
  1142. break;
  1143. #endif
  1144. if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
  1145. popts->ba_intlv_ctl = 0;
  1146. printf("Not enough bank(chip-select) for "
  1147. "CS0+CS1+CS2+CS3 on controller %d, "
  1148. "interleaving disabled!\n", ctrl_num);
  1149. }
  1150. if (pdimm[0].capacity != pdimm[1].capacity) {
  1151. popts->ba_intlv_ctl = 0;
  1152. printf("Not identical DIMM size for "
  1153. "CS0+CS1+CS2+CS3 on controller %d, "
  1154. "interleaving disabled!\n", ctrl_num);
  1155. }
  1156. #endif
  1157. break;
  1158. case FSL_DDR_CS0_CS1:
  1159. if (pdimm[0].n_ranks < 2) {
  1160. popts->ba_intlv_ctl = 0;
  1161. printf("Not enough bank(chip-select) for "
  1162. "CS0+CS1 on controller %d, "
  1163. "interleaving disabled!\n", ctrl_num);
  1164. }
  1165. break;
  1166. case FSL_DDR_CS2_CS3:
  1167. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  1168. if (pdimm[0].n_ranks < 4) {
  1169. popts->ba_intlv_ctl = 0;
  1170. printf("Not enough bank(chip-select) for CS2+CS3 "
  1171. "on controller %d, interleaving disabled!\n", ctrl_num);
  1172. }
  1173. #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  1174. if (pdimm[1].n_ranks < 2) {
  1175. popts->ba_intlv_ctl = 0;
  1176. printf("Not enough bank(chip-select) for CS2+CS3 "
  1177. "on controller %d, interleaving disabled!\n", ctrl_num);
  1178. }
  1179. #endif
  1180. break;
  1181. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  1182. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  1183. if (pdimm[0].n_ranks < 4) {
  1184. popts->ba_intlv_ctl = 0;
  1185. printf("Not enough bank(CS) for CS0+CS1 and "
  1186. "CS2+CS3 on controller %d, "
  1187. "interleaving disabled!\n", ctrl_num);
  1188. }
  1189. #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  1190. if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
  1191. popts->ba_intlv_ctl = 0;
  1192. printf("Not enough bank(CS) for CS0+CS1 and "
  1193. "CS2+CS3 on controller %d, "
  1194. "interleaving disabled!\n", ctrl_num);
  1195. }
  1196. #endif
  1197. break;
  1198. default:
  1199. popts->ba_intlv_ctl = 0;
  1200. break;
  1201. }
  1202. }
  1203. if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
  1204. if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
  1205. popts->addr_hash = 0;
  1206. else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
  1207. "true", buf))
  1208. popts->addr_hash = 1;
  1209. }
  1210. if (pdimm[0].n_ranks == 4)
  1211. popts->quad_rank_present = 1;
  1212. ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  1213. if (popts->registered_dimm_en) {
  1214. popts->rcw_override = 1;
  1215. popts->rcw_1 = 0x000a5a00;
  1216. if (ddr_freq <= 800)
  1217. popts->rcw_2 = 0x00000000;
  1218. else if (ddr_freq <= 1066)
  1219. popts->rcw_2 = 0x00100000;
  1220. else if (ddr_freq <= 1333)
  1221. popts->rcw_2 = 0x00200000;
  1222. else
  1223. popts->rcw_2 = 0x00300000;
  1224. }
  1225. fsl_ddr_board_options(popts, pdimm, ctrl_num);
  1226. return 0;
  1227. }
  1228. void check_interleaving_options(fsl_ddr_info_t *pinfo)
  1229. {
  1230. int i, j, k, check_n_ranks, intlv_invalid = 0;
  1231. unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
  1232. unsigned long long check_rank_density;
  1233. struct dimm_params_s *dimm;
  1234. int first_ctrl = pinfo->first_ctrl;
  1235. int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
  1236. /*
  1237. * Check if all controllers are configured for memory
  1238. * controller interleaving. Identical dimms are recommended. At least
  1239. * the size, row and col address should be checked.
  1240. */
  1241. j = 0;
  1242. check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
  1243. check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
  1244. check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
  1245. check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
  1246. check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
  1247. for (i = first_ctrl; i <= last_ctrl; i++) {
  1248. dimm = &pinfo->dimm_params[i][0];
  1249. if (!pinfo->memctl_opts[i].memctl_interleaving) {
  1250. continue;
  1251. } else if (((check_rank_density != dimm->rank_density) ||
  1252. (check_n_ranks != dimm->n_ranks) ||
  1253. (check_n_row_addr != dimm->n_row_addr) ||
  1254. (check_n_col_addr != dimm->n_col_addr) ||
  1255. (check_intlv !=
  1256. pinfo->memctl_opts[i].memctl_interleaving_mode))){
  1257. intlv_invalid = 1;
  1258. break;
  1259. } else {
  1260. j++;
  1261. }
  1262. }
  1263. if (intlv_invalid) {
  1264. for (i = first_ctrl; i <= last_ctrl; i++)
  1265. pinfo->memctl_opts[i].memctl_interleaving = 0;
  1266. printf("Not all DIMMs are identical. "
  1267. "Memory controller interleaving disabled.\n");
  1268. } else {
  1269. switch (check_intlv) {
  1270. case FSL_DDR_256B_INTERLEAVING:
  1271. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  1272. case FSL_DDR_PAGE_INTERLEAVING:
  1273. case FSL_DDR_BANK_INTERLEAVING:
  1274. case FSL_DDR_SUPERBANK_INTERLEAVING:
  1275. #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
  1276. k = 2;
  1277. #else
  1278. k = CONFIG_NUM_DDR_CONTROLLERS;
  1279. #endif
  1280. break;
  1281. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  1282. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  1283. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  1284. case FSL_DDR_4WAY_1KB_INTERLEAVING:
  1285. case FSL_DDR_4WAY_4KB_INTERLEAVING:
  1286. case FSL_DDR_4WAY_8KB_INTERLEAVING:
  1287. default:
  1288. k = CONFIG_NUM_DDR_CONTROLLERS;
  1289. break;
  1290. }
  1291. debug("%d of %d controllers are interleaving.\n", j, k);
  1292. if (j && (j != k)) {
  1293. for (i = first_ctrl; i <= last_ctrl; i++)
  1294. pinfo->memctl_opts[i].memctl_interleaving = 0;
  1295. if ((last_ctrl - first_ctrl) > 1)
  1296. puts("Not all controllers have compatible interleaving mode. All disabled.\n");
  1297. }
  1298. }
  1299. debug("Checking interleaving options completed\n");
  1300. }
  1301. int fsl_use_spd(void)
  1302. {
  1303. int use_spd = 0;
  1304. #ifdef CONFIG_DDR_SPD
  1305. char buffer[HWCONFIG_BUFFER_SIZE];
  1306. char *buf = NULL;
  1307. /*
  1308. * Extract hwconfig from environment since we have not properly setup
  1309. * the environment but need it for ddr config params
  1310. */
  1311. if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
  1312. buf = buffer;
  1313. /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
  1314. if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
  1315. if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
  1316. use_spd = 1;
  1317. else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
  1318. "fixed", buf))
  1319. use_spd = 0;
  1320. else
  1321. use_spd = 1;
  1322. } else
  1323. use_spd = 1;
  1324. #endif
  1325. return use_spd;
  1326. }