mpc837xerdb.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Kevin Lam <kevin.lam@freescale.com>
  5. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <asm/bitops.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/fsl_mpc83xx_serdes.h>
  16. #include <fdt_support.h>
  17. #include <spd_sdram.h>
  18. #include <vsc7385.h>
  19. #include <fsl_esdhc.h>
  20. #include <linux/delay.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #if defined(CONFIG_SYS_DRAM_TEST)
  23. int
  24. testdram(void)
  25. {
  26. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  27. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  28. uint *p;
  29. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  30. CONFIG_SYS_MEMTEST_START,
  31. CONFIG_SYS_MEMTEST_END);
  32. printf("DRAM test phase 1:\n");
  33. for (p = pstart; p < pend; p++)
  34. *p = 0xaaaaaaaa;
  35. for (p = pstart; p < pend; p++) {
  36. if (*p != 0xaaaaaaaa) {
  37. printf("DRAM test fails at: %08x\n", (uint) p);
  38. return 1;
  39. }
  40. }
  41. printf("DRAM test phase 2:\n");
  42. for (p = pstart; p < pend; p++)
  43. *p = 0x55555555;
  44. for (p = pstart; p < pend; p++) {
  45. if (*p != 0x55555555) {
  46. printf("DRAM test fails at: %08x\n", (uint) p);
  47. return 1;
  48. }
  49. }
  50. printf("DRAM test passed.\n");
  51. return 0;
  52. }
  53. #endif
  54. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  55. void ddr_enable_ecc(unsigned int dram_size);
  56. #endif
  57. int fixed_sdram(void);
  58. int dram_init(void)
  59. {
  60. immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  61. u32 msize = 0;
  62. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  63. return -ENXIO;
  64. #if defined(CONFIG_SPD_EEPROM)
  65. msize = spd_sdram();
  66. #else
  67. msize = fixed_sdram();
  68. #endif
  69. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  70. /* Initialize DDR ECC byte */
  71. ddr_enable_ecc(msize * 1024 * 1024);
  72. #endif
  73. /* return total bus DDR size(bytes) */
  74. gd->ram_size = msize * 1024 * 1024;
  75. return 0;
  76. }
  77. #if !defined(CONFIG_SPD_EEPROM)
  78. /*************************************************************************
  79. * fixed sdram init -- doesn't use serial presence detect.
  80. ************************************************************************/
  81. int fixed_sdram(void)
  82. {
  83. immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  84. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  85. u32 msize_log2 = __ilog2(msize);
  86. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  87. im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  88. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  89. udelay(50000);
  90. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  91. udelay(1000);
  92. im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  93. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  94. udelay(1000);
  95. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  96. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  97. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  98. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  99. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  100. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  101. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  102. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  103. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  104. sync();
  105. udelay(1000);
  106. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  107. udelay(2000);
  108. return CONFIG_SYS_DDR_SIZE;
  109. }
  110. #endif /*!CONFIG_SYS_SPD_EEPROM */
  111. int checkboard(void)
  112. {
  113. puts("Board: Freescale MPC837xERDB\n");
  114. return 0;
  115. }
  116. int board_early_init_f(void)
  117. {
  118. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  119. #ifdef CONFIG_FSL_SERDES
  120. u32 spridr = in_be32(&immr->sysconf.spridr);
  121. /* we check only part num, and don't look for CPU revisions */
  122. switch (PARTID_NO_E(spridr)) {
  123. case SPR_8377:
  124. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
  125. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  126. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
  127. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  128. break;
  129. case SPR_8378:
  130. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
  131. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  132. break;
  133. case SPR_8379:
  134. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
  135. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  136. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
  137. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  138. break;
  139. default:
  140. printf("serdes not configured: unknown CPU part number: "
  141. "%04x\n", spridr >> 16);
  142. break;
  143. }
  144. #endif /* CONFIG_FSL_SERDES */
  145. #ifdef CONFIG_FSL_ESDHC
  146. clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
  147. clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
  148. #endif
  149. return 0;
  150. }
  151. #ifdef CONFIG_FSL_ESDHC
  152. #if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB))
  153. int board_mmc_init(struct bd_info *bd)
  154. {
  155. struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
  156. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  157. int esdhc_hwconfig_enabled = 0;
  158. if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
  159. esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
  160. if (esdhc_hwconfig_enabled == 0)
  161. return 0;
  162. clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
  163. clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
  164. return fsl_esdhc_mmc_init(bd);
  165. }
  166. #endif
  167. #endif
  168. /*
  169. * Miscellaneous late-boot configurations
  170. *
  171. * If a VSC7385 microcode image is present, then upload it.
  172. */
  173. int misc_init_r(void)
  174. {
  175. int rc = 0;
  176. #ifdef CONFIG_VSC7385_IMAGE
  177. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  178. CONFIG_VSC7385_IMAGE_SIZE)) {
  179. puts("Failure uploading VSC7385 microcode.\n");
  180. rc = 1;
  181. }
  182. #endif
  183. return rc;
  184. }
  185. int board_late_init(void)
  186. {
  187. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  188. #ifdef CONFIG_USB_HOST
  189. clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
  190. #endif
  191. return 0;
  192. }
  193. #if defined(CONFIG_OF_BOARD_SETUP)
  194. int ft_board_setup(void *blob, struct bd_info *bd)
  195. {
  196. #ifdef CONFIG_PCI
  197. ft_pci_setup(blob, bd);
  198. #endif
  199. ft_cpu_setup(blob, bd);
  200. fsl_fdt_fixup_dr_usb(blob, bd);
  201. fdt_fixup_esdhc(blob, bd);
  202. return 0;
  203. }
  204. #endif /* CONFIG_OF_BOARD_SETUP */