pcie_dw_rockchip.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Rockchip DesignWare based PCIe host controller driver
  4. *
  5. * Copyright (c) 2021 Rockchip, Inc.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <generic-phy.h>
  11. #include <pci.h>
  12. #include <power-domain.h>
  13. #include <reset.h>
  14. #include <syscon.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm-generic/gpio.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/iopoll.h>
  21. #include <linux/delay.h>
  22. #include <power/regulator.h>
  23. #include "pcie_dw_common.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /**
  26. * struct rk_pcie - RK DW PCIe controller state
  27. *
  28. * @vpcie3v3: The 3.3v power supply for slot
  29. * @apb_base: The base address of vendor regs
  30. * @rst_gpio: The #PERST signal for slot
  31. */
  32. struct rk_pcie {
  33. /* Must be first member of the struct */
  34. struct pcie_dw dw;
  35. struct udevice *vpcie3v3;
  36. void *apb_base;
  37. struct phy phy;
  38. struct clk_bulk clks;
  39. struct reset_ctl_bulk rsts;
  40. struct gpio_desc rst_gpio;
  41. };
  42. /* Parameters for the waiting for iATU enabled routine */
  43. #define PCIE_CLIENT_GENERAL_DEBUG 0x104
  44. #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
  45. #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
  46. #define PCIE_CLIENT_LTSSM_STATUS 0x300
  47. #define SMLH_LINKUP BIT(16)
  48. #define RDLH_LINKUP BIT(17)
  49. #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
  50. #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
  51. #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
  52. #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
  53. #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
  54. #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
  55. #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
  56. #define PCIE_CLIENT_DBF_EN 0xffff0003
  57. /* Parameters for the waiting for #perst signal */
  58. #define MACRO_US 1000
  59. static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
  60. {
  61. if ((uintptr_t)addr & (size - 1)) {
  62. *val = 0;
  63. return -EOPNOTSUPP;
  64. }
  65. if (size == 4) {
  66. *val = readl(addr);
  67. } else if (size == 2) {
  68. *val = readw(addr);
  69. } else if (size == 1) {
  70. *val = readb(addr);
  71. } else {
  72. *val = 0;
  73. return -ENODEV;
  74. }
  75. return 0;
  76. }
  77. static int rk_pcie_write(void __iomem *addr, int size, u32 val)
  78. {
  79. if ((uintptr_t)addr & (size - 1))
  80. return -EOPNOTSUPP;
  81. if (size == 4)
  82. writel(val, addr);
  83. else if (size == 2)
  84. writew(val, addr);
  85. else if (size == 1)
  86. writeb(val, addr);
  87. else
  88. return -ENODEV;
  89. return 0;
  90. }
  91. static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base,
  92. u32 reg, size_t size)
  93. {
  94. int ret;
  95. u32 val;
  96. ret = rk_pcie_read(base + reg, size, &val);
  97. if (ret)
  98. dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
  99. return val;
  100. }
  101. static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base,
  102. u32 reg, size_t size, u32 val)
  103. {
  104. int ret;
  105. ret = rk_pcie_write(base + reg, size, val);
  106. if (ret)
  107. dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
  108. }
  109. /**
  110. * rk_pcie_readl_apb() - Read vendor regs
  111. *
  112. * @rk_pcie: Pointer to the PCI controller state
  113. * @reg: Offset of regs
  114. */
  115. static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
  116. {
  117. return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
  118. }
  119. /**
  120. * rk_pcie_writel_apb() - Write vendor regs
  121. *
  122. * @rk_pcie: Pointer to the PCI controller state
  123. * @reg: Offset of regs
  124. * @val: Value to be writen
  125. */
  126. static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
  127. u32 val)
  128. {
  129. __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
  130. }
  131. /**
  132. * rk_pcie_configure() - Configure link capabilities and speed
  133. *
  134. * @rk_pcie: Pointer to the PCI controller state
  135. * @cap_speed: The capabilities and speed to configure
  136. *
  137. * Configure the link capabilities and speed in the PCIe root complex.
  138. */
  139. static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
  140. {
  141. dw_pcie_dbi_write_enable(&pci->dw, true);
  142. clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
  143. TARGET_LINK_SPEED_MASK, cap_speed);
  144. clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
  145. TARGET_LINK_SPEED_MASK, cap_speed);
  146. dw_pcie_dbi_write_enable(&pci->dw, false);
  147. }
  148. static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
  149. {
  150. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0,
  151. PCIE_CLIENT_DBG_TRANSITION_DATA);
  152. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1,
  153. PCIE_CLIENT_DBG_TRANSITION_DATA);
  154. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0,
  155. PCIE_CLIENT_DBG_TRANSITION_DATA);
  156. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1,
  157. PCIE_CLIENT_DBG_TRANSITION_DATA);
  158. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
  159. PCIE_CLIENT_DBF_EN);
  160. }
  161. static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
  162. {
  163. u32 loop;
  164. debug("ltssm = 0x%x\n",
  165. rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
  166. for (loop = 0; loop < 64; loop++)
  167. debug("fifo_status = 0x%x\n",
  168. rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
  169. }
  170. static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
  171. {
  172. rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
  173. }
  174. static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
  175. {
  176. rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
  177. }
  178. static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
  179. {
  180. rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
  181. }
  182. static int is_link_up(struct rk_pcie *priv)
  183. {
  184. u32 val;
  185. val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
  186. if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
  187. (val & GENMASK(5, 0)) == 0x11)
  188. return 1;
  189. return 0;
  190. }
  191. /**
  192. * rk_pcie_link_up() - Wait for the link to come up
  193. *
  194. * @rk_pcie: Pointer to the PCI controller state
  195. * @cap_speed: Desired link speed
  196. *
  197. * Return: 1 (true) for active line and negetive (false) for no link (timeout)
  198. */
  199. static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
  200. {
  201. int retries;
  202. if (is_link_up(priv)) {
  203. printf("PCI Link already up before configuration!\n");
  204. return 1;
  205. }
  206. /* DW pre link configurations */
  207. rk_pcie_configure(priv, cap_speed);
  208. /* Rest the device */
  209. if (dm_gpio_is_valid(&priv->rst_gpio)) {
  210. dm_gpio_set_value(&priv->rst_gpio, 0);
  211. /*
  212. * Minimal is 100ms from spec but we see
  213. * some wired devices need much more, such as 600ms.
  214. * Add a enough delay to cover all cases.
  215. */
  216. udelay(MACRO_US * 1000);
  217. dm_gpio_set_value(&priv->rst_gpio, 1);
  218. }
  219. rk_pcie_disable_ltssm(priv);
  220. rk_pcie_link_status_clear(priv);
  221. rk_pcie_enable_debug(priv);
  222. /* Enable LTSSM */
  223. rk_pcie_enable_ltssm(priv);
  224. for (retries = 0; retries < 5; retries++) {
  225. if (is_link_up(priv)) {
  226. dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
  227. rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
  228. rk_pcie_debug_dump(priv);
  229. return 0;
  230. }
  231. dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
  232. rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
  233. rk_pcie_debug_dump(priv);
  234. udelay(MACRO_US * 1000);
  235. }
  236. dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
  237. /* Link maybe in Gen switch recovery but we need to wait more 1s */
  238. udelay(MACRO_US * 1000);
  239. return -EIO;
  240. }
  241. static int rockchip_pcie_init_port(struct udevice *dev)
  242. {
  243. int ret;
  244. u32 val;
  245. struct rk_pcie *priv = dev_get_priv(dev);
  246. /* Set power and maybe external ref clk input */
  247. if (priv->vpcie3v3) {
  248. ret = regulator_set_value(priv->vpcie3v3, 3300000);
  249. if (ret) {
  250. dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n",
  251. ret);
  252. return ret;
  253. }
  254. }
  255. udelay(MACRO_US * 1000);
  256. ret = generic_phy_init(&priv->phy);
  257. if (ret) {
  258. dev_err(dev, "failed to init phy (ret=%d)\n", ret);
  259. return ret;
  260. }
  261. ret = generic_phy_power_on(&priv->phy);
  262. if (ret) {
  263. dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
  264. goto err_exit_phy;
  265. }
  266. ret = reset_deassert_bulk(&priv->rsts);
  267. if (ret) {
  268. dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
  269. goto err_power_off_phy;
  270. }
  271. ret = clk_enable_bulk(&priv->clks);
  272. if (ret) {
  273. dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
  274. goto err_deassert_bulk;
  275. }
  276. /* LTSSM EN ctrl mode */
  277. val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
  278. val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
  279. rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
  280. /* Set RC mode */
  281. rk_pcie_writel_apb(priv, 0x0, 0xf00040);
  282. pcie_dw_setup_host(&priv->dw);
  283. ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
  284. if (ret < 0)
  285. goto err_link_up;
  286. return 0;
  287. err_link_up:
  288. clk_disable_bulk(&priv->clks);
  289. err_deassert_bulk:
  290. reset_assert_bulk(&priv->rsts);
  291. err_power_off_phy:
  292. generic_phy_power_off(&priv->phy);
  293. err_exit_phy:
  294. generic_phy_exit(&priv->phy);
  295. return ret;
  296. }
  297. static int rockchip_pcie_parse_dt(struct udevice *dev)
  298. {
  299. struct rk_pcie *priv = dev_get_priv(dev);
  300. int ret;
  301. priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
  302. if (!priv->dw.dbi_base)
  303. return -ENODEV;
  304. dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
  305. priv->apb_base = (void *)dev_read_addr_index(dev, 1);
  306. if (!priv->apb_base)
  307. return -ENODEV;
  308. dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
  309. ret = gpio_request_by_name(dev, "reset-gpios", 0,
  310. &priv->rst_gpio, GPIOD_IS_OUT);
  311. if (ret) {
  312. dev_err(dev, "failed to find reset-gpios property\n");
  313. return ret;
  314. }
  315. ret = reset_get_bulk(dev, &priv->rsts);
  316. if (ret) {
  317. dev_err(dev, "Can't get reset: %d\n", ret);
  318. return ret;
  319. }
  320. ret = clk_get_bulk(dev, &priv->clks);
  321. if (ret) {
  322. dev_err(dev, "Can't get clock: %d\n", ret);
  323. return ret;
  324. }
  325. ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
  326. &priv->vpcie3v3);
  327. if (ret && ret != -ENOENT) {
  328. dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
  329. return ret;
  330. }
  331. ret = generic_phy_get_by_index(dev, 0, &priv->phy);
  332. if (ret) {
  333. dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
  334. return ret;
  335. }
  336. return 0;
  337. }
  338. /**
  339. * rockchip_pcie_probe() - Probe the PCIe bus for active link
  340. *
  341. * @dev: A pointer to the device being operated on
  342. *
  343. * Probe for an active link on the PCIe bus and configure the controller
  344. * to enable this port.
  345. *
  346. * Return: 0 on success, else -ENODEV
  347. */
  348. static int rockchip_pcie_probe(struct udevice *dev)
  349. {
  350. struct rk_pcie *priv = dev_get_priv(dev);
  351. struct udevice *ctlr = pci_get_controller(dev);
  352. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  353. int ret = 0;
  354. priv->dw.first_busno = dev_seq(dev);
  355. priv->dw.dev = dev;
  356. ret = rockchip_pcie_parse_dt(dev);
  357. if (ret)
  358. return ret;
  359. ret = rockchip_pcie_init_port(dev);
  360. if (ret)
  361. return ret;
  362. dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
  363. dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
  364. pcie_dw_get_link_width(&priv->dw),
  365. hose->first_busno);
  366. return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
  367. PCIE_ATU_REGION_INDEX0,
  368. PCIE_ATU_TYPE_MEM,
  369. priv->dw.mem.phys_start,
  370. priv->dw.mem.bus_start,
  371. priv->dw.mem.size);
  372. }
  373. static const struct dm_pci_ops rockchip_pcie_ops = {
  374. .read_config = pcie_dw_read_config,
  375. .write_config = pcie_dw_write_config,
  376. };
  377. static const struct udevice_id rockchip_pcie_ids[] = {
  378. { .compatible = "rockchip,rk3568-pcie" },
  379. { }
  380. };
  381. U_BOOT_DRIVER(rockchip_dw_pcie) = {
  382. .name = "pcie_dw_rockchip",
  383. .id = UCLASS_PCI,
  384. .of_match = rockchip_pcie_ids,
  385. .ops = &rockchip_pcie_ops,
  386. .probe = rockchip_pcie_probe,
  387. .priv_auto = sizeof(struct rk_pcie),
  388. };