pcie_dw_common.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2021 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. *
  6. * Copyright (c) 2021 Rockchip, Inc.
  7. *
  8. * Copyright (C) 2018 Texas Instruments, Inc
  9. */
  10. #ifndef PCIE_DW_COMMON_H
  11. #define PCIE_DW_COMMON_H
  12. #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
  13. /* PCI DBICS registers */
  14. #define PCIE_LINK_STATUS_REG 0x80
  15. #define PCIE_LINK_STATUS_SPEED_OFF 16
  16. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  17. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  18. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  19. /*
  20. * iATU Unroll-specific register definitions
  21. * From 4.80 core version the address translation will be made by unroll.
  22. * The registers are offset from atu_base
  23. */
  24. #define PCIE_ATU_UNR_REGION_CTRL1 0x00
  25. #define PCIE_ATU_UNR_REGION_CTRL2 0x04
  26. #define PCIE_ATU_UNR_LOWER_BASE 0x08
  27. #define PCIE_ATU_UNR_UPPER_BASE 0x0c
  28. #define PCIE_ATU_UNR_LIMIT 0x10
  29. #define PCIE_ATU_UNR_LOWER_TARGET 0x14
  30. #define PCIE_ATU_UNR_UPPER_TARGET 0x18
  31. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  32. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  33. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  34. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  35. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  36. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  37. #define PCIE_ATU_ENABLE (0x1 << 31)
  38. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  39. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  40. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  41. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  42. /* Register address builder */
  43. #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
  44. /* Parameters for the waiting for iATU enabled routine */
  45. #define LINK_WAIT_MAX_IATU_RETRIES 5
  46. #define LINK_WAIT_IATU_US 10000
  47. /* PCI DBICS registers */
  48. #define PCIE_LINK_STATUS_REG 0x80
  49. #define PCIE_LINK_STATUS_SPEED_OFF 16
  50. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  51. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  52. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  53. #define PCIE_LINK_CAPABILITY 0x7c
  54. #define PCIE_LINK_CTL_2 0xa0
  55. #define TARGET_LINK_SPEED_MASK 0xf
  56. #define LINK_SPEED_GEN_1 0x1
  57. #define LINK_SPEED_GEN_2 0x2
  58. #define LINK_SPEED_GEN_3 0x3
  59. /* Synopsys-specific PCIe configuration registers */
  60. #define PCIE_PORT_LINK_CONTROL 0x710
  61. #define PORT_LINK_DLL_LINK_EN BIT(5)
  62. #define PORT_LINK_FAST_LINK_MODE BIT(7)
  63. #define PORT_LINK_MODE_MASK GENMASK(21, 16)
  64. #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
  65. #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
  66. #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
  67. #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
  68. #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
  69. #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
  70. #define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
  71. #define PORT_LOGIC_SPEED_CHANGE BIT(17)
  72. #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
  73. #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
  74. #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
  75. #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
  76. #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
  77. #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
  78. #define PCIE_MISC_CONTROL_1_OFF 0x8bc
  79. #define PCIE_DBI_RO_WR_EN BIT(0)
  80. /* Parameters for the waiting for iATU enabled routine */
  81. #define LINK_WAIT_MAX_IATU_RETRIES 5
  82. #define LINK_WAIT_IATU 10000
  83. /**
  84. * struct pcie_dw - DW PCIe controller state
  85. *
  86. * @dbi_base: The base address of dbi register space
  87. * @cfg_base: The base address of configuration space
  88. * @atu_base: The base address of ATU space
  89. * @cfg_size: The size of the configuration space which is needed
  90. * as it gets written into the PCIE_ATU_LIMIT register
  91. * @first_busno: This driver supports multiple PCIe controllers.
  92. * first_busno stores the bus number of the PCIe root-port
  93. * number which may vary depending on the PCIe setup
  94. * (PEX switches etc).
  95. * @io: The IO space for EP's BAR
  96. * @mem: The memory space for EP's BAR
  97. * @prefetch: The prefetch space for EP's BAR
  98. */
  99. struct pcie_dw {
  100. struct udevice *dev;
  101. void __iomem *dbi_base;
  102. void __iomem *cfg_base;
  103. void __iomem *atu_base;
  104. fdt_size_t cfg_size;
  105. int first_busno;
  106. /* IO, MEM & PREFETCH PCI regions */
  107. struct pci_region io;
  108. struct pci_region mem;
  109. struct pci_region prefetch;
  110. };
  111. int pcie_dw_get_link_speed(struct pcie_dw *pci);
  112. int pcie_dw_get_link_width(struct pcie_dw *pci);
  113. int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, int type, u64 cpu_addr,
  114. u64 pci_addr, u32 size);
  115. int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep,
  116. enum pci_size_t size);
  117. int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value,
  118. enum pci_size_t size);
  119. static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en)
  120. {
  121. u32 val;
  122. val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  123. if (en)
  124. val |= PCIE_DBI_RO_WR_EN;
  125. else
  126. val &= ~PCIE_DBI_RO_WR_EN;
  127. writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  128. }
  129. void pcie_dw_setup_host(struct pcie_dw *pci);
  130. #endif