pci_octeontx.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <pci.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <linux/ioport.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * This driver supports multiple types of operations / host bridges / busses:
  19. *
  20. * OTX_ECAM: Octeon TX & TX2 ECAM (Enhanced Configuration Access Mechanism)
  21. * Used to access the internal on-chip devices which are connected
  22. * to internal buses
  23. * OTX_PEM: Octeon TX PEM (PCI Express MAC)
  24. * Used to access the external (off-chip) PCI devices
  25. * OTX2_PEM: Octeon TX2 PEM (PCI Express MAC)
  26. * Used to access the external (off-chip) PCI devices
  27. */
  28. enum {
  29. OTX_ECAM,
  30. OTX_PEM,
  31. OTX2_PEM,
  32. };
  33. /**
  34. * struct octeontx_pci - Driver private data
  35. * @type: Device type matched via compatible (e.g. OTX_ECAM etc)
  36. * @cfg: Config resource
  37. * @bus: Bus resource
  38. */
  39. struct octeontx_pci {
  40. unsigned int type;
  41. struct resource cfg;
  42. struct resource bus;
  43. };
  44. static uintptr_t octeontx_cfg_addr(struct octeontx_pci *pcie,
  45. int bus_offs, int shift_offs,
  46. pci_dev_t bdf, uint offset)
  47. {
  48. u32 bus, dev, func;
  49. uintptr_t address;
  50. bus = PCI_BUS(bdf) + bus_offs;
  51. dev = PCI_DEV(bdf);
  52. func = PCI_FUNC(bdf);
  53. address = (bus << (20 + shift_offs)) |
  54. (dev << (15 + shift_offs)) |
  55. (func << (12 + shift_offs)) | offset;
  56. address += pcie->cfg.start;
  57. return address;
  58. }
  59. static ulong readl_size(uintptr_t addr, enum pci_size_t size)
  60. {
  61. ulong val;
  62. switch (size) {
  63. case PCI_SIZE_8:
  64. val = readb(addr);
  65. break;
  66. case PCI_SIZE_16:
  67. val = readw(addr);
  68. break;
  69. case PCI_SIZE_32:
  70. val = readl(addr);
  71. break;
  72. default:
  73. printf("Invalid size\n");
  74. return -EINVAL;
  75. };
  76. return val;
  77. }
  78. static void writel_size(uintptr_t addr, enum pci_size_t size, ulong valuep)
  79. {
  80. switch (size) {
  81. case PCI_SIZE_8:
  82. writeb(valuep, addr);
  83. break;
  84. case PCI_SIZE_16:
  85. writew(valuep, addr);
  86. break;
  87. case PCI_SIZE_32:
  88. writel(valuep, addr);
  89. break;
  90. default:
  91. printf("Invalid size\n");
  92. };
  93. }
  94. static bool octeontx_bdf_invalid(pci_dev_t bdf)
  95. {
  96. if (PCI_BUS(bdf) == 1 && PCI_DEV(bdf) > 0)
  97. return true;
  98. return false;
  99. }
  100. static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf,
  101. uint offset, ulong *valuep,
  102. enum pci_size_t size)
  103. {
  104. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  105. struct pci_controller *hose = dev_get_uclass_priv(bus);
  106. uintptr_t address;
  107. address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno,
  108. 0, bdf, offset);
  109. *valuep = readl_size(address, size);
  110. debug("%02x.%02x.%02x: u%d %x -> %lx\n",
  111. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
  112. return 0;
  113. }
  114. static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
  115. uint offset, ulong value,
  116. enum pci_size_t size)
  117. {
  118. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  119. struct pci_controller *hose = dev_get_uclass_priv(bus);
  120. uintptr_t address;
  121. address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno,
  122. 0, bdf, offset);
  123. writel_size(address, size, value);
  124. debug("%02x.%02x.%02x: u%d %x <- %lx\n",
  125. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, value);
  126. return 0;
  127. }
  128. static int octeontx_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
  129. uint offset, ulong *valuep,
  130. enum pci_size_t size)
  131. {
  132. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  133. struct pci_controller *hose = dev_get_uclass_priv(bus);
  134. uintptr_t address;
  135. u8 hdrtype;
  136. u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
  137. u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
  138. address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4,
  139. bdf, 0);
  140. *valuep = pci_conv_32_to_size(~0UL, offset, size);
  141. if (octeontx_bdf_invalid(bdf))
  142. return -EPERM;
  143. *valuep = readl_size(address + offset, size);
  144. hdrtype = readb(address + PCI_HEADER_TYPE);
  145. if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
  146. offset >= PCI_PRIMARY_BUS &&
  147. offset <= PCI_SUBORDINATE_BUS &&
  148. *valuep != pci_conv_32_to_size(~0UL, offset, size))
  149. *valuep -= pci_conv_32_to_size(bus_offs, offset, size);
  150. return 0;
  151. }
  152. static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf,
  153. uint offset, ulong value,
  154. enum pci_size_t size)
  155. {
  156. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  157. struct pci_controller *hose = dev_get_uclass_priv(bus);
  158. uintptr_t address;
  159. u8 hdrtype;
  160. u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
  161. u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
  162. address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 4, bdf, 0);
  163. hdrtype = readb(address + PCI_HEADER_TYPE);
  164. if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
  165. offset >= PCI_PRIMARY_BUS &&
  166. offset <= PCI_SUBORDINATE_BUS &&
  167. value != pci_conv_32_to_size(~0UL, offset, size))
  168. value += pci_conv_32_to_size(bus_offs, offset, size);
  169. if (octeontx_bdf_invalid(bdf))
  170. return -EPERM;
  171. writel_size(address + offset, size, value);
  172. debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
  173. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
  174. address, value);
  175. return 0;
  176. }
  177. static int octeontx2_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
  178. uint offset, ulong *valuep,
  179. enum pci_size_t size)
  180. {
  181. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  182. struct pci_controller *hose = dev_get_uclass_priv(bus);
  183. uintptr_t address;
  184. address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0,
  185. bdf, 0);
  186. *valuep = pci_conv_32_to_size(~0UL, offset, size);
  187. if (octeontx_bdf_invalid(bdf))
  188. return -EPERM;
  189. *valuep = readl_size(address + offset, size);
  190. debug("%02x.%02x.%02x: u%d %x (%lx) -> %lx\n",
  191. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
  192. address, *valuep);
  193. return 0;
  194. }
  195. static int octeontx2_pem_write_config(struct udevice *bus, pci_dev_t bdf,
  196. uint offset, ulong value,
  197. enum pci_size_t size)
  198. {
  199. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  200. struct pci_controller *hose = dev_get_uclass_priv(bus);
  201. uintptr_t address;
  202. address = octeontx_cfg_addr(pcie, 1 - hose->first_busno, 0,
  203. bdf, 0);
  204. if (octeontx_bdf_invalid(bdf))
  205. return -EPERM;
  206. writel_size(address + offset, size, value);
  207. debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
  208. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
  209. address, value);
  210. return 0;
  211. }
  212. int pci_octeontx_read_config(const struct udevice *bus, pci_dev_t bdf,
  213. uint offset, ulong *valuep,
  214. enum pci_size_t size)
  215. {
  216. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  217. int ret = -EIO;
  218. switch (pcie->type) {
  219. case OTX_ECAM:
  220. ret = octeontx_ecam_read_config(bus, bdf, offset, valuep,
  221. size);
  222. break;
  223. case OTX_PEM:
  224. ret = octeontx_pem_read_config(bus, bdf, offset, valuep,
  225. size);
  226. break;
  227. case OTX2_PEM:
  228. ret = octeontx2_pem_read_config(bus, bdf, offset, valuep,
  229. size);
  230. break;
  231. }
  232. return ret;
  233. }
  234. int pci_octeontx_write_config(struct udevice *bus, pci_dev_t bdf,
  235. uint offset, ulong value,
  236. enum pci_size_t size)
  237. {
  238. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
  239. int ret = -EIO;
  240. switch (pcie->type) {
  241. case OTX_ECAM:
  242. ret = octeontx_ecam_write_config(bus, bdf, offset, value,
  243. size);
  244. break;
  245. case OTX_PEM:
  246. ret = octeontx_pem_write_config(bus, bdf, offset, value,
  247. size);
  248. break;
  249. case OTX2_PEM:
  250. ret = octeontx2_pem_write_config(bus, bdf, offset, value,
  251. size);
  252. break;
  253. }
  254. return ret;
  255. }
  256. static int pci_octeontx_of_to_plat(struct udevice *dev)
  257. {
  258. return 0;
  259. }
  260. static int pci_octeontx_probe(struct udevice *dev)
  261. {
  262. struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(dev);
  263. int err;
  264. pcie->type = dev_get_driver_data(dev);
  265. err = dev_read_resource(dev, 0, &pcie->cfg);
  266. if (err) {
  267. debug("Error reading resource: %s\n", fdt_strerror(err));
  268. return err;
  269. }
  270. err = dev_read_pci_bus_range(dev, &pcie->bus);
  271. if (err) {
  272. debug("Error reading resource: %s\n", fdt_strerror(err));
  273. return err;
  274. }
  275. return 0;
  276. }
  277. static const struct dm_pci_ops pci_octeontx_ops = {
  278. .read_config = pci_octeontx_read_config,
  279. .write_config = pci_octeontx_write_config,
  280. };
  281. static const struct udevice_id pci_octeontx_ids[] = {
  282. { .compatible = "cavium,pci-host-thunder-ecam", .data = OTX_ECAM },
  283. { .compatible = "cavium,pci-host-octeontx-ecam", .data = OTX_ECAM },
  284. { .compatible = "pci-host-ecam-generic", .data = OTX_ECAM },
  285. { .compatible = "cavium,pci-host-thunder-pem", .data = OTX_PEM },
  286. { .compatible = "marvell,pci-host-octeontx2-pem", .data = OTX2_PEM },
  287. { }
  288. };
  289. U_BOOT_DRIVER(pci_octeontx) = {
  290. .name = "pci_octeontx",
  291. .id = UCLASS_PCI,
  292. .of_match = pci_octeontx_ids,
  293. .ops = &pci_octeontx_ops,
  294. .of_to_plat = pci_octeontx_of_to_plat,
  295. .probe = pci_octeontx_probe,
  296. .priv_auto = sizeof(struct octeontx_pci),
  297. .flags = DM_FLAG_PRE_RELOC,
  298. };