pci_msc01.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Imagination Technologies
  4. * Author: Paul Burton <paul.burton@mips.com>
  5. */
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <msc01.h>
  9. #include <pci.h>
  10. #include <pci_msc01.h>
  11. #include <asm/io.h>
  12. #define PCI_ACCESS_READ 0
  13. #define PCI_ACCESS_WRITE 1
  14. struct msc01_pci_controller {
  15. struct pci_controller hose;
  16. void *base;
  17. };
  18. static inline struct msc01_pci_controller *
  19. hose_to_msc01(struct pci_controller *hose)
  20. {
  21. return container_of(hose, struct msc01_pci_controller, hose);
  22. }
  23. static int msc01_config_access(struct msc01_pci_controller *msc01,
  24. unsigned char access_type, pci_dev_t bdf,
  25. int where, u32 *data)
  26. {
  27. const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
  28. void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
  29. void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
  30. unsigned int bus = PCI_BUS(bdf);
  31. unsigned int dev = PCI_DEV(bdf);
  32. unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  33. /* clear abort status */
  34. __raw_writel(aborts, intstat);
  35. /* setup address */
  36. __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
  37. (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
  38. (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
  39. ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
  40. msc01->base + MSC01_PCI_CFGADDR_OFS);
  41. /* perform access */
  42. if (access_type == PCI_ACCESS_WRITE)
  43. __raw_writel(*data, cfgdata);
  44. else
  45. *data = __raw_readl(cfgdata);
  46. /* check for aborts */
  47. if (__raw_readl(intstat) & aborts) {
  48. /* clear abort status */
  49. __raw_writel(aborts, intstat);
  50. return -1;
  51. }
  52. return 0;
  53. }
  54. static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
  55. uint where, ulong *val, enum pci_size_t size)
  56. {
  57. struct msc01_pci_controller *msc01 = dev_get_priv(dev);
  58. u32 data = 0;
  59. if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
  60. *val = pci_get_ff(size);
  61. return 0;
  62. }
  63. *val = pci_conv_32_to_size(data, where, size);
  64. return 0;
  65. }
  66. static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
  67. uint where, ulong val, enum pci_size_t size)
  68. {
  69. struct msc01_pci_controller *msc01 = dev_get_priv(dev);
  70. u32 data = 0;
  71. if (size == PCI_SIZE_32) {
  72. data = val;
  73. } else {
  74. u32 old;
  75. if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
  76. return 0;
  77. data = pci_conv_size_to_32(old, val, where, size);
  78. }
  79. msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
  80. return 0;
  81. }
  82. static int msc01_pci_probe(struct udevice *dev)
  83. {
  84. struct msc01_pci_controller *msc01 = dev_get_priv(dev);
  85. msc01->base = dev_remap_addr(dev);
  86. if (!msc01->base)
  87. return -EINVAL;
  88. return 0;
  89. }
  90. static const struct dm_pci_ops msc01_pci_ops = {
  91. .read_config = msc01_pci_read_config,
  92. .write_config = msc01_pci_write_config,
  93. };
  94. static const struct udevice_id msc01_pci_ids[] = {
  95. { .compatible = "mips,pci-msc01" },
  96. { }
  97. };
  98. U_BOOT_DRIVER(msc01_pci) = {
  99. .name = "msc01_pci",
  100. .id = UCLASS_PCI,
  101. .of_match = msc01_pci_ids,
  102. .ops = &msc01_pci_ops,
  103. .probe = msc01_pci_probe,
  104. .priv_auto = sizeof(struct msc01_pci_controller),
  105. };