pci_mpc85xx.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2019
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/bitops.h>
  9. #include <asm/cpm_85xx.h>
  10. #include <pci.h>
  11. #include <dm.h>
  12. #include <asm/fsl_law.h>
  13. struct mpc85xx_pci_priv {
  14. void __iomem *cfg_addr;
  15. void __iomem *cfg_data;
  16. };
  17. static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
  18. uint offset, ulong *value,
  19. enum pci_size_t size)
  20. {
  21. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  22. u32 addr;
  23. addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  24. out_be32(priv->cfg_addr, addr);
  25. sync();
  26. *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
  27. return 0;
  28. }
  29. static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
  30. uint offset, ulong value,
  31. enum pci_size_t size)
  32. {
  33. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  34. u32 addr;
  35. addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  36. out_be32(priv->cfg_addr, addr);
  37. sync();
  38. out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
  39. return 0;
  40. }
  41. #ifdef CONFIG_FSL_LAW
  42. static int
  43. mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
  44. struct pci_region *pre)
  45. {
  46. /*
  47. * Unfortunately we have defines for this addresse,
  48. * as we have to setup the TLB, and at this stage
  49. * we have no access to DT ... may we check here
  50. * if the value in the define is the same ?
  51. */
  52. if (mem)
  53. set_next_law(mem->phys_start, law_size_bits(mem->size),
  54. LAW_TRGT_IF_PCI);
  55. if (io)
  56. set_next_law(io->phys_start, law_size_bits(io->size),
  57. LAW_TRGT_IF_PCI);
  58. if (pre)
  59. set_next_law(pre->phys_start, law_size_bits(pre->size),
  60. LAW_TRGT_IF_PCI);
  61. return 0;
  62. }
  63. #endif
  64. static int mpc85xx_pci_dm_probe(struct udevice *dev)
  65. {
  66. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  67. struct pci_region *io;
  68. struct pci_region *mem;
  69. struct pci_region *pre;
  70. int count;
  71. ccsr_pcix_t *pcix;
  72. count = pci_get_regions(dev, &io, &mem, &pre);
  73. if (count != 2) {
  74. printf("%s: wrong count of regions %d only 2 allowed\n",
  75. __func__, count);
  76. return -EINVAL;
  77. }
  78. #ifdef CONFIG_FSL_LAW
  79. mpc85xx_pci_dm_setup_laws(io, mem, pre);
  80. #endif
  81. pcix = priv->cfg_addr;
  82. /* BAR 1: memory */
  83. out_be32(&pcix->potar1, mem->bus_start >> 12);
  84. out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
  85. out_be32(&pcix->powbar1, mem->phys_start >> 12);
  86. out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
  87. out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
  88. POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
  89. /* BAR 1: IO */
  90. out_be32(&pcix->potar2, io->bus_start >> 12);
  91. out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
  92. out_be32(&pcix->powbar2, io->phys_start >> 12);
  93. out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
  94. out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
  95. POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
  96. out_be32(&pcix->pitar1, 0);
  97. out_be32(&pcix->piwbar1, 0);
  98. out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  99. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
  100. out_be32(&pcix->powar3, 0);
  101. out_be32(&pcix->powar4, 0);
  102. out_be32(&pcix->piwar2, 0);
  103. out_be32(&pcix->piwar3, 0);
  104. return 0;
  105. }
  106. static int mpc85xx_pci_dm_remove(struct udevice *dev)
  107. {
  108. return 0;
  109. }
  110. static int mpc85xx_pci_of_to_plat(struct udevice *dev)
  111. {
  112. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  113. fdt_addr_t addr;
  114. addr = devfdt_get_addr_index(dev, 0);
  115. if (addr == FDT_ADDR_T_NONE)
  116. return -EINVAL;
  117. priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE);
  118. priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4);
  119. return 0;
  120. }
  121. static const struct dm_pci_ops mpc85xx_pci_ops = {
  122. .read_config = mpc85xx_pci_dm_read_config,
  123. .write_config = mpc85xx_pci_dm_write_config,
  124. };
  125. static const struct udevice_id mpc85xx_pci_ids[] = {
  126. { .compatible = "fsl,mpc8540-pci" },
  127. { }
  128. };
  129. U_BOOT_DRIVER(mpc85xx_pci) = {
  130. .name = "mpc85xx_pci",
  131. .id = UCLASS_PCI,
  132. .of_match = mpc85xx_pci_ids,
  133. .ops = &mpc85xx_pci_ops,
  134. .probe = mpc85xx_pci_dm_probe,
  135. .remove = mpc85xx_pci_dm_remove,
  136. .of_to_plat = mpc85xx_pci_of_to_plat,
  137. .priv_auto = sizeof(struct mpc85xx_pci_priv),
  138. };