ls1043ardb.h 8.0 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __LS1043ARDB_H__
  7. #define __LS1043ARDB_H__
  8. #include "ls1043a_common.h"
  9. #define CONFIG_DISPLAY_CPUINFO
  10. #define CONFIG_DISPLAY_BOARDINFO
  11. #if defined(CONFIG_NAND_BOOT)
  12. #define CONFIG_SYS_TEXT_BASE 0x82000000
  13. #else
  14. #define CONFIG_SYS_TEXT_BASE 0x60100000
  15. #endif
  16. #define CONFIG_SYS_CLK_FREQ 100000000
  17. #define CONFIG_DDR_CLK_FREQ 100000000
  18. #define CONFIG_LAYERSCAPE_NS_ACCESS
  19. #define CONFIG_MISC_INIT_R
  20. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  21. /* Physical Memory Map */
  22. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  23. #define CONFIG_NR_DRAM_BANKS 1
  24. #define CONFIG_SYS_SPD_BUS_NUM 0
  25. #define CONFIG_FSL_DDR_BIST
  26. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  27. #define CONFIG_SYS_DDR_RAW_TIMING
  28. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  29. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  30. #ifdef CONFIG_RAMBOOT_PBL
  31. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  32. #endif
  33. #ifdef CONFIG_NAND_BOOT
  34. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  35. #endif
  36. /*
  37. * NOR Flash Definitions
  38. */
  39. #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
  40. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  41. #define CONFIG_SYS_NOR_CSPR \
  42. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  43. CSPR_PORT_SIZE_16 | \
  44. CSPR_MSEL_NOR | \
  45. CSPR_V)
  46. /* NOR Flash Timing Params */
  47. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  48. CSOR_NOR_TRHZ_80)
  49. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  50. FTIM0_NOR_TEADC(0x1) | \
  51. FTIM0_NOR_TAVDS(0x0) | \
  52. FTIM0_NOR_TEAHC(0xc))
  53. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
  54. FTIM1_NOR_TRAD_NOR(0xb) | \
  55. FTIM1_NOR_TSEQRAD_NOR(0x9))
  56. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
  57. FTIM2_NOR_TCH(0x4) | \
  58. FTIM2_NOR_TWPH(0x8) | \
  59. FTIM2_NOR_TWP(0x10))
  60. #define CONFIG_SYS_NOR_FTIM3 0
  61. #define CONFIG_SYS_IFC_CCR 0x01000000
  62. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  63. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  64. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  65. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  66. #define CONFIG_SYS_FLASH_EMPTY_INFO
  67. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  68. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  69. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  70. /*
  71. * NAND Flash Definitions
  72. */
  73. #define CONFIG_NAND_FSL_IFC
  74. #define CONFIG_SYS_NAND_BASE 0x7e800000
  75. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  76. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  77. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  78. | CSPR_PORT_SIZE_8 \
  79. | CSPR_MSEL_NAND \
  80. | CSPR_V)
  81. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  82. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  83. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  84. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  85. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  86. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  87. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  88. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  89. #define CONFIG_SYS_NAND_ONFI_DETECTION
  90. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  91. FTIM0_NAND_TWP(0x18) | \
  92. FTIM0_NAND_TWCHT(0x7) | \
  93. FTIM0_NAND_TWH(0xa))
  94. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  95. FTIM1_NAND_TWBE(0x39) | \
  96. FTIM1_NAND_TRR(0xe) | \
  97. FTIM1_NAND_TRP(0x18))
  98. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  99. FTIM2_NAND_TREH(0xa) | \
  100. FTIM2_NAND_TWHRE(0x1e))
  101. #define CONFIG_SYS_NAND_FTIM3 0x0
  102. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  103. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  104. #define CONFIG_MTD_NAND_VERIFY_WRITE
  105. #define CONFIG_CMD_NAND
  106. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  107. #ifdef CONFIG_NAND_BOOT
  108. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  109. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  110. #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
  111. #endif
  112. /*
  113. * CPLD
  114. */
  115. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  116. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  117. #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
  118. #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  119. CSPR_PORT_SIZE_8 | \
  120. CSPR_MSEL_GPCM | \
  121. CSPR_V)
  122. #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
  123. #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  124. CSOR_NOR_NOR_MODE_AVD_NOR | \
  125. CSOR_NOR_TRHZ_80)
  126. /* CPLD Timing parameters for IFC GPCM */
  127. #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  128. FTIM0_GPCM_TEADC(0xf) | \
  129. FTIM0_GPCM_TEAHC(0xf))
  130. #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  131. FTIM1_GPCM_TRAD(0x3f))
  132. #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  133. FTIM2_GPCM_TCH(0xf) | \
  134. FTIM2_GPCM_TWP(0xff))
  135. #define CONFIG_SYS_CPLD_FTIM3 0x0
  136. /* IFC Timing Params */
  137. #ifdef CONFIG_NAND_BOOT
  138. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  139. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  140. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  141. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  142. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  143. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  144. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  145. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  146. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  147. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  148. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  149. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  150. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  151. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  152. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  153. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  154. #else
  155. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  156. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  157. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  158. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  159. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  160. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  161. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  162. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  163. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  164. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  165. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  166. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  167. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  168. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  169. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  170. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  171. #endif
  172. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
  173. #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
  174. #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
  175. #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
  176. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
  177. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
  178. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
  179. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
  180. /* EEPROM */
  181. #define CONFIG_ID_EEPROM
  182. #define CONFIG_SYS_I2C_EEPROM_NXID
  183. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  184. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  185. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  186. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  187. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  188. /*
  189. * Environment
  190. */
  191. #define CONFIG_ENV_OVERWRITE
  192. #if defined(CONFIG_NAND_BOOT)
  193. #define CONFIG_ENV_IS_IN_NAND
  194. #define CONFIG_ENV_SIZE 0x2000
  195. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  196. #else
  197. #define CONFIG_ENV_IS_IN_FLASH
  198. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  199. #define CONFIG_ENV_SECT_SIZE 0x20000
  200. #define CONFIG_ENV_SIZE 0x20000
  201. #endif
  202. /* FMan */
  203. #ifdef CONFIG_SYS_DPAA_FMAN
  204. #define CONFIG_FMAN_ENET
  205. #define CONFIG_CMD_MII
  206. #define CONFIG_PHYLIB
  207. #define CONFIG_PHYLIB_10G
  208. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  209. #define CONFIG_PHY_VITESSE
  210. #define CONFIG_PHY_REALTEK
  211. #define CONFIG_PHY_AQUANTIA
  212. #define RGMII_PHY1_ADDR 0x1
  213. #define RGMII_PHY2_ADDR 0x2
  214. #define QSGMII_PORT1_PHY_ADDR 0x4
  215. #define QSGMII_PORT2_PHY_ADDR 0x5
  216. #define QSGMII_PORT3_PHY_ADDR 0x6
  217. #define QSGMII_PORT4_PHY_ADDR 0x7
  218. #define FM1_10GEC1_PHY_ADDR 0x1
  219. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  220. #endif
  221. #endif /* __LS1043ARDB_H__ */