ls1043.c 3.4 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <phy.h>
  8. #include <fm_eth.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
  12. #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
  13. #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
  14. #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
  15. #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
  16. #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
  17. #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
  18. #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
  19. #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
  20. u32 port_to_devdisr[] = {
  21. [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
  22. [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
  23. [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
  24. [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
  25. [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
  26. [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
  27. [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
  28. [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
  29. [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
  30. [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
  31. [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
  32. [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
  33. };
  34. static int is_device_disabled(enum fm_port port)
  35. {
  36. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  37. u32 devdisr2 = in_be32(&gur->devdisr2);
  38. return port_to_devdisr[port] & devdisr2;
  39. }
  40. void fman_disable_port(enum fm_port port)
  41. {
  42. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  43. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  44. }
  45. phy_interface_t fman_port_enet_if(enum fm_port port)
  46. {
  47. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  48. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  49. if (is_device_disabled(port)) {
  50. printf("%s:%d: port(%d) is disabled\n", __func__,
  51. __LINE__, port);
  52. return PHY_INTERFACE_MODE_NONE;
  53. }
  54. if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
  55. return PHY_INTERFACE_MODE_XGMII;
  56. if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
  57. return PHY_INTERFACE_MODE_NONE;
  58. if (port == FM1_DTSEC3)
  59. if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
  60. FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
  61. printf("%s:%d: port(FM1_DTSEC3) is OK\n",
  62. __func__, __LINE__);
  63. return PHY_INTERFACE_MODE_RGMII;
  64. }
  65. if (port == FM1_DTSEC4)
  66. if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
  67. FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
  68. printf("%s:%d: port(FM1_DTSEC4) is OK\n",
  69. __func__, __LINE__);
  70. return PHY_INTERFACE_MODE_RGMII;
  71. }
  72. /* handle SGMII */
  73. switch (port) {
  74. case FM1_DTSEC1:
  75. case FM1_DTSEC2:
  76. if ((port == FM1_DTSEC2) &&
  77. is_serdes_configured(SGMII_2500_FM1_DTSEC2))
  78. return PHY_INTERFACE_MODE_SGMII_2500;
  79. case FM1_DTSEC5:
  80. case FM1_DTSEC6:
  81. case FM1_DTSEC9:
  82. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  83. return PHY_INTERFACE_MODE_SGMII;
  84. else if ((port == FM1_DTSEC9) &&
  85. is_serdes_configured(SGMII_2500_FM1_DTSEC9))
  86. return PHY_INTERFACE_MODE_SGMII_2500;
  87. break;
  88. default:
  89. break;
  90. }
  91. /* handle QSGMII */
  92. switch (port) {
  93. case FM1_DTSEC1:
  94. case FM1_DTSEC2:
  95. case FM1_DTSEC5:
  96. case FM1_DTSEC6:
  97. /* only MAC 1,2,5,6 available for QSGMII */
  98. if (is_serdes_configured(QSGMII_FM1_A))
  99. return PHY_INTERFACE_MODE_QSGMII;
  100. break;
  101. default:
  102. break;
  103. }
  104. return PHY_INTERFACE_MODE_NONE;
  105. }