fsl_lsch2_speed.c 3.5 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <linux/compiler.h>
  8. #include <asm/io.h>
  9. #include <asm/processor.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/soc.h>
  12. #include <fsl_ifc.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  15. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  16. #endif
  17. void get_sys_info(struct sys_info *sys_info)
  18. {
  19. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  20. #ifdef CONFIG_FSL_IFC
  21. struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  22. u32 ccr;
  23. #endif
  24. #ifdef CONFIG_SYS_DPAA_FMAN
  25. u32 rcw_tmp;
  26. #endif
  27. struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
  28. unsigned int cpu;
  29. const u8 core_cplx_pll[8] = {
  30. [0] = 0, /* CC1 PPL / 1 */
  31. [1] = 0, /* CC1 PPL / 2 */
  32. [4] = 1, /* CC2 PPL / 1 */
  33. [5] = 1, /* CC2 PPL / 2 */
  34. };
  35. const u8 core_cplx_pll_div[8] = {
  36. [0] = 1, /* CC1 PPL / 1 */
  37. [1] = 2, /* CC1 PPL / 2 */
  38. [4] = 1, /* CC2 PPL / 1 */
  39. [5] = 2, /* CC2 PPL / 2 */
  40. };
  41. uint i;
  42. uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  43. uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  44. unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  45. sys_info->freq_systembus = sysclk;
  46. #ifdef CONFIG_DDR_CLK_FREQ
  47. sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  48. #else
  49. sys_info->freq_ddrbus = sysclk;
  50. #endif
  51. sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  52. FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
  53. FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
  54. sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  55. FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
  56. FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
  57. for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  58. ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
  59. if (ratio[i] > 4)
  60. freq_c_pll[i] = sysclk * ratio[i];
  61. else
  62. freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
  63. }
  64. for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
  65. u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
  66. & 0xf;
  67. u32 cplx_pll = core_cplx_pll[c_pll_sel];
  68. sys_info->freq_processor[cpu] =
  69. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  70. }
  71. #define HWA_CGA_M1_CLK_SEL 0xe0000000
  72. #define HWA_CGA_M1_CLK_SHIFT 29
  73. #ifdef CONFIG_SYS_DPAA_FMAN
  74. rcw_tmp = in_be32(&gur->rcwsr[7]);
  75. switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
  76. case 2:
  77. sys_info->freq_fman[0] = freq_c_pll[0] / 2;
  78. break;
  79. case 3:
  80. sys_info->freq_fman[0] = freq_c_pll[0] / 3;
  81. break;
  82. case 6:
  83. sys_info->freq_fman[0] = freq_c_pll[1] / 2;
  84. break;
  85. case 7:
  86. sys_info->freq_fman[0] = freq_c_pll[1] / 3;
  87. break;
  88. default:
  89. printf("Error: Unknown FMan1 clock select!\n");
  90. break;
  91. }
  92. #endif
  93. #define HWA_CGA_M2_CLK_SEL 0x00000007
  94. #define HWA_CGA_M2_CLK_SHIFT 0
  95. #if defined(CONFIG_FSL_IFC)
  96. ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
  97. ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
  98. sys_info->freq_localbus = sys_info->freq_systembus / ccr;
  99. #endif
  100. }
  101. int get_clocks(void)
  102. {
  103. struct sys_info sys_info;
  104. get_sys_info(&sys_info);
  105. gd->cpu_clk = sys_info.freq_processor[0];
  106. gd->bus_clk = sys_info.freq_systembus;
  107. gd->mem_clk = sys_info.freq_ddrbus;
  108. if (gd->cpu_clk != 0)
  109. return 0;
  110. else
  111. return 1;
  112. }
  113. ulong get_bus_freq(ulong dummy)
  114. {
  115. return gd->bus_clk;
  116. }
  117. ulong get_ddr_freq(ulong dummy)
  118. {
  119. return gd->mem_clk;
  120. }
  121. int get_serial_clock(void)
  122. {
  123. return gd->bus_clk;
  124. }
  125. unsigned int mxc_get_clock(enum mxc_clock clk)
  126. {
  127. switch (clk) {
  128. case MXC_I2C_CLK:
  129. return get_bus_freq(0);
  130. case MXC_DSPI_CLK:
  131. return get_bus_freq(0);
  132. case MXC_UART_CLK:
  133. return get_bus_freq(0);
  134. default:
  135. printf("Unsupported clock\n");
  136. }
  137. return 0;
  138. }