qemu-arm.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017 Tuomas Tynkkynen
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dm.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <virtio_types.h>
  12. #include <virtio.h>
  13. #ifdef CONFIG_ARM64
  14. #include <asm/armv8/mmu.h>
  15. static struct mm_region qemu_arm64_mem_map[] = {
  16. {
  17. /* Flash */
  18. .virt = 0x00000000UL,
  19. .phys = 0x00000000UL,
  20. .size = 0x08000000UL,
  21. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  22. PTE_BLOCK_INNER_SHARE
  23. }, {
  24. /* Lowmem peripherals */
  25. .virt = 0x08000000UL,
  26. .phys = 0x08000000UL,
  27. .size = 0x38000000,
  28. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29. PTE_BLOCK_NON_SHARE |
  30. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31. }, {
  32. /* RAM */
  33. .virt = 0x40000000UL,
  34. .phys = 0x40000000UL,
  35. .size = 255UL * SZ_1G,
  36. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  37. PTE_BLOCK_INNER_SHARE
  38. }, {
  39. /* Highmem PCI-E ECAM memory area */
  40. .virt = 0x4010000000ULL,
  41. .phys = 0x4010000000ULL,
  42. .size = 0x10000000,
  43. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44. PTE_BLOCK_NON_SHARE |
  45. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  46. }, {
  47. /* Highmem PCI-E MMIO memory area */
  48. .virt = 0x8000000000ULL,
  49. .phys = 0x8000000000ULL,
  50. .size = 0x8000000000ULL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  52. PTE_BLOCK_NON_SHARE |
  53. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  54. }, {
  55. /* List terminator */
  56. 0,
  57. }
  58. };
  59. struct mm_region *mem_map = qemu_arm64_mem_map;
  60. #endif
  61. int board_init(void)
  62. {
  63. return 0;
  64. }
  65. int board_late_init(void)
  66. {
  67. /*
  68. * Make sure virtio bus is enumerated so that peripherals
  69. * on the virtio bus can be discovered by their drivers
  70. */
  71. virtio_init();
  72. return 0;
  73. }
  74. int dram_init(void)
  75. {
  76. if (fdtdec_setup_mem_size_base() != 0)
  77. return -EINVAL;
  78. return 0;
  79. }
  80. int dram_init_banksize(void)
  81. {
  82. fdtdec_setup_memory_banksize();
  83. return 0;
  84. }
  85. void *board_fdt_blob_setup(int *err)
  86. {
  87. *err = 0;
  88. /* QEMU loads a generated DTB for us at the start of RAM. */
  89. return (void *)CONFIG_SYS_SDRAM_BASE;
  90. }
  91. void enable_caches(void)
  92. {
  93. icache_enable();
  94. dcache_enable();
  95. }
  96. #if defined(CONFIG_EFI_RNG_PROTOCOL)
  97. #include <efi_loader.h>
  98. #include <efi_rng.h>
  99. #include <dm/device-internal.h>
  100. efi_status_t platform_get_rng_device(struct udevice **dev)
  101. {
  102. int ret;
  103. efi_status_t status = EFI_DEVICE_ERROR;
  104. struct udevice *bus, *devp;
  105. for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
  106. uclass_next_device(&bus)) {
  107. for (device_find_first_child(bus, &devp); devp;
  108. device_find_next_child(&devp)) {
  109. if (device_get_uclass_id(devp) == UCLASS_RNG) {
  110. *dev = devp;
  111. status = EFI_SUCCESS;
  112. break;
  113. }
  114. }
  115. }
  116. if (status != EFI_SUCCESS) {
  117. debug("No rng device found\n");
  118. return EFI_DEVICE_ERROR;
  119. }
  120. if (*dev) {
  121. ret = device_probe(*dev);
  122. if (ret)
  123. return EFI_DEVICE_ERROR;
  124. } else {
  125. debug("Couldn't get child device\n");
  126. return EFI_DEVICE_ERROR;
  127. }
  128. return EFI_SUCCESS;
  129. }
  130. #endif /* CONFIG_EFI_RNG_PROTOCOL */
  131. #ifdef CONFIG_ARM64
  132. #define __W "w"
  133. #else
  134. #define __W
  135. #endif
  136. u8 flash_read8(void *addr)
  137. {
  138. u8 ret;
  139. asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
  140. return ret;
  141. }
  142. u16 flash_read16(void *addr)
  143. {
  144. u16 ret;
  145. asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
  146. return ret;
  147. }
  148. u32 flash_read32(void *addr)
  149. {
  150. u32 ret;
  151. asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
  152. return ret;
  153. }
  154. void flash_write8(u8 value, void *addr)
  155. {
  156. asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
  157. }
  158. void flash_write16(u16 value, void *addr)
  159. {
  160. asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
  161. }
  162. void flash_write32(u32 value, void *addr)
  163. {
  164. asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
  165. }