colibri_imx6.c 32 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. * Copyright (C) 2014-2019, Toradex AG
  6. * copied from nitrogen6x
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <env.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/mx6-ddr.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/mxc_hdmi.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/bootm.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/sata.h>
  23. #include <asm/mach-imx/video.h>
  24. #include <cpu.h>
  25. #include <dm/platform_data/serial_mxc.h>
  26. #include <fsl_esdhc_imx.h>
  27. #include <imx_thermal.h>
  28. #include <micrel.h>
  29. #include <miiphy.h>
  30. #include <netdev.h>
  31. #include <cpu.h>
  32. #include "../common/tdx-cfg-block.h"
  33. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  34. #include "pf0100.h"
  35. #endif
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  41. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  42. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  44. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  45. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  46. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  50. PAD_CTL_SRE_SLOW)
  51. #define NO_PULLUP ( \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  53. PAD_CTL_SRE_SLOW)
  54. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  55. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  56. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  57. #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  58. int dram_init(void)
  59. {
  60. /* use the DDR controllers configured size */
  61. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  62. (ulong)imx_ddr_size());
  63. return 0;
  64. }
  65. /* Colibri UARTA */
  66. iomux_v3_cfg_t const uart1_pads[] = {
  67. MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. };
  70. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  71. /* Colibri MMC */
  72. iomux_v3_cfg_t const usdhc1_pads[] = {
  73. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  80. # define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  81. };
  82. /* eMMC */
  83. iomux_v3_cfg_t const usdhc3_pads[] = {
  84. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  85. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  86. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  87. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  88. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  89. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  90. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  91. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  92. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  93. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  94. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. };
  96. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  97. iomux_v3_cfg_t const enet_pads[] = {
  98. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  100. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  101. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  102. MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  103. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  104. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  105. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  106. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  107. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  108. };
  109. static void setup_iomux_enet(void)
  110. {
  111. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  112. }
  113. /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
  114. iomux_v3_cfg_t const gpio_pads[] = {
  115. /* ADDRESS[17:18] [25] used as GPIO */
  116. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  117. MUX_MODE_SION,
  118. MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  119. MUX_MODE_SION,
  120. MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
  121. MUX_MODE_SION,
  122. /* ADDRESS[19:24] used as GPIO */
  123. MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  124. MUX_MODE_SION,
  125. MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  126. MUX_MODE_SION,
  127. MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  128. MUX_MODE_SION,
  129. MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  130. MUX_MODE_SION,
  131. MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  132. MUX_MODE_SION,
  133. MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
  134. MUX_MODE_SION,
  135. /* DATA[16:29] [31] used as GPIO */
  136. MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  137. MUX_MODE_SION,
  138. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  139. MUX_MODE_SION,
  140. MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  141. MUX_MODE_SION,
  142. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  143. MUX_MODE_SION,
  144. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  145. MUX_MODE_SION,
  146. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  147. MUX_MODE_SION,
  148. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
  149. MUX_MODE_SION,
  150. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  151. MUX_MODE_SION,
  152. MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  153. MUX_MODE_SION,
  154. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  155. MUX_MODE_SION,
  156. MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  157. MUX_MODE_SION,
  158. MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  159. MUX_MODE_SION,
  160. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  161. MUX_MODE_SION,
  162. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  163. MUX_MODE_SION,
  164. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
  165. MUX_MODE_SION,
  166. /* DQM[0:3] used as GPIO */
  167. MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
  168. MUX_MODE_SION,
  169. MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
  170. MUX_MODE_SION,
  171. MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  172. MUX_MODE_SION,
  173. MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  174. MUX_MODE_SION,
  175. /* RDY used as GPIO */
  176. MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  177. MUX_MODE_SION,
  178. /* ADDRESS[16] DATA[30] used as GPIO */
  179. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  180. MUX_MODE_SION,
  181. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  182. MUX_MODE_SION,
  183. /* CSI pins used as GPIO */
  184. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  185. MUX_MODE_SION,
  186. MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  187. MUX_MODE_SION,
  188. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  189. MUX_MODE_SION,
  190. MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  191. MUX_MODE_SION,
  192. MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  193. MUX_MODE_SION,
  194. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  195. MUX_MODE_SION,
  196. MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  197. MUX_MODE_SION,
  198. MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  199. MUX_MODE_SION,
  200. MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
  201. MUX_MODE_SION,
  202. MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  203. MUX_MODE_SION,
  204. MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  205. MUX_MODE_SION,
  206. MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  207. MUX_MODE_SION,
  208. MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  209. MUX_MODE_SION,
  210. /* GPIO */
  211. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
  212. MUX_MODE_SION,
  213. MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  214. MUX_MODE_SION,
  215. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  216. MUX_MODE_SION,
  217. MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
  218. MUX_MODE_SION,
  219. MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
  220. MUX_MODE_SION,
  221. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  222. MUX_MODE_SION,
  223. MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  224. MUX_MODE_SION,
  225. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  226. MUX_MODE_SION,
  227. MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  228. MUX_MODE_SION,
  229. MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  230. MUX_MODE_SION,
  231. MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  232. MUX_MODE_SION,
  233. /* USBH_OC */
  234. MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
  235. /* USBC_ID */
  236. MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
  237. /* USBC_DET */
  238. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
  239. };
  240. static void setup_iomux_gpio(void)
  241. {
  242. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  243. }
  244. iomux_v3_cfg_t const usb_pads[] = {
  245. /* USBH_PEN */
  246. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  247. # define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
  248. };
  249. /*
  250. * UARTs are used in DTE mode, switch the mode on all UARTs before
  251. * any pinmuxing connects a (DCE) output to a transceiver output.
  252. */
  253. #define UCR3 0x88 /* FIFO Control Register */
  254. #define UCR3_RI BIT(8) /* RIDELT DTE mode */
  255. #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
  256. #define UFCR 0x90 /* FIFO Control Register */
  257. #define UFCR_DCEDTE BIT(6) /* DCE=0 */
  258. static void setup_dtemode_uart(void)
  259. {
  260. setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  261. setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  262. setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
  263. clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
  264. clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
  265. clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
  266. }
  267. static void setup_iomux_uart(void)
  268. {
  269. setup_dtemode_uart();
  270. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  271. }
  272. #ifdef CONFIG_USB_EHCI_MX6
  273. int board_ehci_hcd_init(int port)
  274. {
  275. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  276. return 0;
  277. }
  278. #endif
  279. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  280. /* use the following sequence: eMMC, MMC */
  281. struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  282. {USDHC3_BASE_ADDR},
  283. {USDHC1_BASE_ADDR},
  284. };
  285. int board_mmc_getcd(struct mmc *mmc)
  286. {
  287. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  288. int ret = true; /* default: assume inserted */
  289. switch (cfg->esdhc_base) {
  290. case USDHC1_BASE_ADDR:
  291. gpio_request(GPIO_MMC_CD, "MMC_CD");
  292. gpio_direction_input(GPIO_MMC_CD);
  293. ret = !gpio_get_value(GPIO_MMC_CD);
  294. break;
  295. }
  296. return ret;
  297. }
  298. int board_mmc_init(bd_t *bis)
  299. {
  300. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  301. unsigned reg = readl(&psrc->sbmr1) >> 11;
  302. /*
  303. * Upon reading BOOT_CFG register the following map is done:
  304. * Bit 11 and 12 of BOOT_CFG register can determine the current
  305. * mmc port
  306. * 0x1 SD1
  307. * 0x2 SD2
  308. * 0x3 SD4
  309. */
  310. switch (reg & 0x3) {
  311. case 0x0:
  312. imx_iomux_v3_setup_multiple_pads(
  313. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  314. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  315. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  316. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  317. break;
  318. case 0x2:
  319. imx_iomux_v3_setup_multiple_pads(
  320. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  321. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  322. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  323. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  324. break;
  325. default:
  326. puts("MMC boot device not available");
  327. }
  328. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  329. }
  330. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  331. int board_phy_config(struct phy_device *phydev)
  332. {
  333. if (phydev->drv->config)
  334. phydev->drv->config(phydev);
  335. return 0;
  336. }
  337. int board_eth_init(bd_t *bis)
  338. {
  339. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  340. uint32_t base = IMX_FEC_BASE;
  341. struct mii_dev *bus = NULL;
  342. struct phy_device *phydev = NULL;
  343. int ret;
  344. /* provide the PHY clock from the i.MX 6 */
  345. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  346. if (ret)
  347. return ret;
  348. /* set gpr1[ENET_CLK_SEL] */
  349. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  350. setup_iomux_enet();
  351. #ifdef CONFIG_FEC_MXC
  352. bus = fec_get_miibus(base, -1);
  353. if (!bus)
  354. return 0;
  355. /* scan PHY 1..7 */
  356. phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
  357. if (!phydev) {
  358. free(bus);
  359. puts("no PHY found\n");
  360. return 0;
  361. }
  362. phy_reset(phydev);
  363. printf("using PHY at %d\n", phydev->addr);
  364. ret = fec_probe(bis, -1, base, bus, phydev);
  365. if (ret) {
  366. printf("FEC MXC: %s:failed\n", __func__);
  367. free(phydev);
  368. free(bus);
  369. }
  370. #endif /* CONFIG_FEC_MXC */
  371. return 0;
  372. }
  373. static iomux_v3_cfg_t const pwr_intb_pads[] = {
  374. /*
  375. * the bootrom sets the iomux to vselect, potentially connecting
  376. * two outputs. Set this back to GPIO
  377. */
  378. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
  379. };
  380. #if defined(CONFIG_VIDEO_IPUV3)
  381. static iomux_v3_cfg_t const backlight_pads[] = {
  382. /* Backlight On */
  383. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  384. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
  385. /* Backlight PWM, used as GPIO in U-Boot */
  386. MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
  387. MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  388. MUX_MODE_SION,
  389. #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
  390. };
  391. static iomux_v3_cfg_t const rgb_pads[] = {
  392. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
  393. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
  394. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
  395. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
  396. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
  397. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
  398. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
  399. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
  400. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
  401. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
  402. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
  403. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
  404. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
  405. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
  406. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
  407. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
  408. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
  409. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
  410. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
  411. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
  412. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
  413. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
  414. };
  415. static void do_enable_hdmi(struct display_info_t const *dev)
  416. {
  417. imx_enable_hdmi_phy();
  418. }
  419. static void enable_rgb(struct display_info_t const *dev)
  420. {
  421. imx_iomux_v3_setup_multiple_pads(
  422. rgb_pads,
  423. ARRAY_SIZE(rgb_pads));
  424. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  425. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  426. }
  427. static int detect_default(struct display_info_t const *dev)
  428. {
  429. (void) dev;
  430. return 1;
  431. }
  432. struct display_info_t const displays[] = {{
  433. .bus = -1,
  434. .addr = 0,
  435. .pixfmt = IPU_PIX_FMT_RGB24,
  436. .detect = detect_hdmi,
  437. .enable = do_enable_hdmi,
  438. .mode = {
  439. .name = "HDMI",
  440. .refresh = 60,
  441. .xres = 1024,
  442. .yres = 768,
  443. .pixclock = 15385,
  444. .left_margin = 220,
  445. .right_margin = 40,
  446. .upper_margin = 21,
  447. .lower_margin = 7,
  448. .hsync_len = 60,
  449. .vsync_len = 10,
  450. .sync = FB_SYNC_EXT,
  451. .vmode = FB_VMODE_NONINTERLACED
  452. } }, {
  453. .bus = -1,
  454. .addr = 0,
  455. .pixfmt = IPU_PIX_FMT_RGB666,
  456. .detect = detect_default,
  457. .enable = enable_rgb,
  458. .mode = {
  459. .name = "vga-rgb",
  460. .refresh = 60,
  461. .xres = 640,
  462. .yres = 480,
  463. .pixclock = 33000,
  464. .left_margin = 48,
  465. .right_margin = 16,
  466. .upper_margin = 31,
  467. .lower_margin = 11,
  468. .hsync_len = 96,
  469. .vsync_len = 2,
  470. .sync = 0,
  471. .vmode = FB_VMODE_NONINTERLACED
  472. } }, {
  473. .bus = -1,
  474. .addr = 0,
  475. .pixfmt = IPU_PIX_FMT_RGB666,
  476. .enable = enable_rgb,
  477. .mode = {
  478. .name = "wvga-rgb",
  479. .refresh = 60,
  480. .xres = 800,
  481. .yres = 480,
  482. .pixclock = 25000,
  483. .left_margin = 40,
  484. .right_margin = 88,
  485. .upper_margin = 33,
  486. .lower_margin = 10,
  487. .hsync_len = 128,
  488. .vsync_len = 2,
  489. .sync = 0,
  490. .vmode = FB_VMODE_NONINTERLACED
  491. } } };
  492. size_t display_count = ARRAY_SIZE(displays);
  493. static void setup_display(void)
  494. {
  495. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  496. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  497. int reg;
  498. enable_ipu_clock();
  499. imx_setup_hdmi();
  500. /* Turn on LDB0,IPU,IPU DI0 clocks */
  501. reg = __raw_readl(&mxc_ccm->CCGR3);
  502. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  503. writel(reg, &mxc_ccm->CCGR3);
  504. /* set LDB0, LDB1 clk select to 011/011 */
  505. reg = readl(&mxc_ccm->cs2cdr);
  506. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  507. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  508. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  509. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  510. writel(reg, &mxc_ccm->cs2cdr);
  511. reg = readl(&mxc_ccm->cscmr2);
  512. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  513. writel(reg, &mxc_ccm->cscmr2);
  514. reg = readl(&mxc_ccm->chsccdr);
  515. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  516. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  517. writel(reg, &mxc_ccm->chsccdr);
  518. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  519. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  520. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  521. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  522. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  523. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  524. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  525. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  526. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  527. writel(reg, &iomux->gpr[2]);
  528. reg = readl(&iomux->gpr[3]);
  529. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  530. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  531. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  532. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  533. writel(reg, &iomux->gpr[3]);
  534. /* backlight unconditionally on for now */
  535. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  536. ARRAY_SIZE(backlight_pads));
  537. /* use 0 for EDT 7", use 1 for LG fullHD panel */
  538. gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
  539. gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
  540. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  541. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  542. }
  543. /*
  544. * Backlight off before OS handover
  545. */
  546. void board_preboot_os(void)
  547. {
  548. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
  549. gpio_direction_output(RGB_BACKLIGHT_GP, 0);
  550. }
  551. #endif /* defined(CONFIG_VIDEO_IPUV3) */
  552. int board_early_init_f(void)
  553. {
  554. imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
  555. ARRAY_SIZE(pwr_intb_pads));
  556. setup_iomux_uart();
  557. return 0;
  558. }
  559. /*
  560. * Do not overwrite the console
  561. * Use always serial for U-Boot console
  562. */
  563. int overwrite_console(void)
  564. {
  565. return 1;
  566. }
  567. int board_init(void)
  568. {
  569. /* address of boot parameters */
  570. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  571. #if defined(CONFIG_VIDEO_IPUV3)
  572. setup_display();
  573. #endif
  574. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  575. (void) pmic_init();
  576. #endif
  577. #ifdef CONFIG_SATA
  578. setup_sata();
  579. #endif
  580. setup_iomux_gpio();
  581. return 0;
  582. }
  583. #ifdef CONFIG_BOARD_LATE_INIT
  584. int board_late_init(void)
  585. {
  586. #if defined(CONFIG_REVISION_TAG) && \
  587. defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
  588. char env_str[256];
  589. u32 rev;
  590. rev = get_board_rev();
  591. snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
  592. env_set("board_rev", env_str);
  593. #endif
  594. #ifdef CONFIG_CMD_USB_SDP
  595. if (is_boot_from_usb()) {
  596. printf("Serial Downloader recovery mode, using sdp command\n");
  597. env_set("bootdelay", "0");
  598. env_set("bootcmd", "sdp 0");
  599. }
  600. #endif /* CONFIG_CMD_USB_SDP */
  601. return 0;
  602. }
  603. #endif /* CONFIG_BOARD_LATE_INIT */
  604. int checkboard(void)
  605. {
  606. char it[] = " IT";
  607. int minc, maxc;
  608. switch (get_cpu_temp_grade(&minc, &maxc)) {
  609. case TEMP_AUTOMOTIVE:
  610. case TEMP_INDUSTRIAL:
  611. break;
  612. case TEMP_EXTCOMMERCIAL:
  613. default:
  614. it[0] = 0;
  615. };
  616. printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
  617. is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
  618. (gd->ram_size == 0x20000000) ? "512" : "256", it);
  619. return 0;
  620. }
  621. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  622. int ft_board_setup(void *blob, bd_t *bd)
  623. {
  624. u32 cma_size;
  625. ft_common_board_setup(blob, bd);
  626. cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
  627. cma_size = min((u32)(gd->ram_size >> 1), cma_size);
  628. fdt_setprop_u32(blob,
  629. fdt_path_offset(blob, "/reserved-memory/linux,cma"),
  630. "size",
  631. cma_size);
  632. return 0;
  633. }
  634. #endif
  635. #ifdef CONFIG_CMD_BMODE
  636. static const struct boot_mode board_boot_modes[] = {
  637. {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  638. {NULL, 0},
  639. };
  640. #endif
  641. int misc_init_r(void)
  642. {
  643. #ifdef CONFIG_CMD_BMODE
  644. add_board_boot_modes(board_boot_modes);
  645. #endif
  646. return 0;
  647. }
  648. #ifdef CONFIG_LDO_BYPASS_CHECK
  649. /* TODO, use external pmic, for now always ldo_enable */
  650. void ldo_mode_set(int ldo_bypass)
  651. {
  652. return;
  653. }
  654. #endif
  655. #ifdef CONFIG_SPL_BUILD
  656. #include <spl.h>
  657. #include <linux/libfdt.h>
  658. #include "asm/arch/mx6dl-ddr.h"
  659. #include "asm/arch/iomux.h"
  660. #include "asm/arch/crm_regs.h"
  661. static int mx6s_dcd_table[] = {
  662. /* ddr-setup.cfg */
  663. MX6_IOM_DRAM_SDQS0, 0x00000030,
  664. MX6_IOM_DRAM_SDQS1, 0x00000030,
  665. MX6_IOM_DRAM_SDQS2, 0x00000030,
  666. MX6_IOM_DRAM_SDQS3, 0x00000030,
  667. MX6_IOM_DRAM_SDQS4, 0x00000030,
  668. MX6_IOM_DRAM_SDQS5, 0x00000030,
  669. MX6_IOM_DRAM_SDQS6, 0x00000030,
  670. MX6_IOM_DRAM_SDQS7, 0x00000030,
  671. MX6_IOM_GRP_B0DS, 0x00000030,
  672. MX6_IOM_GRP_B1DS, 0x00000030,
  673. MX6_IOM_GRP_B2DS, 0x00000030,
  674. MX6_IOM_GRP_B3DS, 0x00000030,
  675. MX6_IOM_GRP_B4DS, 0x00000030,
  676. MX6_IOM_GRP_B5DS, 0x00000030,
  677. MX6_IOM_GRP_B6DS, 0x00000030,
  678. MX6_IOM_GRP_B7DS, 0x00000030,
  679. MX6_IOM_GRP_ADDDS, 0x00000030,
  680. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  681. MX6_IOM_GRP_CTLDS, 0x00000030,
  682. MX6_IOM_DRAM_DQM0, 0x00020030,
  683. MX6_IOM_DRAM_DQM1, 0x00020030,
  684. MX6_IOM_DRAM_DQM2, 0x00020030,
  685. MX6_IOM_DRAM_DQM3, 0x00020030,
  686. MX6_IOM_DRAM_DQM4, 0x00020030,
  687. MX6_IOM_DRAM_DQM5, 0x00020030,
  688. MX6_IOM_DRAM_DQM6, 0x00020030,
  689. MX6_IOM_DRAM_DQM7, 0x00020030,
  690. MX6_IOM_DRAM_CAS, 0x00020030,
  691. MX6_IOM_DRAM_RAS, 0x00020030,
  692. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  693. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  694. MX6_IOM_DRAM_RESET, 0x00020030,
  695. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  696. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  697. MX6_IOM_DRAM_SDODT0, 0x00003030,
  698. MX6_IOM_DRAM_SDODT1, 0x00003030,
  699. /* (differential input) */
  700. MX6_IOM_DDRMODE_CTL, 0x00020000,
  701. /* (differential input) */
  702. MX6_IOM_GRP_DDRMODE, 0x00020000,
  703. /* disable ddr pullups */
  704. MX6_IOM_GRP_DDRPKE, 0x00000000,
  705. MX6_IOM_DRAM_SDBA2, 0x00000000,
  706. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  707. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  708. /* Read data DQ Byte0-3 delay */
  709. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  710. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  711. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  712. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  713. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  714. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  715. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  716. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  717. /*
  718. * MDMISC mirroring interleaved (row/bank/col)
  719. */
  720. /* TODO: check what the RALAT field does */
  721. MX6_MMDC_P0_MDMISC, 0x00081740,
  722. /*
  723. * MDSCR con_req
  724. */
  725. MX6_MMDC_P0_MDSCR, 0x00008000,
  726. /* 800mhz_2x64mx16.cfg */
  727. MX6_MMDC_P0_MDPDC, 0x0002002D,
  728. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  729. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  730. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  731. MX6_MMDC_P0_MDRWD, 0x000026D2,
  732. MX6_MMDC_P0_MDOR, 0x00301023,
  733. MX6_MMDC_P0_MDOTC, 0x00333030,
  734. MX6_MMDC_P0_MDPDC, 0x0002556D,
  735. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  736. MX6_MMDC_P0_MDASP, 0x00000017,
  737. /* DDR3 DATA BUS SIZE: 64BIT */
  738. /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
  739. /* DDR3 DATA BUS SIZE: 32BIT */
  740. MX6_MMDC_P0_MDCTL, 0x82190000,
  741. /* Write commands to DDR */
  742. /* Load Mode Registers */
  743. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  744. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  745. MX6_MMDC_P0_MDSCR, 0x04008032,
  746. MX6_MMDC_P0_MDSCR, 0x00008033,
  747. MX6_MMDC_P0_MDSCR, 0x00048031,
  748. MX6_MMDC_P0_MDSCR, 0x13208030,
  749. /* ZQ calibration */
  750. MX6_MMDC_P0_MDSCR, 0x04008040,
  751. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  752. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  753. MX6_MMDC_P0_MDREF, 0x00005800,
  754. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  755. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  756. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  757. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  758. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  759. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  760. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  761. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  762. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  763. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  764. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  765. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  766. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  767. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  768. MX6_MMDC_P0_MPMUR0, 0x00000800,
  769. MX6_MMDC_P1_MPMUR0, 0x00000800,
  770. MX6_MMDC_P0_MDSCR, 0x00000000,
  771. MX6_MMDC_P0_MAPSR, 0x00011006,
  772. };
  773. static int mx6dl_dcd_table[] = {
  774. /* ddr-setup.cfg */
  775. MX6_IOM_DRAM_SDQS0, 0x00000030,
  776. MX6_IOM_DRAM_SDQS1, 0x00000030,
  777. MX6_IOM_DRAM_SDQS2, 0x00000030,
  778. MX6_IOM_DRAM_SDQS3, 0x00000030,
  779. MX6_IOM_DRAM_SDQS4, 0x00000030,
  780. MX6_IOM_DRAM_SDQS5, 0x00000030,
  781. MX6_IOM_DRAM_SDQS6, 0x00000030,
  782. MX6_IOM_DRAM_SDQS7, 0x00000030,
  783. MX6_IOM_GRP_B0DS, 0x00000030,
  784. MX6_IOM_GRP_B1DS, 0x00000030,
  785. MX6_IOM_GRP_B2DS, 0x00000030,
  786. MX6_IOM_GRP_B3DS, 0x00000030,
  787. MX6_IOM_GRP_B4DS, 0x00000030,
  788. MX6_IOM_GRP_B5DS, 0x00000030,
  789. MX6_IOM_GRP_B6DS, 0x00000030,
  790. MX6_IOM_GRP_B7DS, 0x00000030,
  791. MX6_IOM_GRP_ADDDS, 0x00000030,
  792. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  793. MX6_IOM_GRP_CTLDS, 0x00000030,
  794. MX6_IOM_DRAM_DQM0, 0x00020030,
  795. MX6_IOM_DRAM_DQM1, 0x00020030,
  796. MX6_IOM_DRAM_DQM2, 0x00020030,
  797. MX6_IOM_DRAM_DQM3, 0x00020030,
  798. MX6_IOM_DRAM_DQM4, 0x00020030,
  799. MX6_IOM_DRAM_DQM5, 0x00020030,
  800. MX6_IOM_DRAM_DQM6, 0x00020030,
  801. MX6_IOM_DRAM_DQM7, 0x00020030,
  802. MX6_IOM_DRAM_CAS, 0x00020030,
  803. MX6_IOM_DRAM_RAS, 0x00020030,
  804. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  805. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  806. MX6_IOM_DRAM_RESET, 0x00020030,
  807. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  808. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  809. MX6_IOM_DRAM_SDODT0, 0x00003030,
  810. MX6_IOM_DRAM_SDODT1, 0x00003030,
  811. /* (differential input) */
  812. MX6_IOM_DDRMODE_CTL, 0x00020000,
  813. /* (differential input) */
  814. MX6_IOM_GRP_DDRMODE, 0x00020000,
  815. /* disable ddr pullups */
  816. MX6_IOM_GRP_DDRPKE, 0x00000000,
  817. MX6_IOM_DRAM_SDBA2, 0x00000000,
  818. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  819. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  820. /* Read data DQ Byte0-3 delay */
  821. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  822. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  823. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  824. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  825. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  826. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  827. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  828. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  829. /*
  830. * MDMISC mirroring interleaved (row/bank/col)
  831. */
  832. /* TODO: check what the RALAT field does */
  833. MX6_MMDC_P0_MDMISC, 0x00081740,
  834. /*
  835. * MDSCR con_req
  836. */
  837. MX6_MMDC_P0_MDSCR, 0x00008000,
  838. /* 800mhz_2x64mx16.cfg */
  839. MX6_MMDC_P0_MDPDC, 0x0002002D,
  840. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  841. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  842. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  843. MX6_MMDC_P0_MDRWD, 0x000026D2,
  844. MX6_MMDC_P0_MDOR, 0x00301023,
  845. MX6_MMDC_P0_MDOTC, 0x00333030,
  846. MX6_MMDC_P0_MDPDC, 0x0002556D,
  847. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  848. MX6_MMDC_P0_MDASP, 0x00000017,
  849. /* DDR3 DATA BUS SIZE: 64BIT */
  850. MX6_MMDC_P0_MDCTL, 0x821A0000,
  851. /* DDR3 DATA BUS SIZE: 32BIT */
  852. /* MX6_MMDC_P0_MDCTL, 0x82190000, */
  853. /* Write commands to DDR */
  854. /* Load Mode Registers */
  855. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  856. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  857. MX6_MMDC_P0_MDSCR, 0x04008032,
  858. MX6_MMDC_P0_MDSCR, 0x00008033,
  859. MX6_MMDC_P0_MDSCR, 0x00048031,
  860. MX6_MMDC_P0_MDSCR, 0x13208030,
  861. /* ZQ calibration */
  862. MX6_MMDC_P0_MDSCR, 0x04008040,
  863. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  864. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  865. MX6_MMDC_P0_MDREF, 0x00005800,
  866. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  867. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  868. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  869. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  870. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  871. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  872. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  873. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  874. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  875. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  876. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  877. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  878. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  879. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  880. MX6_MMDC_P0_MPMUR0, 0x00000800,
  881. MX6_MMDC_P1_MPMUR0, 0x00000800,
  882. MX6_MMDC_P0_MDSCR, 0x00000000,
  883. MX6_MMDC_P0_MAPSR, 0x00011006,
  884. };
  885. static void ccgr_init(void)
  886. {
  887. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  888. writel(0x00C03F3F, &ccm->CCGR0);
  889. writel(0x0030FC03, &ccm->CCGR1);
  890. writel(0x0FFFFFF3, &ccm->CCGR2);
  891. writel(0x3FF0300F, &ccm->CCGR3);
  892. writel(0x00FFF300, &ccm->CCGR4);
  893. writel(0x0F0000F3, &ccm->CCGR5);
  894. writel(0x000003FF, &ccm->CCGR6);
  895. /*
  896. * Setup CCM_CCOSR register as follows:
  897. *
  898. * cko1_en = 1 --> CKO1 enabled
  899. * cko1_div = 111 --> divide by 8
  900. * cko1_sel = 1011 --> ahb_clk_root
  901. *
  902. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  903. */
  904. writel(0x000000FB, &ccm->ccosr);
  905. }
  906. static void ddr_init(int *table, int size)
  907. {
  908. int i;
  909. for (i = 0; i < size / 2 ; i++)
  910. writel(table[2 * i + 1], table[2 * i]);
  911. }
  912. static void spl_dram_init(void)
  913. {
  914. int minc, maxc;
  915. switch (get_cpu_temp_grade(&minc, &maxc)) {
  916. case TEMP_COMMERCIAL:
  917. case TEMP_EXTCOMMERCIAL:
  918. if (is_cpu_type(MXC_CPU_MX6DL)) {
  919. puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
  920. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  921. } else {
  922. puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
  923. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  924. }
  925. break;
  926. case TEMP_INDUSTRIAL:
  927. case TEMP_AUTOMOTIVE:
  928. default:
  929. if (is_cpu_type(MXC_CPU_MX6DL)) {
  930. puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
  931. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  932. } else {
  933. puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
  934. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  935. }
  936. break;
  937. };
  938. udelay(100);
  939. }
  940. static iomux_v3_cfg_t const gpio_reset_pad[] = {
  941. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  942. MUX_MODE_SION
  943. #define GPIO_NRESET IMX_GPIO_NR(6, 27)
  944. };
  945. #define IMX_RESET_CAUSE_POR 0x00011
  946. static void nreset_out(void)
  947. {
  948. int reset_cause = get_imx_reset_cause();
  949. if (reset_cause != IMX_RESET_CAUSE_POR) {
  950. imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
  951. ARRAY_SIZE(gpio_reset_pad));
  952. gpio_direction_output(GPIO_NRESET, 1);
  953. udelay(100);
  954. gpio_direction_output(GPIO_NRESET, 0);
  955. }
  956. }
  957. void board_init_f(ulong dummy)
  958. {
  959. /* setup AIPS and disable watchdog */
  960. arch_cpu_init();
  961. ccgr_init();
  962. gpr_init();
  963. /* iomux */
  964. board_early_init_f();
  965. /* setup GP timer */
  966. timer_init();
  967. /* UART clocks enabled and gd valid - init serial console */
  968. preloader_console_init();
  969. /* Make sure we use dte mode */
  970. setup_dtemode_uart();
  971. /* DDR initialization */
  972. spl_dram_init();
  973. /* Clear the BSS. */
  974. memset(__bss_start, 0, __bss_end - __bss_start);
  975. /* Assert nReset_Out */
  976. nreset_out();
  977. /* load/boot image from boot device */
  978. board_init_r(NULL, 0);
  979. }
  980. void reset_cpu(ulong addr)
  981. {
  982. }
  983. #endif /* CONFIG_SPL_BUILD */
  984. static struct mxc_serial_platdata mxc_serial_plat = {
  985. .reg = (struct mxc_uart *)UART1_BASE,
  986. .use_dte = true,
  987. };
  988. U_BOOT_DEVICE(mxc_serial) = {
  989. .name = "serial_mxc",
  990. .platdata = &mxc_serial_plat,
  991. };