apalis_imx6.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. * Copyright (C) 2014-2019, Toradex AG
  6. * copied from nitrogen6x
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <ahci.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/mx6-ddr.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/mxc_hdmi.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/bootm.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/sata.h>
  23. #include <asm/mach-imx/video.h>
  24. #include <dm/device-internal.h>
  25. #include <dm/platform_data/serial_mxc.h>
  26. #include <dwc_ahsata.h>
  27. #include <env.h>
  28. #include <fsl_esdhc_imx.h>
  29. #include <imx_thermal.h>
  30. #include <micrel.h>
  31. #include <miiphy.h>
  32. #include <netdev.h>
  33. #include "../common/tdx-cfg-block.h"
  34. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35. #include "pf0100.h"
  36. #endif
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  45. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  49. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  51. PAD_CTL_SRE_SLOW)
  52. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  53. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  54. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  55. #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  56. #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  57. #define APALIS_IMX6_SATA_INIT_RETRIES 10
  58. int dram_init(void)
  59. {
  60. /* use the DDR controllers configured size */
  61. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  62. (ulong)imx_ddr_size());
  63. return 0;
  64. }
  65. /* Apalis UART1 */
  66. iomux_v3_cfg_t const uart1_pads_dce[] = {
  67. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. };
  70. iomux_v3_cfg_t const uart1_pads_dte[] = {
  71. MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72. MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. };
  74. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  75. /* Apalis MMC1 */
  76. iomux_v3_cfg_t const usdhc1_pads[] = {
  77. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83. MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84. MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85. MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86. MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  88. # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
  89. };
  90. /* Apalis SD1 */
  91. iomux_v3_cfg_t const usdhc2_pads[] = {
  92. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  99. # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
  100. };
  101. /* eMMC */
  102. iomux_v3_cfg_t const usdhc3_pads[] = {
  103. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  104. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  105. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  106. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  107. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  108. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  113. MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
  114. };
  115. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  116. int mx6_rgmii_rework(struct phy_device *phydev)
  117. {
  118. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  119. ksz9031_phy_extended_write(phydev, 0x02,
  120. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  121. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  122. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  123. ksz9031_phy_extended_write(phydev, 0x02,
  124. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  125. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  126. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  127. ksz9031_phy_extended_write(phydev, 0x02,
  128. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  129. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  130. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  131. ksz9031_phy_extended_write(phydev, 0x02,
  132. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  133. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  134. return 0;
  135. }
  136. iomux_v3_cfg_t const enet_pads[] = {
  137. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  138. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  139. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  140. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  141. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  142. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  143. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  147. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  148. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  149. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  150. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  151. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  152. /* KSZ9031 PHY Reset */
  153. MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  154. MUX_MODE_SION,
  155. # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
  156. };
  157. static void setup_iomux_enet(void)
  158. {
  159. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  160. }
  161. static int reset_enet_phy(struct mii_dev *bus)
  162. {
  163. /* Reset KSZ9031 PHY */
  164. gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
  165. gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
  166. mdelay(10);
  167. gpio_set_value(GPIO_ENET_PHY_RESET, 1);
  168. return 0;
  169. }
  170. /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
  171. iomux_v3_cfg_t const gpio_pads[] = {
  172. /* Apalis GPIO1 - GPIO8 */
  173. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  174. MUX_MODE_SION,
  175. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  176. MUX_MODE_SION,
  177. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  178. MUX_MODE_SION,
  179. MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  180. MUX_MODE_SION,
  181. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  182. MUX_MODE_SION,
  183. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
  184. MUX_MODE_SION,
  185. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  186. MUX_MODE_SION,
  187. MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  188. MUX_MODE_SION,
  189. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  190. MUX_MODE_SION,
  191. };
  192. static void setup_iomux_gpio(void)
  193. {
  194. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  195. }
  196. iomux_v3_cfg_t const usb_pads[] = {
  197. /* USBH_EN */
  198. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  199. # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
  200. /* USB_VBUS_DET */
  201. MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  202. # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
  203. /* USBO1_ID */
  204. MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
  205. /* USBO1_EN */
  206. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  207. # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
  208. };
  209. /*
  210. * UARTs are used in DTE mode, switch the mode on all UARTs before
  211. * any pinmuxing connects a (DCE) output to a transceiver output.
  212. */
  213. #define UCR3 0x88 /* FIFO Control Register */
  214. #define UCR3_RI BIT(8) /* RIDELT DTE mode */
  215. #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
  216. #define UFCR 0x90 /* FIFO Control Register */
  217. #define UFCR_DCEDTE BIT(6) /* DCE=0 */
  218. static void setup_dtemode_uart(void)
  219. {
  220. setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  221. setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  222. setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
  223. setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
  224. clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
  225. clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
  226. clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
  227. clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
  228. }
  229. static void setup_dcemode_uart(void)
  230. {
  231. clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  232. clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  233. clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
  234. clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
  235. }
  236. static void setup_iomux_dte_uart(void)
  237. {
  238. setup_dtemode_uart();
  239. imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
  240. ARRAY_SIZE(uart1_pads_dte));
  241. }
  242. static void setup_iomux_dce_uart(void)
  243. {
  244. setup_dcemode_uart();
  245. imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
  246. ARRAY_SIZE(uart1_pads_dce));
  247. }
  248. #ifdef CONFIG_USB_EHCI_MX6
  249. int board_ehci_hcd_init(int port)
  250. {
  251. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  252. return 0;
  253. }
  254. #endif
  255. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  256. /* use the following sequence: eMMC, MMC1, SD1 */
  257. struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  258. {USDHC3_BASE_ADDR},
  259. {USDHC1_BASE_ADDR},
  260. {USDHC2_BASE_ADDR},
  261. };
  262. int board_mmc_getcd(struct mmc *mmc)
  263. {
  264. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  265. int ret = true; /* default: assume inserted */
  266. switch (cfg->esdhc_base) {
  267. case USDHC1_BASE_ADDR:
  268. gpio_request(GPIO_MMC_CD, "MMC_CD");
  269. gpio_direction_input(GPIO_MMC_CD);
  270. ret = !gpio_get_value(GPIO_MMC_CD);
  271. break;
  272. case USDHC2_BASE_ADDR:
  273. gpio_request(GPIO_MMC_CD, "SD_CD");
  274. gpio_direction_input(GPIO_SD_CD);
  275. ret = !gpio_get_value(GPIO_SD_CD);
  276. break;
  277. }
  278. return ret;
  279. }
  280. int board_mmc_init(bd_t *bis)
  281. {
  282. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  283. unsigned reg = readl(&psrc->sbmr1) >> 11;
  284. /*
  285. * Upon reading BOOT_CFG register the following map is done:
  286. * Bit 11 and 12 of BOOT_CFG register can determine the current
  287. * mmc port
  288. * 0x1 SD1
  289. * 0x2 SD2
  290. * 0x3 SD4
  291. */
  292. switch (reg & 0x3) {
  293. case 0x0:
  294. imx_iomux_v3_setup_multiple_pads(
  295. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  296. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  297. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  298. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  299. break;
  300. case 0x1:
  301. imx_iomux_v3_setup_multiple_pads(
  302. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  303. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  304. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  305. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  306. break;
  307. case 0x2:
  308. imx_iomux_v3_setup_multiple_pads(
  309. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  310. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  311. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  312. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  313. break;
  314. default:
  315. puts("MMC boot device not available");
  316. }
  317. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  318. }
  319. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  320. int board_phy_config(struct phy_device *phydev)
  321. {
  322. mx6_rgmii_rework(phydev);
  323. if (phydev->drv->config)
  324. phydev->drv->config(phydev);
  325. return 0;
  326. }
  327. int board_eth_init(bd_t *bis)
  328. {
  329. uint32_t base = IMX_FEC_BASE;
  330. struct mii_dev *bus = NULL;
  331. struct phy_device *phydev = NULL;
  332. int ret;
  333. setup_iomux_enet();
  334. #ifdef CONFIG_FEC_MXC
  335. bus = fec_get_miibus(base, -1);
  336. if (!bus)
  337. return 0;
  338. bus->reset = reset_enet_phy;
  339. /* scan PHY 4,5,6,7 */
  340. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  341. if (!phydev) {
  342. free(bus);
  343. puts("no PHY found\n");
  344. return 0;
  345. }
  346. printf("using PHY at %d\n", phydev->addr);
  347. ret = fec_probe(bis, -1, base, bus, phydev);
  348. if (ret) {
  349. printf("FEC MXC: %s:failed\n", __func__);
  350. free(phydev);
  351. free(bus);
  352. }
  353. #endif /* CONFIG_FEC_MXC */
  354. return 0;
  355. }
  356. static iomux_v3_cfg_t const pwr_intb_pads[] = {
  357. /*
  358. * the bootrom sets the iomux to vselect, potentially connecting
  359. * two outputs. Set this back to GPIO
  360. */
  361. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
  362. };
  363. #if defined(CONFIG_VIDEO_IPUV3)
  364. static iomux_v3_cfg_t const backlight_pads[] = {
  365. /* Backlight on RGB connector: J15 */
  366. MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  367. MUX_MODE_SION,
  368. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
  369. /* additional CPU pin on BKL_PWM, keep in tristate */
  370. MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
  371. /* Backlight PWM, used as GPIO in U-Boot */
  372. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  373. MUX_MODE_SION,
  374. #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
  375. /* buffer output enable 0: buffer enabled */
  376. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
  377. #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
  378. /* PSAVE# integrated VDAC */
  379. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  380. MUX_MODE_SION,
  381. #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
  382. };
  383. static iomux_v3_cfg_t const rgb_pads[] = {
  384. MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
  385. MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
  386. MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
  387. MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
  388. MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
  389. MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
  390. MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
  391. MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
  392. MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
  393. MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
  394. MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
  395. MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
  396. MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
  397. MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
  398. MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
  399. MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
  400. MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
  401. MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
  402. MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
  403. MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
  404. MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
  405. MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
  406. MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
  407. MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
  408. MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
  409. MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
  410. MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
  411. MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
  412. };
  413. static void do_enable_hdmi(struct display_info_t const *dev)
  414. {
  415. imx_enable_hdmi_phy();
  416. }
  417. static void enable_lvds(struct display_info_t const *dev)
  418. {
  419. struct iomuxc *iomux = (struct iomuxc *)
  420. IOMUXC_BASE_ADDR;
  421. u32 reg = readl(&iomux->gpr[2]);
  422. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  423. writel(reg, &iomux->gpr[2]);
  424. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  425. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  426. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  427. }
  428. static void enable_rgb(struct display_info_t const *dev)
  429. {
  430. imx_iomux_v3_setup_multiple_pads(
  431. rgb_pads,
  432. ARRAY_SIZE(rgb_pads));
  433. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  434. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  435. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  436. }
  437. static int detect_default(struct display_info_t const *dev)
  438. {
  439. (void) dev;
  440. return 1;
  441. }
  442. struct display_info_t const displays[] = {{
  443. .bus = -1,
  444. .addr = 0,
  445. .pixfmt = IPU_PIX_FMT_RGB24,
  446. .detect = detect_hdmi,
  447. .enable = do_enable_hdmi,
  448. .mode = {
  449. .name = "HDMI",
  450. .refresh = 60,
  451. .xres = 1024,
  452. .yres = 768,
  453. .pixclock = 15385,
  454. .left_margin = 220,
  455. .right_margin = 40,
  456. .upper_margin = 21,
  457. .lower_margin = 7,
  458. .hsync_len = 60,
  459. .vsync_len = 10,
  460. .sync = FB_SYNC_EXT,
  461. .vmode = FB_VMODE_NONINTERLACED
  462. } }, {
  463. .bus = -1,
  464. .addr = 0,
  465. .di = 1,
  466. .pixfmt = IPU_PIX_FMT_RGB24,
  467. .detect = detect_default,
  468. .enable = enable_rgb,
  469. .mode = {
  470. .name = "vga-rgb",
  471. .refresh = 60,
  472. .xres = 640,
  473. .yres = 480,
  474. .pixclock = 33000,
  475. .left_margin = 48,
  476. .right_margin = 16,
  477. .upper_margin = 31,
  478. .lower_margin = 11,
  479. .hsync_len = 96,
  480. .vsync_len = 2,
  481. .sync = 0,
  482. .vmode = FB_VMODE_NONINTERLACED
  483. } }, {
  484. .bus = -1,
  485. .addr = 0,
  486. .di = 1,
  487. .pixfmt = IPU_PIX_FMT_RGB24,
  488. .enable = enable_rgb,
  489. .mode = {
  490. .name = "wvga-rgb",
  491. .refresh = 60,
  492. .xres = 800,
  493. .yres = 480,
  494. .pixclock = 25000,
  495. .left_margin = 40,
  496. .right_margin = 88,
  497. .upper_margin = 33,
  498. .lower_margin = 10,
  499. .hsync_len = 128,
  500. .vsync_len = 2,
  501. .sync = 0,
  502. .vmode = FB_VMODE_NONINTERLACED
  503. } }, {
  504. .bus = -1,
  505. .addr = 0,
  506. .pixfmt = IPU_PIX_FMT_LVDS666,
  507. .enable = enable_lvds,
  508. .mode = {
  509. .name = "wsvga-lvds",
  510. .refresh = 60,
  511. .xres = 1024,
  512. .yres = 600,
  513. .pixclock = 15385,
  514. .left_margin = 220,
  515. .right_margin = 40,
  516. .upper_margin = 21,
  517. .lower_margin = 7,
  518. .hsync_len = 60,
  519. .vsync_len = 10,
  520. .sync = FB_SYNC_EXT,
  521. .vmode = FB_VMODE_NONINTERLACED
  522. } } };
  523. size_t display_count = ARRAY_SIZE(displays);
  524. static void setup_display(void)
  525. {
  526. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  527. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  528. int reg;
  529. enable_ipu_clock();
  530. imx_setup_hdmi();
  531. /* Turn on LDB0,IPU,IPU DI0 clocks */
  532. reg = __raw_readl(&mxc_ccm->CCGR3);
  533. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  534. writel(reg, &mxc_ccm->CCGR3);
  535. /* set LDB0, LDB1 clk select to 011/011 */
  536. reg = readl(&mxc_ccm->cs2cdr);
  537. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  538. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  539. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  540. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  541. writel(reg, &mxc_ccm->cs2cdr);
  542. reg = readl(&mxc_ccm->cscmr2);
  543. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  544. writel(reg, &mxc_ccm->cscmr2);
  545. reg = readl(&mxc_ccm->chsccdr);
  546. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  547. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  548. writel(reg, &mxc_ccm->chsccdr);
  549. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  550. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  551. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  552. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  553. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  554. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  555. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  556. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  557. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  558. writel(reg, &iomux->gpr[2]);
  559. reg = readl(&iomux->gpr[3]);
  560. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  561. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  562. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  563. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  564. writel(reg, &iomux->gpr[3]);
  565. /* backlight unconditionally on for now */
  566. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  567. ARRAY_SIZE(backlight_pads));
  568. /* use 0 for EDT 7", use 1 for LG fullHD panel */
  569. gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
  570. gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
  571. gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
  572. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  573. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  574. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  575. }
  576. /*
  577. * Backlight off before OS handover
  578. */
  579. void board_preboot_os(void)
  580. {
  581. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
  582. gpio_direction_output(RGB_BACKLIGHT_GP, 0);
  583. }
  584. #endif /* defined(CONFIG_VIDEO_IPUV3) */
  585. int board_early_init_f(void)
  586. {
  587. imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
  588. ARRAY_SIZE(pwr_intb_pads));
  589. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  590. setup_iomux_dte_uart();
  591. #else
  592. setup_iomux_dce_uart();
  593. #endif
  594. return 0;
  595. }
  596. /*
  597. * Do not overwrite the console
  598. * Use always serial for U-Boot console
  599. */
  600. int overwrite_console(void)
  601. {
  602. return 1;
  603. }
  604. int board_init(void)
  605. {
  606. /* address of boot parameters */
  607. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  608. #if defined(CONFIG_VIDEO_IPUV3)
  609. setup_display();
  610. #endif
  611. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  612. (void) pmic_init();
  613. #endif
  614. #ifdef CONFIG_SATA
  615. setup_sata();
  616. #endif
  617. setup_iomux_gpio();
  618. return 0;
  619. }
  620. #ifdef CONFIG_BOARD_LATE_INIT
  621. int board_late_init(void)
  622. {
  623. #if defined(CONFIG_REVISION_TAG) && \
  624. defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
  625. char env_str[256];
  626. u32 rev;
  627. rev = get_board_rev();
  628. snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
  629. env_set("board_rev", env_str);
  630. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  631. if ((rev & 0xfff0) == 0x0100) {
  632. char *fdt_env;
  633. /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
  634. setup_iomux_dce_uart();
  635. /* if using the default device tree, use version for V1.0 HW */
  636. fdt_env = env_get("fdt_file");
  637. if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
  638. env_set("fdt_file", FDT_FILE_V1_0);
  639. printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
  640. #ifndef CONFIG_ENV_IS_NOWHERE
  641. env_save();
  642. #endif
  643. }
  644. }
  645. #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
  646. #endif /* CONFIG_REVISION_TAG */
  647. #ifdef CONFIG_CMD_USB_SDP
  648. if (is_boot_from_usb()) {
  649. printf("Serial Downloader recovery mode, using sdp command\n");
  650. env_set("bootdelay", "0");
  651. env_set("bootcmd", "sdp 0");
  652. }
  653. #endif /* CONFIG_CMD_USB_SDP */
  654. return 0;
  655. }
  656. #endif /* CONFIG_BOARD_LATE_INIT */
  657. int checkboard(void)
  658. {
  659. char it[] = " IT";
  660. int minc, maxc;
  661. switch (get_cpu_temp_grade(&minc, &maxc)) {
  662. case TEMP_AUTOMOTIVE:
  663. case TEMP_INDUSTRIAL:
  664. break;
  665. case TEMP_EXTCOMMERCIAL:
  666. default:
  667. it[0] = 0;
  668. };
  669. printf("Model: Toradex Apalis iMX6 %s %s%s\n",
  670. is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
  671. (gd->ram_size == 0x80000000) ? "2GB" :
  672. (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
  673. return 0;
  674. }
  675. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  676. int ft_board_setup(void *blob, bd_t *bd)
  677. {
  678. return ft_common_board_setup(blob, bd);
  679. }
  680. #endif
  681. #ifdef CONFIG_CMD_BMODE
  682. static const struct boot_mode board_boot_modes[] = {
  683. /* 4-bit bus width */
  684. {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  685. {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  686. {NULL, 0},
  687. };
  688. #endif
  689. int misc_init_r(void)
  690. {
  691. #ifdef CONFIG_CMD_BMODE
  692. add_board_boot_modes(board_boot_modes);
  693. #endif
  694. return 0;
  695. }
  696. #ifdef CONFIG_LDO_BYPASS_CHECK
  697. /* TODO, use external pmic, for now always ldo_enable */
  698. void ldo_mode_set(int ldo_bypass)
  699. {
  700. return;
  701. }
  702. #endif
  703. #ifdef CONFIG_SPL_BUILD
  704. #include <spl.h>
  705. #include <linux/libfdt.h>
  706. #include "asm/arch/mx6q-ddr.h"
  707. #include "asm/arch/iomux.h"
  708. #include "asm/arch/crm_regs.h"
  709. static int mx6_com_dcd_table[] = {
  710. /* ddr-setup.cfg */
  711. MX6_IOM_DRAM_SDQS0, 0x00000030,
  712. MX6_IOM_DRAM_SDQS1, 0x00000030,
  713. MX6_IOM_DRAM_SDQS2, 0x00000030,
  714. MX6_IOM_DRAM_SDQS3, 0x00000030,
  715. MX6_IOM_DRAM_SDQS4, 0x00000030,
  716. MX6_IOM_DRAM_SDQS5, 0x00000030,
  717. MX6_IOM_DRAM_SDQS6, 0x00000030,
  718. MX6_IOM_DRAM_SDQS7, 0x00000030,
  719. MX6_IOM_GRP_B0DS, 0x00000030,
  720. MX6_IOM_GRP_B1DS, 0x00000030,
  721. MX6_IOM_GRP_B2DS, 0x00000030,
  722. MX6_IOM_GRP_B3DS, 0x00000030,
  723. MX6_IOM_GRP_B4DS, 0x00000030,
  724. MX6_IOM_GRP_B5DS, 0x00000030,
  725. MX6_IOM_GRP_B6DS, 0x00000030,
  726. MX6_IOM_GRP_B7DS, 0x00000030,
  727. MX6_IOM_GRP_ADDDS, 0x00000030,
  728. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  729. MX6_IOM_GRP_CTLDS, 0x00000030,
  730. MX6_IOM_DRAM_DQM0, 0x00020030,
  731. MX6_IOM_DRAM_DQM1, 0x00020030,
  732. MX6_IOM_DRAM_DQM2, 0x00020030,
  733. MX6_IOM_DRAM_DQM3, 0x00020030,
  734. MX6_IOM_DRAM_DQM4, 0x00020030,
  735. MX6_IOM_DRAM_DQM5, 0x00020030,
  736. MX6_IOM_DRAM_DQM6, 0x00020030,
  737. MX6_IOM_DRAM_DQM7, 0x00020030,
  738. MX6_IOM_DRAM_CAS, 0x00020030,
  739. MX6_IOM_DRAM_RAS, 0x00020030,
  740. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  741. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  742. MX6_IOM_DRAM_RESET, 0x00020030,
  743. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  744. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  745. MX6_IOM_DRAM_SDODT0, 0x00003030,
  746. MX6_IOM_DRAM_SDODT1, 0x00003030,
  747. /* (differential input) */
  748. MX6_IOM_DDRMODE_CTL, 0x00020000,
  749. /* (differential input) */
  750. MX6_IOM_GRP_DDRMODE, 0x00020000,
  751. /* disable ddr pullups */
  752. MX6_IOM_GRP_DDRPKE, 0x00000000,
  753. MX6_IOM_DRAM_SDBA2, 0x00000000,
  754. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  755. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  756. /* Read data DQ Byte0-3 delay */
  757. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  758. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  759. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  760. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  761. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  762. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  763. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  764. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  765. /*
  766. * MDMISC mirroring interleaved (row/bank/col)
  767. */
  768. MX6_MMDC_P0_MDMISC, 0x00081740,
  769. /*
  770. * MDSCR con_req
  771. */
  772. MX6_MMDC_P0_MDSCR, 0x00008000,
  773. /* 1066mhz_4x128mx16.cfg */
  774. MX6_MMDC_P0_MDPDC, 0x00020036,
  775. MX6_MMDC_P0_MDCFG0, 0x555A7954,
  776. MX6_MMDC_P0_MDCFG1, 0xDB328F64,
  777. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  778. MX6_MMDC_P0_MDRWD, 0x000026D2,
  779. MX6_MMDC_P0_MDOR, 0x005A1023,
  780. MX6_MMDC_P0_MDOTC, 0x09555050,
  781. MX6_MMDC_P0_MDPDC, 0x00025576,
  782. MX6_MMDC_P0_MDASP, 0x00000027,
  783. MX6_MMDC_P0_MDCTL, 0x831A0000,
  784. MX6_MMDC_P0_MDSCR, 0x04088032,
  785. MX6_MMDC_P0_MDSCR, 0x00008033,
  786. MX6_MMDC_P0_MDSCR, 0x00428031,
  787. MX6_MMDC_P0_MDSCR, 0x19308030,
  788. MX6_MMDC_P0_MDSCR, 0x04008040,
  789. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  790. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  791. MX6_MMDC_P0_MDREF, 0x00005800,
  792. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  793. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  794. MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
  795. MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
  796. MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
  797. MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
  798. MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
  799. MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
  800. MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
  801. MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
  802. MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
  803. MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
  804. MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
  805. MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
  806. MX6_MMDC_P0_MPMUR0, 0x00000800,
  807. MX6_MMDC_P1_MPMUR0, 0x00000800,
  808. MX6_MMDC_P0_MDSCR, 0x00000000,
  809. MX6_MMDC_P0_MAPSR, 0x00011006,
  810. };
  811. static int mx6_it_dcd_table[] = {
  812. /* ddr-setup.cfg */
  813. MX6_IOM_DRAM_SDQS0, 0x00000030,
  814. MX6_IOM_DRAM_SDQS1, 0x00000030,
  815. MX6_IOM_DRAM_SDQS2, 0x00000030,
  816. MX6_IOM_DRAM_SDQS3, 0x00000030,
  817. MX6_IOM_DRAM_SDQS4, 0x00000030,
  818. MX6_IOM_DRAM_SDQS5, 0x00000030,
  819. MX6_IOM_DRAM_SDQS6, 0x00000030,
  820. MX6_IOM_DRAM_SDQS7, 0x00000030,
  821. MX6_IOM_GRP_B0DS, 0x00000030,
  822. MX6_IOM_GRP_B1DS, 0x00000030,
  823. MX6_IOM_GRP_B2DS, 0x00000030,
  824. MX6_IOM_GRP_B3DS, 0x00000030,
  825. MX6_IOM_GRP_B4DS, 0x00000030,
  826. MX6_IOM_GRP_B5DS, 0x00000030,
  827. MX6_IOM_GRP_B6DS, 0x00000030,
  828. MX6_IOM_GRP_B7DS, 0x00000030,
  829. MX6_IOM_GRP_ADDDS, 0x00000030,
  830. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  831. MX6_IOM_GRP_CTLDS, 0x00000030,
  832. MX6_IOM_DRAM_DQM0, 0x00020030,
  833. MX6_IOM_DRAM_DQM1, 0x00020030,
  834. MX6_IOM_DRAM_DQM2, 0x00020030,
  835. MX6_IOM_DRAM_DQM3, 0x00020030,
  836. MX6_IOM_DRAM_DQM4, 0x00020030,
  837. MX6_IOM_DRAM_DQM5, 0x00020030,
  838. MX6_IOM_DRAM_DQM6, 0x00020030,
  839. MX6_IOM_DRAM_DQM7, 0x00020030,
  840. MX6_IOM_DRAM_CAS, 0x00020030,
  841. MX6_IOM_DRAM_RAS, 0x00020030,
  842. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  843. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  844. MX6_IOM_DRAM_RESET, 0x00020030,
  845. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  846. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  847. MX6_IOM_DRAM_SDODT0, 0x00003030,
  848. MX6_IOM_DRAM_SDODT1, 0x00003030,
  849. /* (differential input) */
  850. MX6_IOM_DDRMODE_CTL, 0x00020000,
  851. /* (differential input) */
  852. MX6_IOM_GRP_DDRMODE, 0x00020000,
  853. /* disable ddr pullups */
  854. MX6_IOM_GRP_DDRPKE, 0x00000000,
  855. MX6_IOM_DRAM_SDBA2, 0x00000000,
  856. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  857. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  858. /* Read data DQ Byte0-3 delay */
  859. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  860. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  861. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  862. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  863. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  864. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  865. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  866. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  867. /*
  868. * MDMISC mirroring interleaved (row/bank/col)
  869. */
  870. MX6_MMDC_P0_MDMISC, 0x00081740,
  871. /*
  872. * MDSCR con_req
  873. */
  874. MX6_MMDC_P0_MDSCR, 0x00008000,
  875. /* 1066mhz_4x256mx16.cfg */
  876. MX6_MMDC_P0_MDPDC, 0x00020036,
  877. MX6_MMDC_P0_MDCFG0, 0x898E78f5,
  878. MX6_MMDC_P0_MDCFG1, 0xff328f64,
  879. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  880. MX6_MMDC_P0_MDRWD, 0x000026D2,
  881. MX6_MMDC_P0_MDOR, 0x008E1023,
  882. MX6_MMDC_P0_MDOTC, 0x09444040,
  883. MX6_MMDC_P0_MDPDC, 0x00025576,
  884. MX6_MMDC_P0_MDASP, 0x00000047,
  885. MX6_MMDC_P0_MDCTL, 0x841A0000,
  886. MX6_MMDC_P0_MDSCR, 0x02888032,
  887. MX6_MMDC_P0_MDSCR, 0x00008033,
  888. MX6_MMDC_P0_MDSCR, 0x00048031,
  889. MX6_MMDC_P0_MDSCR, 0x19408030,
  890. MX6_MMDC_P0_MDSCR, 0x04008040,
  891. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  892. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  893. MX6_MMDC_P0_MDREF, 0x00007800,
  894. MX6_MMDC_P0_MPODTCTRL, 0x00022227,
  895. MX6_MMDC_P1_MPODTCTRL, 0x00022227,
  896. MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
  897. MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
  898. MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
  899. MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
  900. MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
  901. MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
  902. MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
  903. MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
  904. MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
  905. MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
  906. MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
  907. MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
  908. MX6_MMDC_P0_MPMUR0, 0x00000800,
  909. MX6_MMDC_P1_MPMUR0, 0x00000800,
  910. MX6_MMDC_P0_MDSCR, 0x00000000,
  911. MX6_MMDC_P0_MAPSR, 0x00011006,
  912. };
  913. static void ccgr_init(void)
  914. {
  915. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  916. writel(0x00C03F3F, &ccm->CCGR0);
  917. writel(0x0030FC03, &ccm->CCGR1);
  918. writel(0x0FFFFFF3, &ccm->CCGR2);
  919. writel(0x3FF0300F, &ccm->CCGR3);
  920. writel(0x00FFF300, &ccm->CCGR4);
  921. writel(0x0F0000F3, &ccm->CCGR5);
  922. writel(0x000003FF, &ccm->CCGR6);
  923. /*
  924. * Setup CCM_CCOSR register as follows:
  925. *
  926. * cko1_en = 1 --> CKO1 enabled
  927. * cko1_div = 111 --> divide by 8
  928. * cko1_sel = 1011 --> ahb_clk_root
  929. *
  930. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  931. */
  932. writel(0x000000FB, &ccm->ccosr);
  933. }
  934. static void ddr_init(int *table, int size)
  935. {
  936. int i;
  937. for (i = 0; i < size / 2 ; i++)
  938. writel(table[2 * i + 1], table[2 * i]);
  939. }
  940. static void spl_dram_init(void)
  941. {
  942. int minc, maxc;
  943. switch (get_cpu_temp_grade(&minc, &maxc)) {
  944. case TEMP_COMMERCIAL:
  945. case TEMP_EXTCOMMERCIAL:
  946. puts("Commercial temperature grade DDR3 timings.\n");
  947. ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
  948. break;
  949. case TEMP_INDUSTRIAL:
  950. case TEMP_AUTOMOTIVE:
  951. default:
  952. puts("Industrial temperature grade DDR3 timings.\n");
  953. ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
  954. break;
  955. };
  956. udelay(100);
  957. }
  958. void board_init_f(ulong dummy)
  959. {
  960. /* setup AIPS and disable watchdog */
  961. arch_cpu_init();
  962. ccgr_init();
  963. gpr_init();
  964. /* iomux */
  965. board_early_init_f();
  966. /* setup GP timer */
  967. timer_init();
  968. /* UART clocks enabled and gd valid - init serial console */
  969. preloader_console_init();
  970. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  971. /* Make sure we use dte mode */
  972. setup_dtemode_uart();
  973. #endif
  974. /* DDR initialization */
  975. spl_dram_init();
  976. /* Clear the BSS. */
  977. memset(__bss_start, 0, __bss_end - __bss_start);
  978. /* load/boot image from boot device */
  979. board_init_r(NULL, 0);
  980. }
  981. void reset_cpu(ulong addr)
  982. {
  983. }
  984. #endif /* CONFIG_SPL_BUILD */
  985. static struct mxc_serial_platdata mxc_serial_plat = {
  986. .reg = (struct mxc_uart *)UART1_BASE,
  987. .use_dte = true,
  988. };
  989. U_BOOT_DEVICE(mxc_serial) = {
  990. .name = "serial_mxc",
  991. .platdata = &mxc_serial_plat,
  992. };