devkit8000.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2008
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Sunil Kumar <sunilsaini05@gmail.com>
  8. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  9. *
  10. * (C) Copyright 2009
  11. * Frederik Kriewitz <frederik@kriewitz.eu>
  12. *
  13. * Derived from Beagle Board and 3430 SDP code by
  14. * Richard Woodruff <r-woodruff2@ti.com>
  15. * Syed Mohammed Khasim <khasim@ti.com>
  16. *
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <env.h>
  21. #include <ns16550.h>
  22. #include <twl4030.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/arch/mux.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/mem.h>
  28. #include <asm/mach-types.h>
  29. #include "devkit8000.h"
  30. #include <asm/gpio.h>
  31. #ifdef CONFIG_DRIVER_DM9000
  32. #include <net.h>
  33. #include <netdev.h>
  34. #endif
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static u32 gpmc_net_config[GPMC_MAX_REG] = {
  37. NET_GPMC_CONFIG1,
  38. NET_GPMC_CONFIG2,
  39. NET_GPMC_CONFIG3,
  40. NET_GPMC_CONFIG4,
  41. NET_GPMC_CONFIG5,
  42. NET_GPMC_CONFIG6,
  43. 0
  44. };
  45. static const struct ns16550_platdata devkit8000_serial = {
  46. .base = OMAP34XX_UART3,
  47. .reg_shift = 2,
  48. .clock = V_NS16550_CLK,
  49. .fcr = UART_FCR_DEFVAL,
  50. };
  51. U_BOOT_DEVICE(devkit8000_uart) = {
  52. "ns16550_serial",
  53. &devkit8000_serial
  54. };
  55. /*
  56. * Routine: board_init
  57. * Description: Early hardware init.
  58. */
  59. int board_init(void)
  60. {
  61. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  62. /* board id for Linux */
  63. gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
  64. /* boot param addr */
  65. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  66. return 0;
  67. }
  68. /* Configure GPMC registers for DM9000 */
  69. static void gpmc_dm9000_config(void)
  70. {
  71. enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
  72. CONFIG_DM9000_BASE, GPMC_SIZE_16M);
  73. }
  74. /*
  75. * Routine: misc_init_r
  76. * Description: Configure board specific parts
  77. */
  78. int misc_init_r(void)
  79. {
  80. struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  81. #ifdef CONFIG_DRIVER_DM9000
  82. uchar enetaddr[6];
  83. u32 die_id_0;
  84. #endif
  85. twl4030_power_init();
  86. #ifdef CONFIG_TWL4030_LED
  87. twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
  88. #endif
  89. #ifdef CONFIG_DRIVER_DM9000
  90. /* Configure GPMC registers for DM9000 */
  91. enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
  92. CONFIG_DM9000_BASE, GPMC_SIZE_16M);
  93. /* Use OMAP DIE_ID as MAC address */
  94. if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
  95. printf("ethaddr not set, using Die ID\n");
  96. die_id_0 = readl(&id_base->die_id_0);
  97. enetaddr[0] = 0x02; /* locally administered */
  98. enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
  99. enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
  100. enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
  101. enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
  102. enetaddr[5] = (die_id_0 & 0x000000ff);
  103. eth_env_set_enetaddr("ethaddr", enetaddr);
  104. }
  105. #endif
  106. omap_die_id_display();
  107. return 0;
  108. }
  109. /*
  110. * Routine: set_muxconf_regs
  111. * Description: Setting up the configuration Mux registers specific to the
  112. * hardware. Many pins need to be moved from protect to primary
  113. * mode.
  114. */
  115. void set_muxconf_regs(void)
  116. {
  117. MUX_DEVKIT8000();
  118. }
  119. #if defined(CONFIG_MMC)
  120. int board_mmc_init(bd_t *bis)
  121. {
  122. return omap_mmc_init(0, 0, 0, -1, -1);
  123. }
  124. #endif
  125. #if defined(CONFIG_MMC)
  126. void board_mmc_power_init(void)
  127. {
  128. twl4030_power_mmc_init(0);
  129. }
  130. #endif
  131. #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
  132. /*
  133. * Routine: board_eth_init
  134. * Description: Setting up the Ethernet hardware.
  135. */
  136. int board_eth_init(bd_t *bis)
  137. {
  138. return dm9000_initialize(bis);
  139. }
  140. #endif
  141. #ifdef CONFIG_SPL_OS_BOOT
  142. /*
  143. * Do board specific preparation before SPL
  144. * Linux boot
  145. */
  146. void spl_board_prepare_for_linux(void)
  147. {
  148. gpmc_dm9000_config();
  149. }
  150. /*
  151. * devkit8000 specific implementation of spl_start_uboot()
  152. *
  153. * RETURN
  154. * 0 if the button is not pressed
  155. * 1 if the button is pressed
  156. */
  157. int spl_start_uboot(void)
  158. {
  159. int val = 0;
  160. if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
  161. gpio_direction_input(SPL_OS_BOOT_KEY);
  162. val = gpio_get_value(SPL_OS_BOOT_KEY);
  163. gpio_free(SPL_OS_BOOT_KEY);
  164. }
  165. return !val;
  166. }
  167. #endif
  168. /*
  169. * Routine: get_board_mem_timings
  170. * Description: If we use SPL then there is no x-loader nor config header
  171. * so we have to setup the DDR timings ourself on the first bank. This
  172. * provides the timing values back to the function that configures
  173. * the memory. We have either one or two banks of 128MB DDR.
  174. */
  175. void get_board_mem_timings(struct board_sdrc_timings *timings)
  176. {
  177. /* General SDRC config */
  178. timings->mcfg = MICRON_V_MCFG_165(128 << 20);
  179. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  180. /* AC timings */
  181. timings->ctrla = MICRON_V_ACTIMA_165;
  182. timings->ctrlb = MICRON_V_ACTIMB_165;
  183. timings->mr = MICRON_V_MR_165;
  184. }