evm.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * evm.c
  4. *
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Antoine Tenart, <atenart@adeneo-embedded.com>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <spl.h>
  11. #include <asm/cache.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/ddr_defs.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/mmc_host_def.h>
  19. #include <asm/arch/mem.h>
  20. #include <asm/arch/mux.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int board_init(void)
  23. {
  24. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  25. #if defined(CONFIG_NAND)
  26. gpmc_init();
  27. #endif
  28. return 0;
  29. }
  30. int board_eth_init(bd_t *bis)
  31. {
  32. uint8_t mac_addr[6];
  33. uint32_t mac_hi, mac_lo;
  34. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  35. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  36. printf("<ethaddr> not set. Reading from E-fuse\n");
  37. /* try reading mac address from efuse */
  38. mac_lo = readl(&cdev->macid0l);
  39. mac_hi = readl(&cdev->macid0h);
  40. mac_addr[0] = mac_hi & 0xFF;
  41. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  42. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  43. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  44. mac_addr[4] = mac_lo & 0xFF;
  45. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  46. if (is_valid_ethaddr(mac_addr))
  47. eth_env_set_enetaddr("ethaddr", mac_addr);
  48. else
  49. printf("Unable to read MAC address. Set <ethaddr>\n");
  50. }
  51. return 0;
  52. }
  53. #ifdef CONFIG_SPL_BUILD
  54. static struct module_pin_mux mmc_pin_mux[] = {
  55. { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  56. { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  57. { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  58. { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  59. { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  60. { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  61. { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  62. { -1 },
  63. };
  64. void set_uart_mux_conf(void) {}
  65. void set_mux_conf_regs(void)
  66. {
  67. configure_module_pin_mux(mmc_pin_mux);
  68. }
  69. /*
  70. * EMIF Paramters. Refer the EMIF register documentation and the
  71. * memory datasheet for details. This is for 796 MHz.
  72. */
  73. #define EMIF_TIM1 0x1779C9FE
  74. #define EMIF_TIM2 0x50608074
  75. #define EMIF_TIM3 0x009F857F
  76. #define EMIF_SDREF 0x10001841
  77. #define EMIF_SDCFG 0x62A73832
  78. #define EMIF_PHYCFG 0x00000110
  79. static const struct emif_regs ddr3_emif_regs = {
  80. .sdram_config = EMIF_SDCFG,
  81. .ref_ctrl = EMIF_SDREF,
  82. .sdram_tim1 = EMIF_TIM1,
  83. .sdram_tim2 = EMIF_TIM2,
  84. .sdram_tim3 = EMIF_TIM3,
  85. .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
  86. };
  87. static const struct cmd_control ddr3_ctrl = {
  88. .cmd0csratio = 0x100,
  89. .cmd0iclkout = 0x001,
  90. .cmd1csratio = 0x100,
  91. .cmd1iclkout = 0x001,
  92. .cmd2csratio = 0x100,
  93. .cmd2iclkout = 0x001,
  94. };
  95. /* These values are obtained from the CCS app */
  96. #define RD_DQS_GATE (0x1B3)
  97. #define RD_DQS (0x35)
  98. #define WR_DQS (0x93)
  99. static struct ddr_data ddr3_data = {
  100. .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
  101. .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
  102. .datawiratio0 = ((0x20<<10) | 0x20<<0),
  103. .datagiratio0 = ((0x20<<10) | 0x20<<0),
  104. .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
  105. .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
  106. };
  107. static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
  108. .dmm_lisa_map_0 = 0x00000000,
  109. .dmm_lisa_map_1 = 0x00000000,
  110. .dmm_lisa_map_2 = 0x80640300,
  111. .dmm_lisa_map_3 = 0xC0640320,
  112. };
  113. void sdram_init(void)
  114. {
  115. /*
  116. * Pass in our DDR3 config information and that we have 2 EMIFs to
  117. * configure.
  118. */
  119. config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
  120. &evm_lisa_map_regs, 2);
  121. }
  122. #endif /* CONFIG_SPL_BUILD */