board.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. * Author: Felipe Balbi <balbi@ti.com>
  6. *
  7. * Based on board/ti/dra7xx/evm.c
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <palmas.h>
  12. #include <sata.h>
  13. #include <usb.h>
  14. #include <asm/omap_common.h>
  15. #include <asm/omap_sec_common.h>
  16. #include <asm/emif.h>
  17. #include <asm/gpio.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/dra7xx_iodelay.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/mmc_host_def.h>
  23. #include <asm/arch/sata.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/omap.h>
  26. #include <usb.h>
  27. #include <linux/usb/gadget.h>
  28. #include <dwc3-uboot.h>
  29. #include <dwc3-omap-uboot.h>
  30. #include <ti-usb-phy-uboot.h>
  31. #include <mmc.h>
  32. #include "../common/board_detect.h"
  33. #include "mux_data.h"
  34. #define board_is_x15() board_ti_is("BBRDX15_")
  35. #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
  36. !strncmp("B.10", board_ti_get_rev(), 3))
  37. #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
  38. !strncmp("C.00", board_ti_get_rev(), 3))
  39. #define board_is_am572x_evm() board_ti_is("AM572PM_")
  40. #define board_is_am572x_evm_reva3() \
  41. (board_ti_is("AM572PM_") && \
  42. !strncmp("A.30", board_ti_get_rev(), 3))
  43. #define board_is_am574x_idk() board_ti_is("AM574IDK")
  44. #define board_is_am572x_idk() board_ti_is("AM572IDK")
  45. #define board_is_am571x_idk() board_ti_is("AM571IDK")
  46. #ifdef CONFIG_DRIVER_TI_CPSW
  47. #include <cpsw.h>
  48. #endif
  49. DECLARE_GLOBAL_DATA_PTR;
  50. #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
  51. /* GPIO 7_11 */
  52. #define GPIO_DDR_VTT_EN 203
  53. /* Touch screen controller to identify the LCD */
  54. #define OSD_TS_FT_BUS_ADDRESS 0
  55. #define OSD_TS_FT_CHIP_ADDRESS 0x38
  56. #define OSD_TS_FT_REG_ID 0xA3
  57. /*
  58. * Touchscreen IDs for various OSD panels
  59. * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  60. */
  61. /* Used on newer osd101t2587 Panels */
  62. #define OSD_TS_FT_ID_5x46 0x54
  63. /* Used on older osd101t2045 Panels */
  64. #define OSD_TS_FT_ID_5606 0x08
  65. #define SYSINFO_BOARD_NAME_MAX_LEN 45
  66. #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
  67. #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
  68. const struct omap_sysinfo sysinfo = {
  69. "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  70. };
  71. static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  72. .dmm_lisa_map_3 = 0x80740300,
  73. .is_ma_present = 0x1
  74. };
  75. static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  76. .dmm_lisa_map_3 = 0x80640100,
  77. .is_ma_present = 0x1
  78. };
  79. static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  80. .dmm_lisa_map_2 = 0xc0600200,
  81. .dmm_lisa_map_3 = 0x80600100,
  82. .is_ma_present = 0x1
  83. };
  84. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  85. {
  86. if (board_is_am571x_idk())
  87. *dmm_lisa_regs = &am571x_idk_lisa_regs;
  88. else if (board_is_am574x_idk())
  89. *dmm_lisa_regs = &am574x_idk_lisa_regs;
  90. else
  91. *dmm_lisa_regs = &beagle_x15_lisa_regs;
  92. }
  93. static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  94. .sdram_config_init = 0x61851b32,
  95. .sdram_config = 0x61851b32,
  96. .sdram_config2 = 0x08000000,
  97. .ref_ctrl = 0x000040F1,
  98. .ref_ctrl_final = 0x00001035,
  99. .sdram_tim1 = 0xcccf36ab,
  100. .sdram_tim2 = 0x308f7fda,
  101. .sdram_tim3 = 0x409f88a8,
  102. .read_idle_ctrl = 0x00050000,
  103. .zq_config = 0x5007190b,
  104. .temp_alert_config = 0x00000000,
  105. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  106. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  107. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  108. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  109. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  110. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  111. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  112. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  113. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  114. .emif_rd_wr_lvl_ctl = 0x00000000,
  115. .emif_rd_wr_exec_thresh = 0x00000305
  116. };
  117. /* Ext phy ctrl regs 1-35 */
  118. static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  119. 0x10040100,
  120. 0x00910091,
  121. 0x00950095,
  122. 0x009B009B,
  123. 0x009E009E,
  124. 0x00980098,
  125. 0x00340034,
  126. 0x00350035,
  127. 0x00340034,
  128. 0x00310031,
  129. 0x00340034,
  130. 0x007F007F,
  131. 0x007F007F,
  132. 0x007F007F,
  133. 0x007F007F,
  134. 0x007F007F,
  135. 0x00480048,
  136. 0x004A004A,
  137. 0x00520052,
  138. 0x00550055,
  139. 0x00500050,
  140. 0x00000000,
  141. 0x00600020,
  142. 0x40011080,
  143. 0x08102040,
  144. 0x0,
  145. 0x0,
  146. 0x0,
  147. 0x0,
  148. 0x0,
  149. 0x0,
  150. 0x0,
  151. 0x0,
  152. 0x0,
  153. 0x0
  154. };
  155. static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  156. .sdram_config_init = 0x61851b32,
  157. .sdram_config = 0x61851b32,
  158. .sdram_config2 = 0x08000000,
  159. .ref_ctrl = 0x000040F1,
  160. .ref_ctrl_final = 0x00001035,
  161. .sdram_tim1 = 0xcccf36b3,
  162. .sdram_tim2 = 0x308f7fda,
  163. .sdram_tim3 = 0x407f88a8,
  164. .read_idle_ctrl = 0x00050000,
  165. .zq_config = 0x5007190b,
  166. .temp_alert_config = 0x00000000,
  167. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  168. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  169. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  170. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  171. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  172. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  173. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  174. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  175. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  176. .emif_rd_wr_lvl_ctl = 0x00000000,
  177. .emif_rd_wr_exec_thresh = 0x00000305
  178. };
  179. static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  180. 0x10040100,
  181. 0x00910091,
  182. 0x00950095,
  183. 0x009B009B,
  184. 0x009E009E,
  185. 0x00980098,
  186. 0x00340034,
  187. 0x00350035,
  188. 0x00340034,
  189. 0x00310031,
  190. 0x00340034,
  191. 0x007F007F,
  192. 0x007F007F,
  193. 0x007F007F,
  194. 0x007F007F,
  195. 0x007F007F,
  196. 0x00480048,
  197. 0x004A004A,
  198. 0x00520052,
  199. 0x00550055,
  200. 0x00500050,
  201. 0x00000000,
  202. 0x00600020,
  203. 0x40011080,
  204. 0x08102040,
  205. 0x0,
  206. 0x0,
  207. 0x0,
  208. 0x0,
  209. 0x0,
  210. 0x0,
  211. 0x0,
  212. 0x0,
  213. 0x0,
  214. 0x0
  215. };
  216. static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
  217. .sdram_config_init = 0x61863332,
  218. .sdram_config = 0x61863332,
  219. .sdram_config2 = 0x08000000,
  220. .ref_ctrl = 0x0000514d,
  221. .ref_ctrl_final = 0x0000144a,
  222. .sdram_tim1 = 0xd333887c,
  223. .sdram_tim2 = 0x30b37fe3,
  224. .sdram_tim3 = 0x409f8ad8,
  225. .read_idle_ctrl = 0x00050000,
  226. .zq_config = 0x5007190b,
  227. .temp_alert_config = 0x00000000,
  228. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  229. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  230. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  231. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  232. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  233. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  234. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  235. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  236. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  237. .emif_rd_wr_lvl_ctl = 0x00000000,
  238. .emif_rd_wr_exec_thresh = 0x00000305
  239. };
  240. static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
  241. .sdram_config_init = 0x61863332,
  242. .sdram_config = 0x61863332,
  243. .sdram_config2 = 0x08000000,
  244. .ref_ctrl = 0x0000514d,
  245. .ref_ctrl_final = 0x0000144a,
  246. .sdram_tim1 = 0xd333887c,
  247. .sdram_tim2 = 0x30b37fe3,
  248. .sdram_tim3 = 0x409f8ad8,
  249. .read_idle_ctrl = 0x00050000,
  250. .zq_config = 0x5007190b,
  251. .temp_alert_config = 0x00000000,
  252. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  253. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  254. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  255. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  256. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  257. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  258. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  259. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  260. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  261. .emif_rd_wr_lvl_ctl = 0x00000000,
  262. .emif_rd_wr_exec_thresh = 0x00000305,
  263. .emif_ecc_ctrl_reg = 0xD0000001,
  264. .emif_ecc_address_range_1 = 0x3FFF0000,
  265. .emif_ecc_address_range_2 = 0x00000000
  266. };
  267. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  268. {
  269. switch (emif_nr) {
  270. case 1:
  271. if (board_is_am571x_idk())
  272. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  273. else if (board_is_am574x_idk())
  274. *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
  275. else
  276. *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  277. break;
  278. case 2:
  279. if (board_is_am574x_idk())
  280. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  281. else
  282. *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  283. break;
  284. }
  285. }
  286. void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  287. {
  288. switch (emif_nr) {
  289. case 1:
  290. *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  291. *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  292. break;
  293. case 2:
  294. *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  295. *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  296. break;
  297. }
  298. }
  299. struct vcores_data beagle_x15_volts = {
  300. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  301. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  302. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  303. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  304. .mpu.pmic = &tps659038,
  305. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  306. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  307. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  308. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  309. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  310. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  311. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  312. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  313. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  314. .eve.pmic = &tps659038,
  315. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  316. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  317. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  318. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  319. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  320. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  321. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  322. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  323. .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  324. .gpu.pmic = &tps659038,
  325. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  326. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  327. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  328. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  329. .core.addr = TPS659038_REG_ADDR_SMPS6,
  330. .core.pmic = &tps659038,
  331. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  332. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  333. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  334. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  335. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  336. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  337. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  338. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  339. .iva.pmic = &tps659038,
  340. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  341. };
  342. struct vcores_data am572x_idk_volts = {
  343. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  344. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  345. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  346. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  347. .mpu.pmic = &tps659038,
  348. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  349. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  350. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  351. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  352. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  353. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  354. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  355. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  356. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  357. .eve.pmic = &tps659038,
  358. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  359. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  360. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  361. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  362. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  363. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  364. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  365. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  366. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  367. .gpu.pmic = &tps659038,
  368. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  369. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  370. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  371. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  372. .core.addr = TPS659038_REG_ADDR_SMPS7,
  373. .core.pmic = &tps659038,
  374. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  375. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  376. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  377. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  378. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  379. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  380. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  381. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  382. .iva.pmic = &tps659038,
  383. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  384. };
  385. struct vcores_data am571x_idk_volts = {
  386. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  387. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  388. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  389. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  390. .mpu.pmic = &tps659038,
  391. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  392. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  393. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  394. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  395. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  396. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  397. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  398. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  399. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  400. .eve.pmic = &tps659038,
  401. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  402. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  403. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  404. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  405. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  406. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  407. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  408. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  409. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  410. .gpu.pmic = &tps659038,
  411. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  412. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  413. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  414. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  415. .core.addr = TPS659038_REG_ADDR_SMPS7,
  416. .core.pmic = &tps659038,
  417. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  418. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  419. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  420. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  421. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  422. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  423. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  424. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  425. .iva.pmic = &tps659038,
  426. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  427. };
  428. int get_voltrail_opp(int rail_offset)
  429. {
  430. int opp;
  431. switch (rail_offset) {
  432. case VOLT_MPU:
  433. opp = DRA7_MPU_OPP;
  434. break;
  435. case VOLT_CORE:
  436. opp = DRA7_CORE_OPP;
  437. break;
  438. case VOLT_GPU:
  439. opp = DRA7_GPU_OPP;
  440. break;
  441. case VOLT_EVE:
  442. opp = DRA7_DSPEVE_OPP;
  443. break;
  444. case VOLT_IVA:
  445. opp = DRA7_IVA_OPP;
  446. break;
  447. default:
  448. opp = OPP_NOM;
  449. }
  450. return opp;
  451. }
  452. #ifdef CONFIG_SPL_BUILD
  453. /* No env to setup for SPL */
  454. static inline void setup_board_eeprom_env(void) { }
  455. /* Override function to read eeprom information */
  456. void do_board_detect(void)
  457. {
  458. int rc;
  459. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  460. CONFIG_EEPROM_CHIP_ADDRESS);
  461. if (rc)
  462. printf("ti_i2c_eeprom_init failed %d\n", rc);
  463. }
  464. #else /* CONFIG_SPL_BUILD */
  465. /* Override function to read eeprom information: actual i2c read done by SPL*/
  466. void do_board_detect(void)
  467. {
  468. char *bname = NULL;
  469. int rc;
  470. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  471. CONFIG_EEPROM_CHIP_ADDRESS);
  472. if (rc)
  473. printf("ti_i2c_eeprom_init failed %d\n", rc);
  474. if (board_is_x15())
  475. bname = "BeagleBoard X15";
  476. else if (board_is_am572x_evm())
  477. bname = "AM572x EVM";
  478. else if (board_is_am574x_idk())
  479. bname = "AM574x IDK";
  480. else if (board_is_am572x_idk())
  481. bname = "AM572x IDK";
  482. else if (board_is_am571x_idk())
  483. bname = "AM571x IDK";
  484. if (bname)
  485. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  486. "Board: %s REV %s\n", bname, board_ti_get_rev());
  487. }
  488. static void setup_board_eeprom_env(void)
  489. {
  490. char *name = "beagle_x15";
  491. int rc;
  492. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  493. CONFIG_EEPROM_CHIP_ADDRESS);
  494. if (rc)
  495. goto invalid_eeprom;
  496. if (board_is_x15()) {
  497. if (board_is_x15_revb1())
  498. name = "beagle_x15_revb1";
  499. else if (board_is_x15_revc())
  500. name = "beagle_x15_revc";
  501. else
  502. name = "beagle_x15";
  503. } else if (board_is_am572x_evm()) {
  504. if (board_is_am572x_evm_reva3())
  505. name = "am57xx_evm_reva3";
  506. else
  507. name = "am57xx_evm";
  508. } else if (board_is_am574x_idk()) {
  509. name = "am574x_idk";
  510. } else if (board_is_am572x_idk()) {
  511. name = "am572x_idk";
  512. } else if (board_is_am571x_idk()) {
  513. name = "am571x_idk";
  514. } else {
  515. printf("Unidentified board claims %s in eeprom header\n",
  516. board_ti_get_name());
  517. }
  518. invalid_eeprom:
  519. set_board_info_env(name);
  520. }
  521. #endif /* CONFIG_SPL_BUILD */
  522. void vcores_init(void)
  523. {
  524. if (board_is_am572x_idk() || board_is_am574x_idk())
  525. *omap_vcores = &am572x_idk_volts;
  526. else if (board_is_am571x_idk())
  527. *omap_vcores = &am571x_idk_volts;
  528. else
  529. *omap_vcores = &beagle_x15_volts;
  530. }
  531. void hw_data_init(void)
  532. {
  533. *prcm = &dra7xx_prcm;
  534. if (is_dra72x())
  535. *dplls_data = &dra72x_dplls;
  536. else if (is_dra76x())
  537. *dplls_data = &dra76x_dplls;
  538. else
  539. *dplls_data = &dra7xx_dplls;
  540. *ctrl = &dra7xx_ctrl;
  541. }
  542. bool am571x_idk_needs_lcd(void)
  543. {
  544. bool needs_lcd;
  545. gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
  546. if (gpio_get_value(GPIO_ETH_LCD))
  547. needs_lcd = false;
  548. else
  549. needs_lcd = true;
  550. gpio_free(GPIO_ETH_LCD);
  551. return needs_lcd;
  552. }
  553. int board_init(void)
  554. {
  555. gpmc_init();
  556. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  557. return 0;
  558. }
  559. void am57x_idk_lcd_detect(void)
  560. {
  561. int r = -ENODEV;
  562. char *idk_lcd = "no";
  563. struct udevice *dev;
  564. /* Only valid for IDKs */
  565. if (board_is_x15() || board_is_am572x_evm())
  566. return;
  567. /* Only AM571x IDK has gpio control detect.. so check that */
  568. if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
  569. goto out;
  570. r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
  571. OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
  572. if (r) {
  573. printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
  574. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  575. r);
  576. /* AM572x IDK has no explicit settings for optional LCD kit */
  577. if (board_is_am571x_idk())
  578. printf("%s: Touch screen detect failed: %d!\n",
  579. __func__, r);
  580. goto out;
  581. }
  582. /* Read FT ID */
  583. r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
  584. if (r < 0) {
  585. printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
  586. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  587. OSD_TS_FT_REG_ID, r);
  588. goto out;
  589. }
  590. switch (r) {
  591. case OSD_TS_FT_ID_5606:
  592. idk_lcd = "osd101t2045";
  593. break;
  594. case OSD_TS_FT_ID_5x46:
  595. idk_lcd = "osd101t2587";
  596. break;
  597. default:
  598. printf("%s: Unidentifed Touch screen ID 0x%02x\n",
  599. __func__, r);
  600. /* we will let default be "no lcd" */
  601. }
  602. out:
  603. env_set("idk_lcd", idk_lcd);
  604. return;
  605. }
  606. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  607. static int device_okay(const char *path)
  608. {
  609. int node;
  610. node = fdt_path_offset(gd->fdt_blob, path);
  611. if (node < 0)
  612. return 0;
  613. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  614. }
  615. #endif
  616. int board_late_init(void)
  617. {
  618. setup_board_eeprom_env();
  619. u8 val;
  620. /*
  621. * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  622. * This is the POWERHOLD-in-Low behavior.
  623. */
  624. palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  625. /*
  626. * Default FIT boot on HS devices. Non FIT images are not allowed
  627. * on HS devices.
  628. */
  629. if (get_device_type() == HS_DEVICE)
  630. env_set("boot_fit", "1");
  631. /*
  632. * Set the GPIO7 Pad to POWERHOLD. This has higher priority
  633. * over DEV_CTRL.DEV_ON bit. This can be reset in case of
  634. * PMIC Power off. So to be on the safer side set it back
  635. * to POWERHOLD mode irrespective of the current state.
  636. */
  637. palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  638. &val);
  639. val = val | TPS65903X_PAD2_POWERHOLD_MASK;
  640. palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  641. val);
  642. omap_die_id_serial();
  643. omap_set_fastboot_vars();
  644. am57x_idk_lcd_detect();
  645. #if !defined(CONFIG_SPL_BUILD)
  646. board_ti_set_ethaddr(2);
  647. #endif
  648. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  649. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  650. enable_usb_clocks(0);
  651. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  652. enable_usb_clocks(1);
  653. #endif
  654. return 0;
  655. }
  656. void set_muxconf_regs(void)
  657. {
  658. do_set_mux32((*ctrl)->control_padconf_core_base,
  659. early_padconf, ARRAY_SIZE(early_padconf));
  660. }
  661. #ifdef CONFIG_IODELAY_RECALIBRATION
  662. void recalibrate_iodelay(void)
  663. {
  664. const struct pad_conf_entry *pconf;
  665. const struct iodelay_cfg_entry *iod, *delta_iod;
  666. int pconf_sz, iod_sz, delta_iod_sz = 0;
  667. int ret;
  668. if (board_is_am572x_idk()) {
  669. pconf = core_padconf_array_essential_am572x_idk;
  670. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
  671. iod = iodelay_cfg_array_am572x_idk;
  672. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
  673. } else if (board_is_am574x_idk()) {
  674. pconf = core_padconf_array_essential_am574x_idk;
  675. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
  676. iod = iodelay_cfg_array_am574x_idk;
  677. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
  678. } else if (board_is_am571x_idk()) {
  679. pconf = core_padconf_array_essential_am571x_idk;
  680. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
  681. iod = iodelay_cfg_array_am571x_idk;
  682. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
  683. } else {
  684. /* Common for X15/GPEVM */
  685. pconf = core_padconf_array_essential_x15;
  686. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
  687. /* There never was an SR1.0 X15.. So.. */
  688. if (omap_revision() == DRA752_ES1_1) {
  689. iod = iodelay_cfg_array_x15_sr1_1;
  690. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
  691. } else {
  692. /* Since full production should switch to SR2.0 */
  693. iod = iodelay_cfg_array_x15_sr2_0;
  694. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
  695. }
  696. }
  697. /* Setup I/O isolation */
  698. ret = __recalibrate_iodelay_start();
  699. if (ret)
  700. goto err;
  701. /* Do the muxing here */
  702. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  703. /* Now do the weird minor deltas that should be safe */
  704. if (board_is_x15() || board_is_am572x_evm()) {
  705. if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
  706. board_is_x15_revc()) {
  707. pconf = core_padconf_array_delta_x15_sr2_0;
  708. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
  709. } else {
  710. pconf = core_padconf_array_delta_x15_sr1_1;
  711. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
  712. }
  713. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  714. }
  715. if (board_is_am571x_idk()) {
  716. if (am571x_idk_needs_lcd()) {
  717. pconf = core_padconf_array_vout_am571x_idk;
  718. pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
  719. delta_iod = iodelay_cfg_array_am571x_idk_4port;
  720. delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
  721. } else {
  722. pconf = core_padconf_array_icss1eth_am571x_idk;
  723. pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
  724. }
  725. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  726. }
  727. /* Setup IOdelay configuration */
  728. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
  729. if (delta_iod_sz)
  730. ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
  731. delta_iod_sz);
  732. err:
  733. /* Closeup.. remove isolation */
  734. __recalibrate_iodelay_end(ret);
  735. }
  736. #endif
  737. #if defined(CONFIG_MMC)
  738. int board_mmc_init(bd_t *bis)
  739. {
  740. omap_mmc_init(0, 0, 0, -1, -1);
  741. omap_mmc_init(1, 0, 0, -1, -1);
  742. return 0;
  743. }
  744. static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
  745. .hw_rev = "rev11",
  746. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  747. MMC_CAP(UHS_SDR104),
  748. .max_freq = 96000000,
  749. };
  750. static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
  751. .hw_rev = "rev11",
  752. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  753. MMC_CAP(UHS_SDR104) |
  754. MMC_CAP(UHS_SDR50),
  755. .max_freq = 48000000,
  756. };
  757. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  758. {
  759. switch (omap_revision()) {
  760. case DRA752_ES1_0:
  761. case DRA752_ES1_1:
  762. if (addr == OMAP_HSMMC1_BASE)
  763. return &am57x_es1_1_mmc1_fixups;
  764. else
  765. return &am57x_es1_1_mmc23_fixups;
  766. default:
  767. return NULL;
  768. }
  769. }
  770. #endif
  771. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  772. int spl_start_uboot(void)
  773. {
  774. /* break into full u-boot on 'c' */
  775. if (serial_tstc() && serial_getc() == 'c')
  776. return 1;
  777. #ifdef CONFIG_SPL_ENV_SUPPORT
  778. env_init();
  779. env_load();
  780. if (env_get_yesno("boot_os") != 1)
  781. return 1;
  782. #endif
  783. return 0;
  784. }
  785. #endif
  786. #ifdef CONFIG_DRIVER_TI_CPSW
  787. /* Delay value to add to calibrated value */
  788. #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  789. #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  790. #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  791. #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  792. #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  793. #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  794. #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  795. #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  796. #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  797. #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  798. static void cpsw_control(int enabled)
  799. {
  800. /* VTP can be added here */
  801. }
  802. static struct cpsw_slave_data cpsw_slaves[] = {
  803. {
  804. .slave_reg_ofs = 0x208,
  805. .sliver_reg_ofs = 0xd80,
  806. .phy_addr = 1,
  807. },
  808. {
  809. .slave_reg_ofs = 0x308,
  810. .sliver_reg_ofs = 0xdc0,
  811. .phy_addr = 2,
  812. },
  813. };
  814. static struct cpsw_platform_data cpsw_data = {
  815. .mdio_base = CPSW_MDIO_BASE,
  816. .cpsw_base = CPSW_BASE,
  817. .mdio_div = 0xff,
  818. .channels = 8,
  819. .cpdma_reg_ofs = 0x800,
  820. .slaves = 1,
  821. .slave_data = cpsw_slaves,
  822. .ale_reg_ofs = 0xd00,
  823. .ale_entries = 1024,
  824. .host_port_reg_ofs = 0x108,
  825. .hw_stats_reg_ofs = 0x900,
  826. .bd_ram_ofs = 0x2000,
  827. .mac_control = (1 << 5),
  828. .control = cpsw_control,
  829. .host_port_num = 0,
  830. .version = CPSW_CTRL_VERSION_2,
  831. };
  832. static u64 mac_to_u64(u8 mac[6])
  833. {
  834. int i;
  835. u64 addr = 0;
  836. for (i = 0; i < 6; i++) {
  837. addr <<= 8;
  838. addr |= mac[i];
  839. }
  840. return addr;
  841. }
  842. static void u64_to_mac(u64 addr, u8 mac[6])
  843. {
  844. mac[5] = addr;
  845. mac[4] = addr >> 8;
  846. mac[3] = addr >> 16;
  847. mac[2] = addr >> 24;
  848. mac[1] = addr >> 32;
  849. mac[0] = addr >> 40;
  850. }
  851. int board_eth_init(bd_t *bis)
  852. {
  853. int ret;
  854. uint8_t mac_addr[6];
  855. uint32_t mac_hi, mac_lo;
  856. uint32_t ctrl_val;
  857. int i;
  858. u64 mac1, mac2;
  859. u8 mac_addr1[6], mac_addr2[6];
  860. int num_macs;
  861. /* try reading mac address from efuse */
  862. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  863. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  864. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  865. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  866. mac_addr[2] = mac_hi & 0xFF;
  867. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  868. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  869. mac_addr[5] = mac_lo & 0xFF;
  870. if (!env_get("ethaddr")) {
  871. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  872. if (is_valid_ethaddr(mac_addr))
  873. eth_env_set_enetaddr("ethaddr", mac_addr);
  874. }
  875. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  876. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  877. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  878. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  879. mac_addr[2] = mac_hi & 0xFF;
  880. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  881. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  882. mac_addr[5] = mac_lo & 0xFF;
  883. if (!env_get("eth1addr")) {
  884. if (is_valid_ethaddr(mac_addr))
  885. eth_env_set_enetaddr("eth1addr", mac_addr);
  886. }
  887. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  888. ctrl_val |= 0x22;
  889. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  890. /* The phy address for the AM57xx IDK are different than x15 */
  891. if (board_is_am572x_idk() || board_is_am571x_idk() ||
  892. board_is_am574x_idk()) {
  893. cpsw_data.slave_data[0].phy_addr = 0;
  894. cpsw_data.slave_data[1].phy_addr = 1;
  895. }
  896. ret = cpsw_register(&cpsw_data);
  897. if (ret < 0)
  898. printf("Error %d registering CPSW switch\n", ret);
  899. /*
  900. * Export any Ethernet MAC addresses from EEPROM.
  901. * On AM57xx the 2 MAC addresses define the address range
  902. */
  903. board_ti_get_eth_mac_addr(0, mac_addr1);
  904. board_ti_get_eth_mac_addr(1, mac_addr2);
  905. if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
  906. mac1 = mac_to_u64(mac_addr1);
  907. mac2 = mac_to_u64(mac_addr2);
  908. /* must contain an address range */
  909. num_macs = mac2 - mac1 + 1;
  910. /* <= 50 to protect against user programming error */
  911. if (num_macs > 0 && num_macs <= 50) {
  912. for (i = 0; i < num_macs; i++) {
  913. u64_to_mac(mac1 + i, mac_addr);
  914. if (is_valid_ethaddr(mac_addr)) {
  915. eth_env_set_enetaddr_by_index("eth",
  916. i + 2,
  917. mac_addr);
  918. }
  919. }
  920. }
  921. }
  922. return ret;
  923. }
  924. #endif
  925. #ifdef CONFIG_BOARD_EARLY_INIT_F
  926. /* VTT regulator enable */
  927. static inline void vtt_regulator_enable(void)
  928. {
  929. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  930. return;
  931. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  932. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  933. }
  934. int board_early_init_f(void)
  935. {
  936. vtt_regulator_enable();
  937. return 0;
  938. }
  939. #endif
  940. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  941. int ft_board_setup(void *blob, bd_t *bd)
  942. {
  943. ft_cpu_setup(blob, bd);
  944. return 0;
  945. }
  946. #endif
  947. #ifdef CONFIG_SPL_LOAD_FIT
  948. int board_fit_config_name_match(const char *name)
  949. {
  950. if (board_is_x15()) {
  951. if (board_is_x15_revb1()) {
  952. if (!strcmp(name, "am57xx-beagle-x15-revb1"))
  953. return 0;
  954. } else if (board_is_x15_revc()) {
  955. if (!strcmp(name, "am57xx-beagle-x15-revc"))
  956. return 0;
  957. } else if (!strcmp(name, "am57xx-beagle-x15")) {
  958. return 0;
  959. }
  960. } else if (board_is_am572x_evm() &&
  961. !strcmp(name, "am57xx-beagle-x15")) {
  962. return 0;
  963. } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
  964. return 0;
  965. } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
  966. return 0;
  967. } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
  968. return 0;
  969. }
  970. return -1;
  971. }
  972. #endif
  973. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  974. int fastboot_set_reboot_flag(void)
  975. {
  976. printf("Setting reboot to fastboot flag ...\n");
  977. env_set("dofastboot", "1");
  978. env_save();
  979. return 0;
  980. }
  981. #endif
  982. #ifdef CONFIG_TI_SECURE_DEVICE
  983. void board_fit_image_post_process(void **p_image, size_t *p_size)
  984. {
  985. secure_boot_verify_image(p_image, p_size);
  986. }
  987. void board_tee_image_process(ulong tee_image, size_t tee_size)
  988. {
  989. secure_tee_install((u32)tee_image);
  990. }
  991. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  992. #endif