board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM43XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <linux/errno.h>
  13. #include <spl.h>
  14. #include <usb.h>
  15. #include <asm/omap_sec_common.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/mux.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/emif.h>
  22. #include <asm/omap_common.h>
  23. #include "../common/board_detect.h"
  24. #include "board.h"
  25. #include <power/pmic.h>
  26. #include <power/tps65218.h>
  27. #include <power/tps62362.h>
  28. #include <miiphy.h>
  29. #include <cpsw.h>
  30. #include <linux/usb/gadget.h>
  31. #include <dwc3-uboot.h>
  32. #include <dwc3-omap-uboot.h>
  33. #include <ti-usb-phy-uboot.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  36. /*
  37. * Read header information from EEPROM into global structure.
  38. */
  39. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  40. void do_board_detect(void)
  41. {
  42. /* Ensure I2C is initialized for EEPROM access*/
  43. gpi2c_init();
  44. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  45. CONFIG_EEPROM_CHIP_ADDRESS))
  46. printf("ti_i2c_eeprom_init failed\n");
  47. }
  48. #endif
  49. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  50. const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  51. { /* 19.2 MHz */
  52. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  53. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  54. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  55. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  56. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  57. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  58. },
  59. { /* 24 MHz */
  60. {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
  61. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  62. {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
  63. {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
  64. {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
  65. {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
  66. },
  67. { /* 25 MHz */
  68. {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
  69. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  70. {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
  71. {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
  72. {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
  73. {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
  74. },
  75. { /* 26 MHz */
  76. {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
  77. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  78. {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
  79. {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
  80. {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
  81. {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
  82. },
  83. };
  84. const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  85. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  86. {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
  87. {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
  88. {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
  89. };
  90. const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  91. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  92. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  93. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  94. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  95. };
  96. const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
  97. {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
  98. {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
  99. {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
  100. {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
  101. };
  102. const struct dpll_params gp_evm_dpll_ddr = {
  103. 50, 2, 1, -1, 2, -1, -1};
  104. static const struct dpll_params idk_dpll_ddr = {
  105. 400, 23, 1, -1, 2, -1, -1
  106. };
  107. static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
  108. 0x00500050,
  109. 0x00350035,
  110. 0x00350035,
  111. 0x00350035,
  112. 0x00350035,
  113. 0x00350035,
  114. 0x00000000,
  115. 0x00000000,
  116. 0x00000000,
  117. 0x00000000,
  118. 0x00000000,
  119. 0x00000000,
  120. 0x00000000,
  121. 0x00000000,
  122. 0x00000000,
  123. 0x00000000,
  124. 0x00000000,
  125. 0x00000000,
  126. 0x40001000,
  127. 0x08102040
  128. };
  129. const struct ctrl_ioregs ioregs_lpddr2 = {
  130. .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
  131. .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
  132. .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
  133. .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  134. .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  135. .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  136. .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  137. .emif_sdram_config_ext = 0x1,
  138. };
  139. const struct emif_regs emif_regs_lpddr2 = {
  140. .sdram_config = 0x808012BA,
  141. .ref_ctrl = 0x0000040D,
  142. .sdram_tim1 = 0xEA86B411,
  143. .sdram_tim2 = 0x103A094A,
  144. .sdram_tim3 = 0x0F6BA37F,
  145. .read_idle_ctrl = 0x00050000,
  146. .zq_config = 0x50074BE4,
  147. .temp_alert_config = 0x0,
  148. .emif_rd_wr_lvl_rmp_win = 0x0,
  149. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  150. .emif_rd_wr_lvl_ctl = 0x0,
  151. .emif_ddr_phy_ctlr_1 = 0x0E284006,
  152. .emif_rd_wr_exec_thresh = 0x80000405,
  153. .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
  154. .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
  155. .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
  156. .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
  157. .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  158. .emif_prio_class_serv_map = 0x80000001,
  159. .emif_connect_id_serv_1_map = 0x80000094,
  160. .emif_connect_id_serv_2_map = 0x00000000,
  161. .emif_cos_config = 0x000FFFFF
  162. };
  163. const struct ctrl_ioregs ioregs_ddr3 = {
  164. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  165. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  166. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  167. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  168. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  169. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  170. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  171. .emif_sdram_config_ext = 0xc163,
  172. };
  173. const struct emif_regs ddr3_emif_regs_400Mhz = {
  174. .sdram_config = 0x638413B2,
  175. .ref_ctrl = 0x00000C30,
  176. .sdram_tim1 = 0xEAAAD4DB,
  177. .sdram_tim2 = 0x266B7FDA,
  178. .sdram_tim3 = 0x107F8678,
  179. .read_idle_ctrl = 0x00050000,
  180. .zq_config = 0x50074BE4,
  181. .temp_alert_config = 0x0,
  182. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  183. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  184. .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
  185. .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
  186. .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
  187. .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
  188. .emif_rd_wr_lvl_rmp_win = 0x0,
  189. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  190. .emif_rd_wr_lvl_ctl = 0x0,
  191. .emif_rd_wr_exec_thresh = 0x80000405,
  192. .emif_prio_class_serv_map = 0x80000001,
  193. .emif_connect_id_serv_1_map = 0x80000094,
  194. .emif_connect_id_serv_2_map = 0x00000000,
  195. .emif_cos_config = 0x000FFFFF
  196. };
  197. /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
  198. const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
  199. .sdram_config = 0x638413B2,
  200. .ref_ctrl = 0x00000C30,
  201. .sdram_tim1 = 0xEAAAD4DB,
  202. .sdram_tim2 = 0x266B7FDA,
  203. .sdram_tim3 = 0x107F8678,
  204. .read_idle_ctrl = 0x00050000,
  205. .zq_config = 0x50074BE4,
  206. .temp_alert_config = 0x0,
  207. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  208. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  209. .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
  210. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  211. .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
  212. .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
  213. .emif_rd_wr_exec_thresh = 0x80000405,
  214. .emif_prio_class_serv_map = 0x80000001,
  215. .emif_connect_id_serv_1_map = 0x80000094,
  216. .emif_connect_id_serv_2_map = 0x00000000,
  217. .emif_cos_config = 0x000FFFFF
  218. };
  219. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  220. const struct emif_regs ddr3_emif_regs_400Mhz_production = {
  221. .sdram_config = 0x638413B2,
  222. .ref_ctrl = 0x00000C30,
  223. .sdram_tim1 = 0xEAAAD4DB,
  224. .sdram_tim2 = 0x266B7FDA,
  225. .sdram_tim3 = 0x107F8678,
  226. .read_idle_ctrl = 0x00050000,
  227. .zq_config = 0x50074BE4,
  228. .temp_alert_config = 0x0,
  229. .emif_ddr_phy_ctlr_1 = 0x00048008,
  230. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  231. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  232. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  233. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  234. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  235. .emif_rd_wr_exec_thresh = 0x80000405,
  236. .emif_prio_class_serv_map = 0x80000001,
  237. .emif_connect_id_serv_1_map = 0x80000094,
  238. .emif_connect_id_serv_2_map = 0x00000000,
  239. .emif_cos_config = 0x000FFFFF
  240. };
  241. static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
  242. .sdram_config = 0x638413b2,
  243. .sdram_config2 = 0x00000000,
  244. .ref_ctrl = 0x00000c30,
  245. .sdram_tim1 = 0xeaaad4db,
  246. .sdram_tim2 = 0x266b7fda,
  247. .sdram_tim3 = 0x107f8678,
  248. .read_idle_ctrl = 0x00050000,
  249. .zq_config = 0x50074be4,
  250. .temp_alert_config = 0x0,
  251. .emif_ddr_phy_ctlr_1 = 0x0e084008,
  252. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  253. .emif_ddr_ext_phy_ctrl_2 = 0x89,
  254. .emif_ddr_ext_phy_ctrl_3 = 0x90,
  255. .emif_ddr_ext_phy_ctrl_4 = 0x8e,
  256. .emif_ddr_ext_phy_ctrl_5 = 0x8d,
  257. .emif_rd_wr_lvl_rmp_win = 0x0,
  258. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  259. .emif_rd_wr_lvl_ctl = 0x00000000,
  260. .emif_rd_wr_exec_thresh = 0x80000000,
  261. .emif_prio_class_serv_map = 0x80000001,
  262. .emif_connect_id_serv_1_map = 0x80000094,
  263. .emif_connect_id_serv_2_map = 0x00000000,
  264. .emif_cos_config = 0x000FFFFF
  265. };
  266. static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
  267. .sdram_config = 0x61a11b32,
  268. .sdram_config2 = 0x00000000,
  269. .ref_ctrl = 0x00000c30,
  270. .sdram_tim1 = 0xeaaad4db,
  271. .sdram_tim2 = 0x266b7fda,
  272. .sdram_tim3 = 0x107f8678,
  273. .read_idle_ctrl = 0x00050000,
  274. .zq_config = 0x50074be4,
  275. .temp_alert_config = 0x00000000,
  276. .emif_ddr_phy_ctlr_1 = 0x00008009,
  277. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  278. .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
  279. .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
  280. .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
  281. .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
  282. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  283. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  284. .emif_rd_wr_lvl_ctl = 0x00000000,
  285. .emif_rd_wr_exec_thresh = 0x00000405,
  286. .emif_prio_class_serv_map = 0x00000000,
  287. .emif_connect_id_serv_1_map = 0x00000000,
  288. .emif_connect_id_serv_2_map = 0x00000000,
  289. .emif_cos_config = 0x00ffffff
  290. };
  291. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  292. {
  293. if (board_is_eposevm()) {
  294. *regs = ext_phy_ctrl_const_base_lpddr2;
  295. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
  296. }
  297. return;
  298. }
  299. const struct dpll_params *get_dpll_ddr_params(void)
  300. {
  301. int ind = get_sys_clk_index();
  302. if (board_is_eposevm())
  303. return &epos_evm_dpll_ddr[ind];
  304. else if (board_is_evm() || board_is_sk())
  305. return &gp_evm_dpll_ddr;
  306. else if (board_is_idk())
  307. return &idk_dpll_ddr;
  308. printf(" Board '%s' not supported\n", board_ti_get_name());
  309. return NULL;
  310. }
  311. /*
  312. * get_opp_offset:
  313. * Returns the index for safest OPP of the device to boot.
  314. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
  315. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
  316. * This data is read from dev_attribute register which is e-fused.
  317. * A'1' in bit indicates OPP disabled and not available, a '0' indicates
  318. * OPP available. Lowest OPP starts with min_off. So returning the
  319. * bit with rightmost '0'.
  320. */
  321. static int get_opp_offset(int max_off, int min_off)
  322. {
  323. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  324. int opp, offset, i;
  325. /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  326. opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  327. for (i = max_off; i >= min_off; i--) {
  328. offset = opp & (1 << i);
  329. if (!offset)
  330. return i;
  331. }
  332. return min_off;
  333. }
  334. const struct dpll_params *get_dpll_mpu_params(void)
  335. {
  336. int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
  337. u32 ind = get_sys_clk_index();
  338. return &dpll_mpu[ind][opp];
  339. }
  340. const struct dpll_params *get_dpll_core_params(void)
  341. {
  342. int ind = get_sys_clk_index();
  343. return &dpll_core[ind];
  344. }
  345. const struct dpll_params *get_dpll_per_params(void)
  346. {
  347. int ind = get_sys_clk_index();
  348. return &dpll_per[ind];
  349. }
  350. void scale_vcores_generic(u32 m)
  351. {
  352. int mpu_vdd, ddr_volt;
  353. #ifndef CONFIG_DM_I2C
  354. if (i2c_probe(TPS65218_CHIP_PM))
  355. return;
  356. #else
  357. if (power_tps65218_init(0))
  358. return;
  359. #endif
  360. switch (m) {
  361. case 1000:
  362. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  363. break;
  364. case 800:
  365. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
  366. break;
  367. case 720:
  368. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
  369. break;
  370. case 600:
  371. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  372. break;
  373. case 300:
  374. mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
  375. break;
  376. default:
  377. puts("Unknown MPU clock, not scaling\n");
  378. return;
  379. }
  380. /* Set DCDC1 (CORE) voltage to 1.1V */
  381. if (tps65218_voltage_update(TPS65218_DCDC1,
  382. TPS65218_DCDC_VOLT_SEL_1100MV)) {
  383. printf("%s failure\n", __func__);
  384. return;
  385. }
  386. /* Set DCDC2 (MPU) voltage */
  387. if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  388. printf("%s failure\n", __func__);
  389. return;
  390. }
  391. if (board_is_eposevm())
  392. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
  393. else
  394. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
  395. /* Set DCDC3 (DDR) voltage */
  396. if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
  397. printf("%s failure\n", __func__);
  398. return;
  399. }
  400. }
  401. void scale_vcores_idk(u32 m)
  402. {
  403. int mpu_vdd;
  404. #ifndef CONFIG_DM_I2C
  405. if (i2c_probe(TPS62362_I2C_ADDR))
  406. return;
  407. #else
  408. if (power_tps62362_init(0))
  409. return;
  410. #endif
  411. switch (m) {
  412. case 1000:
  413. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  414. break;
  415. case 800:
  416. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
  417. break;
  418. case 720:
  419. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
  420. break;
  421. case 600:
  422. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
  423. break;
  424. case 300:
  425. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  426. break;
  427. default:
  428. puts("Unknown MPU clock, not scaling\n");
  429. return;
  430. }
  431. /* Set VDD_MPU voltage */
  432. if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
  433. printf("%s failure\n", __func__);
  434. return;
  435. }
  436. }
  437. void gpi2c_init(void)
  438. {
  439. /* When needed to be invoked prior to BSS initialization */
  440. static bool first_time = true;
  441. if (first_time) {
  442. enable_i2c0_pin_mux();
  443. #ifndef CONFIG_DM_I2C
  444. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  445. CONFIG_SYS_OMAP24_I2C_SLAVE);
  446. #endif
  447. first_time = false;
  448. }
  449. }
  450. void scale_vcores(void)
  451. {
  452. const struct dpll_params *mpu_params;
  453. /* Ensure I2C is initialized for PMIC configuration */
  454. gpi2c_init();
  455. /* Get the frequency */
  456. mpu_params = get_dpll_mpu_params();
  457. if (board_is_idk())
  458. scale_vcores_idk(mpu_params->m);
  459. else
  460. scale_vcores_generic(mpu_params->m);
  461. }
  462. void set_uart_mux_conf(void)
  463. {
  464. enable_uart0_pin_mux();
  465. }
  466. void set_mux_conf_regs(void)
  467. {
  468. enable_board_pin_mux();
  469. }
  470. static void enable_vtt_regulator(void)
  471. {
  472. u32 temp;
  473. /* enable module */
  474. writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
  475. /* enable output for GPIO5_7 */
  476. writel(GPIO_SETDATAOUT(7),
  477. AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
  478. temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  479. temp = temp & ~(GPIO_OE_ENABLE(7));
  480. writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  481. }
  482. enum {
  483. RTC_BOARD_EPOS = 1,
  484. RTC_BOARD_EVM14,
  485. RTC_BOARD_EVM12,
  486. RTC_BOARD_GPEVM,
  487. RTC_BOARD_SK,
  488. };
  489. /*
  490. * In the rtc_only+DRR in self-refresh boot path we have the board type info
  491. * in the rtc scratch pad register hence we bypass the costly i2c reads to
  492. * eeprom and directly programthe board name string
  493. */
  494. void rtc_only_update_board_type(u32 btype)
  495. {
  496. const char *name = "";
  497. const char *rev = "1.0";
  498. switch (btype) {
  499. case RTC_BOARD_EPOS:
  500. name = "AM43EPOS";
  501. break;
  502. case RTC_BOARD_EVM14:
  503. name = "AM43__GP";
  504. rev = "1.4";
  505. break;
  506. case RTC_BOARD_EVM12:
  507. name = "AM43__GP";
  508. rev = "1.2";
  509. break;
  510. case RTC_BOARD_GPEVM:
  511. name = "AM43__GP";
  512. break;
  513. case RTC_BOARD_SK:
  514. name = "AM43__SK";
  515. break;
  516. }
  517. ti_i2c_eeprom_am_set(name, rev);
  518. }
  519. u32 rtc_only_get_board_type(void)
  520. {
  521. if (board_is_eposevm())
  522. return RTC_BOARD_EPOS;
  523. else if (board_is_evm_14_or_later())
  524. return RTC_BOARD_EVM14;
  525. else if (board_is_evm_12_or_later())
  526. return RTC_BOARD_EVM12;
  527. else if (board_is_gpevm())
  528. return RTC_BOARD_GPEVM;
  529. else if (board_is_sk())
  530. return RTC_BOARD_SK;
  531. return 0;
  532. }
  533. void sdram_init(void)
  534. {
  535. /*
  536. * EPOS EVM has 1GB LPDDR2 connected to EMIF.
  537. * GP EMV has 1GB DDR3 connected to EMIF
  538. * along with VTT regulator.
  539. */
  540. if (board_is_eposevm()) {
  541. config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
  542. } else if (board_is_evm_14_or_later()) {
  543. enable_vtt_regulator();
  544. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  545. &ddr3_emif_regs_400Mhz_production, 0);
  546. } else if (board_is_evm_12_or_later()) {
  547. enable_vtt_regulator();
  548. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  549. &ddr3_emif_regs_400Mhz_beta, 0);
  550. } else if (board_is_evm()) {
  551. enable_vtt_regulator();
  552. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  553. &ddr3_emif_regs_400Mhz, 0);
  554. } else if (board_is_sk()) {
  555. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  556. &ddr3_sk_emif_regs_400Mhz, 0);
  557. } else if (board_is_idk()) {
  558. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  559. &ddr3_idk_emif_regs_400Mhz, 0);
  560. }
  561. }
  562. #endif
  563. /* setup board specific PMIC */
  564. int power_init_board(void)
  565. {
  566. int rc;
  567. #ifndef CONFIG_DM_I2C
  568. struct pmic *p = NULL;
  569. #endif
  570. if (board_is_idk()) {
  571. rc = power_tps62362_init(0);
  572. if (rc)
  573. goto done;
  574. #ifndef CONFIG_DM_I2C
  575. p = pmic_get("TPS62362");
  576. if (!p || pmic_probe(p))
  577. goto done;
  578. #endif
  579. puts("PMIC: TPS62362\n");
  580. } else {
  581. rc = power_tps65218_init(0);
  582. if (rc)
  583. goto done;
  584. #ifndef CONFIG_DM_I2C
  585. p = pmic_get("TPS65218_PMIC");
  586. if (!p || pmic_probe(p))
  587. goto done;
  588. #endif
  589. puts("PMIC: TPS65218\n");
  590. }
  591. done:
  592. return 0;
  593. }
  594. int board_init(void)
  595. {
  596. struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  597. u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  598. modena_init0_bw_integer, modena_init0_watermark_0;
  599. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  600. gpmc_init();
  601. /*
  602. * Call this to initialize *ctrl again
  603. */
  604. hw_data_init();
  605. /* Clear all important bits for DSS errata that may need to be tweaked*/
  606. mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  607. MREQPRIO_0_SAB_INIT0_MASK;
  608. mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  609. modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  610. BW_LIMITER_BW_FRAC_MASK;
  611. modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  612. BW_LIMITER_BW_INT_MASK;
  613. modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  614. BW_LIMITER_BW_WATERMARK_MASK;
  615. /* Setting MReq Priority of the DSS*/
  616. mreqprio_0 |= 0x77;
  617. /*
  618. * Set L3 Fast Configuration Register
  619. * Limiting bandwith for ARM core to 700 MBPS
  620. */
  621. modena_init0_bw_fractional |= 0x10;
  622. modena_init0_bw_integer |= 0x3;
  623. writel(mreqprio_0, &cdev->mreqprio_0);
  624. writel(mreqprio_1, &cdev->mreqprio_1);
  625. writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  626. writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  627. writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
  628. return 0;
  629. }
  630. #ifdef CONFIG_BOARD_LATE_INIT
  631. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  632. static int device_okay(const char *path)
  633. {
  634. int node;
  635. node = fdt_path_offset(gd->fdt_blob, path);
  636. if (node < 0)
  637. return 0;
  638. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  639. }
  640. #endif
  641. int board_late_init(void)
  642. {
  643. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  644. set_board_info_env(NULL);
  645. /*
  646. * Default FIT boot on HS devices. Non FIT images are not allowed
  647. * on HS devices.
  648. */
  649. if (get_device_type() == HS_DEVICE)
  650. env_set("boot_fit", "1");
  651. #endif
  652. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  653. if (device_okay("/ocp/omap_dwc3@48380000"))
  654. enable_usb_clocks(0);
  655. if (device_okay("/ocp/omap_dwc3@483c0000"))
  656. enable_usb_clocks(1);
  657. #endif
  658. return 0;
  659. }
  660. #endif
  661. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  662. #ifdef CONFIG_USB_DWC3
  663. static struct dwc3_device usb_otg_ss1 = {
  664. .maximum_speed = USB_SPEED_HIGH,
  665. .base = USB_OTG_SS1_BASE,
  666. .tx_fifo_resize = false,
  667. .index = 0,
  668. };
  669. static struct dwc3_omap_device usb_otg_ss1_glue = {
  670. .base = (void *)USB_OTG_SS1_GLUE_BASE,
  671. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  672. .index = 0,
  673. };
  674. static struct ti_usb_phy_device usb_phy1_device = {
  675. .usb2_phy_power = (void *)USB2_PHY1_POWER,
  676. .index = 0,
  677. };
  678. static struct dwc3_device usb_otg_ss2 = {
  679. .maximum_speed = USB_SPEED_HIGH,
  680. .base = USB_OTG_SS2_BASE,
  681. .tx_fifo_resize = false,
  682. .index = 1,
  683. };
  684. static struct dwc3_omap_device usb_otg_ss2_glue = {
  685. .base = (void *)USB_OTG_SS2_GLUE_BASE,
  686. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  687. .index = 1,
  688. };
  689. static struct ti_usb_phy_device usb_phy2_device = {
  690. .usb2_phy_power = (void *)USB2_PHY2_POWER,
  691. .index = 1,
  692. };
  693. int usb_gadget_handle_interrupts(int index)
  694. {
  695. u32 status;
  696. status = dwc3_omap_uboot_interrupt_status(index);
  697. if (status)
  698. dwc3_uboot_handle_interrupt(index);
  699. return 0;
  700. }
  701. #endif /* CONFIG_USB_DWC3 */
  702. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  703. int board_usb_init(int index, enum usb_init_type init)
  704. {
  705. enable_usb_clocks(index);
  706. #ifdef CONFIG_USB_DWC3
  707. switch (index) {
  708. case 0:
  709. if (init == USB_INIT_DEVICE) {
  710. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  711. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  712. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  713. ti_usb_phy_uboot_init(&usb_phy1_device);
  714. dwc3_uboot_init(&usb_otg_ss1);
  715. }
  716. break;
  717. case 1:
  718. if (init == USB_INIT_DEVICE) {
  719. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  720. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  721. ti_usb_phy_uboot_init(&usb_phy2_device);
  722. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  723. dwc3_uboot_init(&usb_otg_ss2);
  724. }
  725. break;
  726. default:
  727. printf("Invalid Controller Index\n");
  728. }
  729. #endif
  730. return 0;
  731. }
  732. int board_usb_cleanup(int index, enum usb_init_type init)
  733. {
  734. #ifdef CONFIG_USB_DWC3
  735. switch (index) {
  736. case 0:
  737. case 1:
  738. if (init == USB_INIT_DEVICE) {
  739. ti_usb_phy_uboot_exit(index);
  740. dwc3_uboot_exit(index);
  741. dwc3_omap_uboot_exit(index);
  742. }
  743. break;
  744. default:
  745. printf("Invalid Controller Index\n");
  746. }
  747. #endif
  748. disable_usb_clocks(index);
  749. return 0;
  750. }
  751. #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
  752. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  753. #ifdef CONFIG_DRIVER_TI_CPSW
  754. static void cpsw_control(int enabled)
  755. {
  756. /* Additional controls can be added here */
  757. return;
  758. }
  759. static struct cpsw_slave_data cpsw_slaves[] = {
  760. {
  761. .slave_reg_ofs = 0x208,
  762. .sliver_reg_ofs = 0xd80,
  763. .phy_addr = 16,
  764. },
  765. {
  766. .slave_reg_ofs = 0x308,
  767. .sliver_reg_ofs = 0xdc0,
  768. .phy_addr = 1,
  769. },
  770. };
  771. static struct cpsw_platform_data cpsw_data = {
  772. .mdio_base = CPSW_MDIO_BASE,
  773. .cpsw_base = CPSW_BASE,
  774. .mdio_div = 0xff,
  775. .channels = 8,
  776. .cpdma_reg_ofs = 0x800,
  777. .slaves = 1,
  778. .slave_data = cpsw_slaves,
  779. .ale_reg_ofs = 0xd00,
  780. .ale_entries = 1024,
  781. .host_port_reg_ofs = 0x108,
  782. .hw_stats_reg_ofs = 0x900,
  783. .bd_ram_ofs = 0x2000,
  784. .mac_control = (1 << 5),
  785. .control = cpsw_control,
  786. .host_port_num = 0,
  787. .version = CPSW_CTRL_VERSION_2,
  788. };
  789. int board_eth_init(bd_t *bis)
  790. {
  791. int rv;
  792. uint8_t mac_addr[6];
  793. uint32_t mac_hi, mac_lo;
  794. /* try reading mac address from efuse */
  795. mac_lo = readl(&cdev->macid0l);
  796. mac_hi = readl(&cdev->macid0h);
  797. mac_addr[0] = mac_hi & 0xFF;
  798. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  799. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  800. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  801. mac_addr[4] = mac_lo & 0xFF;
  802. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  803. if (!env_get("ethaddr")) {
  804. puts("<ethaddr> not set. Validating first E-fuse MAC\n");
  805. if (is_valid_ethaddr(mac_addr))
  806. eth_env_set_enetaddr("ethaddr", mac_addr);
  807. }
  808. mac_lo = readl(&cdev->macid1l);
  809. mac_hi = readl(&cdev->macid1h);
  810. mac_addr[0] = mac_hi & 0xFF;
  811. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  812. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  813. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  814. mac_addr[4] = mac_lo & 0xFF;
  815. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  816. if (!env_get("eth1addr")) {
  817. if (is_valid_ethaddr(mac_addr))
  818. eth_env_set_enetaddr("eth1addr", mac_addr);
  819. }
  820. if (board_is_eposevm()) {
  821. writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
  822. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
  823. cpsw_slaves[0].phy_addr = 16;
  824. } else if (board_is_sk()) {
  825. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  826. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  827. cpsw_slaves[0].phy_addr = 4;
  828. cpsw_slaves[1].phy_addr = 5;
  829. } else if (board_is_idk()) {
  830. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  831. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  832. cpsw_slaves[0].phy_addr = 0;
  833. } else {
  834. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  835. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  836. cpsw_slaves[0].phy_addr = 0;
  837. }
  838. rv = cpsw_register(&cpsw_data);
  839. if (rv < 0)
  840. printf("Error %d registering CPSW switch\n", rv);
  841. return rv;
  842. }
  843. #endif
  844. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  845. int ft_board_setup(void *blob, bd_t *bd)
  846. {
  847. ft_cpu_setup(blob, bd);
  848. return 0;
  849. }
  850. #endif
  851. #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
  852. int board_fit_config_name_match(const char *name)
  853. {
  854. bool eeprom_read = board_ti_was_eeprom_read();
  855. if (!strcmp(name, "am4372-generic") && !eeprom_read)
  856. return 0;
  857. else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
  858. return 0;
  859. else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
  860. return 0;
  861. else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
  862. return 0;
  863. else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
  864. return 0;
  865. else
  866. return -1;
  867. }
  868. #endif
  869. #ifdef CONFIG_DTB_RESELECT
  870. int embedded_dtb_select(void)
  871. {
  872. do_board_detect();
  873. fdtdec_setup();
  874. return 0;
  875. }
  876. #endif
  877. #ifdef CONFIG_TI_SECURE_DEVICE
  878. void board_fit_image_post_process(void **p_image, size_t *p_size)
  879. {
  880. secure_boot_verify_image(p_image, p_size);
  881. }
  882. void board_tee_image_process(ulong tee_image, size_t tee_size)
  883. {
  884. secure_tee_install((u32)tee_image);
  885. }
  886. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  887. #endif