board.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <spl.h>
  14. #include <serial.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/clk_synthesizer.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/mmc_host_def.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/io.h>
  26. #include <asm/emif.h>
  27. #include <asm/gpio.h>
  28. #include <asm/omap_common.h>
  29. #include <asm/omap_sec_common.h>
  30. #include <asm/omap_mmc.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <power/tps65217.h>
  35. #include <power/tps65910.h>
  36. #include <environment.h>
  37. #include <watchdog.h>
  38. #include "../common/board_detect.h"
  39. #include "board.h"
  40. DECLARE_GLOBAL_DATA_PTR;
  41. /* GPIO that controls power to DDR on EVM-SK */
  42. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  43. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
  44. #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
  45. #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
  46. #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
  47. #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
  48. #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
  49. #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
  50. #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
  51. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  52. #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  53. #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  54. #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  55. #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  56. #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
  57. #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
  58. /*
  59. * Read header information from EEPROM into global structure.
  60. */
  61. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  62. void do_board_detect(void)
  63. {
  64. enable_i2c0_pin_mux();
  65. #ifndef CONFIG_DM_I2C
  66. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  67. #endif
  68. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  69. CONFIG_EEPROM_CHIP_ADDRESS))
  70. printf("ti_i2c_eeprom_init failed\n");
  71. }
  72. #endif
  73. #ifndef CONFIG_DM_SERIAL
  74. struct serial_device *default_serial_console(void)
  75. {
  76. if (board_is_icev2())
  77. return &eserial4_device;
  78. else
  79. return &eserial1_device;
  80. }
  81. #endif
  82. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  83. static const struct ddr_data ddr2_data = {
  84. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  85. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  86. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  87. };
  88. static const struct cmd_control ddr2_cmd_ctrl_data = {
  89. .cmd0csratio = MT47H128M16RT25E_RATIO,
  90. .cmd1csratio = MT47H128M16RT25E_RATIO,
  91. .cmd2csratio = MT47H128M16RT25E_RATIO,
  92. };
  93. static const struct emif_regs ddr2_emif_reg_data = {
  94. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  95. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  96. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  97. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  98. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  99. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  100. };
  101. static const struct emif_regs ddr2_evm_emif_reg_data = {
  102. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  103. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  104. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  105. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  106. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  107. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  108. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  109. };
  110. static const struct ddr_data ddr3_data = {
  111. .datardsratio0 = MT41J128MJT125_RD_DQS,
  112. .datawdsratio0 = MT41J128MJT125_WR_DQS,
  113. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  114. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  115. };
  116. static const struct ddr_data ddr3_beagleblack_data = {
  117. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  118. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  119. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  120. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  121. };
  122. static const struct ddr_data ddr3_evm_data = {
  123. .datardsratio0 = MT41J512M8RH125_RD_DQS,
  124. .datawdsratio0 = MT41J512M8RH125_WR_DQS,
  125. .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
  126. .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
  127. };
  128. static const struct ddr_data ddr3_icev2_data = {
  129. .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
  130. .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
  131. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
  132. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
  133. };
  134. static const struct cmd_control ddr3_cmd_ctrl_data = {
  135. .cmd0csratio = MT41J128MJT125_RATIO,
  136. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  137. .cmd1csratio = MT41J128MJT125_RATIO,
  138. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  139. .cmd2csratio = MT41J128MJT125_RATIO,
  140. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  141. };
  142. static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
  143. .cmd0csratio = MT41K256M16HA125E_RATIO,
  144. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  145. .cmd1csratio = MT41K256M16HA125E_RATIO,
  146. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  147. .cmd2csratio = MT41K256M16HA125E_RATIO,
  148. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  149. };
  150. static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
  151. .cmd0csratio = MT41J512M8RH125_RATIO,
  152. .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  153. .cmd1csratio = MT41J512M8RH125_RATIO,
  154. .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  155. .cmd2csratio = MT41J512M8RH125_RATIO,
  156. .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  157. };
  158. static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
  159. .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
  160. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  161. .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
  162. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  163. .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
  164. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  165. };
  166. static struct emif_regs ddr3_emif_reg_data = {
  167. .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  168. .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  169. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  170. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  171. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  172. .zq_config = MT41J128MJT125_ZQ_CFG,
  173. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  174. PHY_EN_DYN_PWRDN,
  175. };
  176. static struct emif_regs ddr3_beagleblack_emif_reg_data = {
  177. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  178. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  179. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  180. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  181. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  182. .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
  183. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  184. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  185. };
  186. static struct emif_regs ddr3_evm_emif_reg_data = {
  187. .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
  188. .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
  189. .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
  190. .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
  191. .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
  192. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  193. .zq_config = MT41J512M8RH125_ZQ_CFG,
  194. .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
  195. PHY_EN_DYN_PWRDN,
  196. };
  197. static struct emif_regs ddr3_icev2_emif_reg_data = {
  198. .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
  199. .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
  200. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
  201. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
  202. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
  203. .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
  204. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
  205. PHY_EN_DYN_PWRDN,
  206. };
  207. #ifdef CONFIG_SPL_OS_BOOT
  208. int spl_start_uboot(void)
  209. {
  210. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  211. /* break into full u-boot on 'c' */
  212. if (serial_tstc() && serial_getc() == 'c')
  213. return 1;
  214. #endif
  215. #ifdef CONFIG_SPL_ENV_SUPPORT
  216. env_init();
  217. env_load();
  218. if (env_get_yesno("boot_os") != 1)
  219. return 1;
  220. #endif
  221. return 0;
  222. }
  223. #endif
  224. const struct dpll_params *get_dpll_ddr_params(void)
  225. {
  226. int ind = get_sys_clk_index();
  227. if (board_is_evm_sk())
  228. return &dpll_ddr3_303MHz[ind];
  229. else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
  230. return &dpll_ddr3_400MHz[ind];
  231. else if (board_is_evm_15_or_later())
  232. return &dpll_ddr3_303MHz[ind];
  233. else
  234. return &dpll_ddr2_266MHz[ind];
  235. }
  236. static u8 bone_not_connected_to_ac_power(void)
  237. {
  238. if (board_is_bone()) {
  239. uchar pmic_status_reg;
  240. if (tps65217_reg_read(TPS65217_STATUS,
  241. &pmic_status_reg))
  242. return 1;
  243. if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
  244. puts("No AC power, switching to default OPP\n");
  245. return 1;
  246. }
  247. }
  248. return 0;
  249. }
  250. const struct dpll_params *get_dpll_mpu_params(void)
  251. {
  252. int ind = get_sys_clk_index();
  253. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  254. if (bone_not_connected_to_ac_power())
  255. freq = MPUPLL_M_600;
  256. if (board_is_pb() || board_is_bone_lt())
  257. freq = MPUPLL_M_1000;
  258. switch (freq) {
  259. case MPUPLL_M_1000:
  260. return &dpll_mpu_opp[ind][5];
  261. case MPUPLL_M_800:
  262. return &dpll_mpu_opp[ind][4];
  263. case MPUPLL_M_720:
  264. return &dpll_mpu_opp[ind][3];
  265. case MPUPLL_M_600:
  266. return &dpll_mpu_opp[ind][2];
  267. case MPUPLL_M_500:
  268. return &dpll_mpu_opp100;
  269. case MPUPLL_M_300:
  270. return &dpll_mpu_opp[ind][0];
  271. }
  272. return &dpll_mpu_opp[ind][0];
  273. }
  274. static void scale_vcores_bone(int freq)
  275. {
  276. int usb_cur_lim, mpu_vdd;
  277. /*
  278. * Only perform PMIC configurations if board rev > A1
  279. * on Beaglebone White
  280. */
  281. if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
  282. return;
  283. #ifndef CONFIG_DM_I2C
  284. if (i2c_probe(TPS65217_CHIP_PM))
  285. return;
  286. #else
  287. if (power_tps65217_init(0))
  288. return;
  289. #endif
  290. /*
  291. * On Beaglebone White we need to ensure we have AC power
  292. * before increasing the frequency.
  293. */
  294. if (bone_not_connected_to_ac_power())
  295. freq = MPUPLL_M_600;
  296. /*
  297. * Override what we have detected since we know if we have
  298. * a Beaglebone Black it supports 1GHz.
  299. */
  300. if (board_is_pb() || board_is_bone_lt())
  301. freq = MPUPLL_M_1000;
  302. switch (freq) {
  303. case MPUPLL_M_1000:
  304. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  305. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  306. break;
  307. case MPUPLL_M_800:
  308. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  309. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  310. break;
  311. case MPUPLL_M_720:
  312. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  313. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  314. break;
  315. case MPUPLL_M_600:
  316. case MPUPLL_M_500:
  317. case MPUPLL_M_300:
  318. default:
  319. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  320. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  321. break;
  322. }
  323. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  324. TPS65217_POWER_PATH,
  325. usb_cur_lim,
  326. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  327. puts("tps65217_reg_write failure\n");
  328. /* Set DCDC3 (CORE) voltage to 1.10V */
  329. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  330. TPS65217_DCDC_VOLT_SEL_1100MV)) {
  331. puts("tps65217_voltage_update failure\n");
  332. return;
  333. }
  334. /* Set DCDC2 (MPU) voltage */
  335. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  336. puts("tps65217_voltage_update failure\n");
  337. return;
  338. }
  339. /*
  340. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  341. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  342. */
  343. if (board_is_bone()) {
  344. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  345. TPS65217_DEFLS1,
  346. TPS65217_LDO_VOLTAGE_OUT_3_3,
  347. TPS65217_LDO_MASK))
  348. puts("tps65217_reg_write failure\n");
  349. } else {
  350. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  351. TPS65217_DEFLS1,
  352. TPS65217_LDO_VOLTAGE_OUT_1_8,
  353. TPS65217_LDO_MASK))
  354. puts("tps65217_reg_write failure\n");
  355. }
  356. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  357. TPS65217_DEFLS2,
  358. TPS65217_LDO_VOLTAGE_OUT_3_3,
  359. TPS65217_LDO_MASK))
  360. puts("tps65217_reg_write failure\n");
  361. }
  362. void scale_vcores_generic(int freq)
  363. {
  364. int sil_rev, mpu_vdd;
  365. /*
  366. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  367. * MPU frequencies we support we use a CORE voltage of
  368. * 1.10V. For MPU voltage we need to switch based on
  369. * the frequency we are running at.
  370. */
  371. #ifndef CONFIG_DM_I2C
  372. if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
  373. return;
  374. #else
  375. if (power_tps65910_init(0))
  376. return;
  377. #endif
  378. /*
  379. * Depending on MPU clock and PG we will need a different
  380. * VDD to drive at that speed.
  381. */
  382. sil_rev = readl(&cdev->deviceid) >> 28;
  383. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  384. /* Tell the TPS65910 to use i2c */
  385. tps65910_set_i2c_control();
  386. /* First update MPU voltage. */
  387. if (tps65910_voltage_update(MPU, mpu_vdd))
  388. return;
  389. /* Second, update the CORE voltage. */
  390. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  391. return;
  392. }
  393. void gpi2c_init(void)
  394. {
  395. /* When needed to be invoked prior to BSS initialization */
  396. static bool first_time = true;
  397. if (first_time) {
  398. enable_i2c0_pin_mux();
  399. #ifndef CONFIG_DM_I2C
  400. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  401. CONFIG_SYS_OMAP24_I2C_SLAVE);
  402. #endif
  403. first_time = false;
  404. }
  405. }
  406. void scale_vcores(void)
  407. {
  408. int freq;
  409. gpi2c_init();
  410. freq = am335x_get_efuse_mpu_max_freq(cdev);
  411. if (board_is_beaglebonex())
  412. scale_vcores_bone(freq);
  413. else
  414. scale_vcores_generic(freq);
  415. }
  416. void set_uart_mux_conf(void)
  417. {
  418. #if CONFIG_CONS_INDEX == 1
  419. enable_uart0_pin_mux();
  420. #elif CONFIG_CONS_INDEX == 2
  421. enable_uart1_pin_mux();
  422. #elif CONFIG_CONS_INDEX == 3
  423. enable_uart2_pin_mux();
  424. #elif CONFIG_CONS_INDEX == 4
  425. enable_uart3_pin_mux();
  426. #elif CONFIG_CONS_INDEX == 5
  427. enable_uart4_pin_mux();
  428. #elif CONFIG_CONS_INDEX == 6
  429. enable_uart5_pin_mux();
  430. #endif
  431. }
  432. void set_mux_conf_regs(void)
  433. {
  434. enable_board_pin_mux();
  435. }
  436. const struct ctrl_ioregs ioregs_evmsk = {
  437. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  438. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  439. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  440. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  441. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  442. };
  443. const struct ctrl_ioregs ioregs_bonelt = {
  444. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  445. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  446. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  447. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  448. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  449. };
  450. const struct ctrl_ioregs ioregs_evm15 = {
  451. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  452. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  453. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  454. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  455. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  456. };
  457. const struct ctrl_ioregs ioregs = {
  458. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  459. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  460. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  461. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  462. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  463. };
  464. void sdram_init(void)
  465. {
  466. if (board_is_evm_sk()) {
  467. /*
  468. * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
  469. * This is safe enough to do on older revs.
  470. */
  471. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  472. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  473. }
  474. if (board_is_icev2()) {
  475. gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
  476. gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
  477. }
  478. if (board_is_evm_sk())
  479. config_ddr(303, &ioregs_evmsk, &ddr3_data,
  480. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  481. else if (board_is_pb() || board_is_bone_lt())
  482. config_ddr(400, &ioregs_bonelt,
  483. &ddr3_beagleblack_data,
  484. &ddr3_beagleblack_cmd_ctrl_data,
  485. &ddr3_beagleblack_emif_reg_data, 0);
  486. else if (board_is_evm_15_or_later())
  487. config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
  488. &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
  489. else if (board_is_icev2())
  490. config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
  491. &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
  492. 0);
  493. else if (board_is_gp_evm())
  494. config_ddr(266, &ioregs, &ddr2_data,
  495. &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
  496. else
  497. config_ddr(266, &ioregs, &ddr2_data,
  498. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  499. }
  500. #endif
  501. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  502. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  503. static void request_and_set_gpio(int gpio, char *name, int val)
  504. {
  505. int ret;
  506. ret = gpio_request(gpio, name);
  507. if (ret < 0) {
  508. printf("%s: Unable to request %s\n", __func__, name);
  509. return;
  510. }
  511. ret = gpio_direction_output(gpio, 0);
  512. if (ret < 0) {
  513. printf("%s: Unable to set %s as output\n", __func__, name);
  514. goto err_free_gpio;
  515. }
  516. gpio_set_value(gpio, val);
  517. return;
  518. err_free_gpio:
  519. gpio_free(gpio);
  520. }
  521. #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
  522. #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
  523. /**
  524. * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
  525. * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
  526. * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
  527. * give 50MHz output for Eth0 and 1.
  528. */
  529. static struct clk_synth cdce913_data = {
  530. .id = 0x81,
  531. .capacitor = 0x90,
  532. .mux = 0x6d,
  533. .pdiv2 = 0x2,
  534. .pdiv3 = 0x2,
  535. };
  536. #endif
  537. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
  538. defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
  539. #define MAX_CPSW_SLAVES 2
  540. /* At the moment, we do not want to stop booting for any failures here */
  541. int ft_board_setup(void *fdt, bd_t *bd)
  542. {
  543. const char *slave_path, *enet_name;
  544. int enetnode, slavenode, phynode;
  545. struct udevice *ethdev;
  546. char alias[16];
  547. u32 phy_id[2];
  548. int phy_addr;
  549. int i, ret;
  550. /* phy address fixup needed only on beagle bone family */
  551. if (!board_is_beaglebonex())
  552. goto done;
  553. for (i = 0; i < MAX_CPSW_SLAVES; i++) {
  554. sprintf(alias, "ethernet%d", i);
  555. slave_path = fdt_get_alias(fdt, alias);
  556. if (!slave_path)
  557. continue;
  558. slavenode = fdt_path_offset(fdt, slave_path);
  559. if (slavenode < 0)
  560. continue;
  561. enetnode = fdt_parent_offset(fdt, slavenode);
  562. enet_name = fdt_get_name(fdt, enetnode, NULL);
  563. ethdev = eth_get_dev_by_name(enet_name);
  564. if (!ethdev)
  565. continue;
  566. phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
  567. /* check for phy_id as well as phy-handle properties */
  568. ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
  569. phy_id, 2);
  570. if (ret == 2) {
  571. if (phy_id[1] != phy_addr) {
  572. printf("fixing up phy_id for %s, old: %d, new: %d\n",
  573. alias, phy_id[1], phy_addr);
  574. phy_id[0] = cpu_to_fdt32(phy_id[0]);
  575. phy_id[1] = cpu_to_fdt32(phy_addr);
  576. do_fixup_by_path(fdt, slave_path, "phy_id",
  577. phy_id, sizeof(phy_id), 0);
  578. }
  579. } else {
  580. phynode = fdtdec_lookup_phandle(fdt, slavenode,
  581. "phy-handle");
  582. if (phynode < 0)
  583. continue;
  584. ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
  585. if (ret < 0)
  586. continue;
  587. if (ret != phy_addr) {
  588. printf("fixing up phy-handle for %s, old: %d, new: %d\n",
  589. alias, ret, phy_addr);
  590. fdt_setprop_u32(fdt, phynode, "reg",
  591. cpu_to_fdt32(phy_addr));
  592. }
  593. }
  594. }
  595. done:
  596. return 0;
  597. }
  598. #endif
  599. /*
  600. * Basic board specific setup. Pinmux has been handled already.
  601. */
  602. int board_init(void)
  603. {
  604. #if defined(CONFIG_HW_WATCHDOG)
  605. hw_watchdog_init();
  606. #endif
  607. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  608. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  609. gpmc_init();
  610. #endif
  611. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  612. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  613. if (board_is_icev2()) {
  614. int rv;
  615. u32 reg;
  616. REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
  617. /* Make J19 status available on GPIO1_26 */
  618. REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
  619. REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
  620. /*
  621. * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
  622. * jumpers near the port. Read the jumper value and set
  623. * the pinmux, external mux and PHY clock accordingly.
  624. * As jumper line is overridden by PHY RX_DV pin immediately
  625. * after bootstrap (power-up/reset), we need to sample
  626. * it during PHY reset using GPIO rising edge detection.
  627. */
  628. REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
  629. /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
  630. reg = readl(GPIO0_RISINGDETECT) | BIT(11);
  631. writel(reg, GPIO0_RISINGDETECT);
  632. reg = readl(GPIO1_RISINGDETECT) | BIT(26);
  633. writel(reg, GPIO1_RISINGDETECT);
  634. /* Reset PHYs to capture the Jumper setting */
  635. gpio_set_value(GPIO_PHY_RESET, 0);
  636. udelay(2); /* PHY datasheet states 1uS min. */
  637. gpio_set_value(GPIO_PHY_RESET, 1);
  638. reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
  639. if (reg) {
  640. writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
  641. /* RMII mode */
  642. printf("ETH0, CPSW\n");
  643. } else {
  644. /* MII mode */
  645. printf("ETH0, PRU\n");
  646. cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
  647. }
  648. reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
  649. if (reg) {
  650. writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
  651. /* RMII mode */
  652. printf("ETH1, CPSW\n");
  653. gpio_set_value(GPIO_MUX_MII_CTRL, 1);
  654. } else {
  655. /* MII mode */
  656. printf("ETH1, PRU\n");
  657. cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
  658. }
  659. /* disable rising edge IRQs */
  660. reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
  661. writel(reg, GPIO0_RISINGDETECT);
  662. reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
  663. writel(reg, GPIO1_RISINGDETECT);
  664. rv = setup_clock_synthesizer(&cdce913_data);
  665. if (rv) {
  666. printf("Clock synthesizer setup failed %d\n", rv);
  667. return rv;
  668. }
  669. /* reset PHYs */
  670. gpio_set_value(GPIO_PHY_RESET, 0);
  671. udelay(2); /* PHY datasheet states 1uS min. */
  672. gpio_set_value(GPIO_PHY_RESET, 1);
  673. }
  674. #endif
  675. return 0;
  676. }
  677. #ifdef CONFIG_BOARD_LATE_INIT
  678. int board_late_init(void)
  679. {
  680. #if !defined(CONFIG_SPL_BUILD)
  681. uint8_t mac_addr[6];
  682. uint32_t mac_hi, mac_lo;
  683. #endif
  684. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  685. char *name = NULL;
  686. if (board_is_bone_lt()) {
  687. /* BeagleBoard.org BeagleBone Black Wireless: */
  688. if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
  689. name = "BBBW";
  690. }
  691. /* SeeedStudio BeagleBone Green Wireless */
  692. if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
  693. name = "BBGW";
  694. }
  695. /* BeagleBoard.org BeagleBone Blue */
  696. if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
  697. name = "BBBL";
  698. }
  699. }
  700. if (board_is_bbg1())
  701. name = "BBG1";
  702. if (board_is_bben())
  703. name = "BBEN";
  704. set_board_info_env(name);
  705. /*
  706. * Default FIT boot on HS devices. Non FIT images are not allowed
  707. * on HS devices.
  708. */
  709. if (get_device_type() == HS_DEVICE)
  710. env_set("boot_fit", "1");
  711. #endif
  712. #if !defined(CONFIG_SPL_BUILD)
  713. /* try reading mac address from efuse */
  714. mac_lo = readl(&cdev->macid0l);
  715. mac_hi = readl(&cdev->macid0h);
  716. mac_addr[0] = mac_hi & 0xFF;
  717. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  718. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  719. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  720. mac_addr[4] = mac_lo & 0xFF;
  721. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  722. if (!env_get("ethaddr")) {
  723. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  724. if (is_valid_ethaddr(mac_addr))
  725. eth_env_set_enetaddr("ethaddr", mac_addr);
  726. }
  727. mac_lo = readl(&cdev->macid1l);
  728. mac_hi = readl(&cdev->macid1h);
  729. mac_addr[0] = mac_hi & 0xFF;
  730. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  731. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  732. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  733. mac_addr[4] = mac_lo & 0xFF;
  734. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  735. if (!env_get("eth1addr")) {
  736. if (is_valid_ethaddr(mac_addr))
  737. eth_env_set_enetaddr("eth1addr", mac_addr);
  738. }
  739. #endif
  740. if (!env_get("serial#")) {
  741. char *board_serial = env_get("board_serial");
  742. char *ethaddr = env_get("ethaddr");
  743. if (!board_serial || !strncmp(board_serial, "unknown", 7))
  744. env_set("serial#", ethaddr);
  745. else
  746. env_set("serial#", board_serial);
  747. }
  748. return 0;
  749. }
  750. #endif
  751. /* CPSW platdata */
  752. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  753. struct cpsw_slave_data slave_data[] = {
  754. {
  755. .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
  756. .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
  757. .phy_addr = 0,
  758. },
  759. {
  760. .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
  761. .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
  762. .phy_addr = 1,
  763. },
  764. };
  765. struct cpsw_platform_data am335_eth_data = {
  766. .cpsw_base = CPSW_BASE,
  767. .version = CPSW_CTRL_VERSION_2,
  768. .bd_ram_ofs = CPSW_BD_OFFSET,
  769. .ale_reg_ofs = CPSW_ALE_OFFSET,
  770. .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
  771. .mdio_div = CPSW_MDIO_DIV,
  772. .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  773. .channels = 8,
  774. .slaves = 2,
  775. .slave_data = slave_data,
  776. .ale_entries = 1024,
  777. .bd_ram_ofs = 0x2000,
  778. .mac_control = 0x20,
  779. .active_slave = 0,
  780. .mdio_base = 0x4a101000,
  781. .gmii_sel = 0x44e10650,
  782. .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
  783. .syscon_addr = 0x44e10630,
  784. .macid_sel_compat = "cpsw,am33xx",
  785. };
  786. struct eth_pdata cpsw_pdata = {
  787. .iobase = 0x4a100000,
  788. .phy_interface = 0,
  789. .priv_pdata = &am335_eth_data,
  790. };
  791. U_BOOT_DEVICE(am335x_eth) = {
  792. .name = "eth_cpsw",
  793. .platdata = &cpsw_pdata,
  794. };
  795. #endif
  796. #ifdef CONFIG_SPL_LOAD_FIT
  797. int board_fit_config_name_match(const char *name)
  798. {
  799. if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
  800. return 0;
  801. else if (board_is_bone() && !strcmp(name, "am335x-bone"))
  802. return 0;
  803. else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
  804. return 0;
  805. else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
  806. return 0;
  807. else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
  808. return 0;
  809. else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
  810. return 0;
  811. else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
  812. return 0;
  813. else
  814. return -1;
  815. }
  816. #endif
  817. #ifdef CONFIG_TI_SECURE_DEVICE
  818. void board_fit_image_post_process(void **p_image, size_t *p_size)
  819. {
  820. secure_boot_verify_image(p_image, p_size);
  821. }
  822. #endif
  823. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  824. static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
  825. .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
  826. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
  827. .cfg.f_min = 400000,
  828. .cfg.f_max = 52000000,
  829. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  830. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  831. };
  832. U_BOOT_DEVICE(am335x_mmc0) = {
  833. .name = "omap_hsmmc",
  834. .platdata = &am335x_mmc0_platdata,
  835. };
  836. static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
  837. .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
  838. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
  839. .cfg.f_min = 400000,
  840. .cfg.f_max = 52000000,
  841. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  842. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  843. };
  844. U_BOOT_DEVICE(am335x_mmc1) = {
  845. .name = "omap_hsmmc",
  846. .platdata = &am335x_mmc1_platdata,
  847. };
  848. #endif