ts4800.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Savoir-faire Linux Inc.
  4. *
  5. * Derived from MX51EVK code by
  6. * Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/gpio.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux-mx51.h>
  13. #include <env.h>
  14. #include <linux/errno.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/mach-imx/mx5_video.h>
  19. #include <mmc.h>
  20. #include <input.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <mc13892.h>
  23. #include <malloc.h>
  24. #include <netdev.h>
  25. #include <phy.h>
  26. #include "ts4800.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifdef CONFIG_FSL_ESDHC_IMX
  29. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  30. {MMC_SDHC1_BASE_ADDR},
  31. {MMC_SDHC2_BASE_ADDR},
  32. };
  33. #endif
  34. int dram_init(void)
  35. {
  36. /* dram_init must store complete ramsize in gd->ram_size */
  37. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  38. PHYS_SDRAM_1_SIZE);
  39. return 0;
  40. }
  41. u32 get_board_rev(void)
  42. {
  43. u32 rev = get_cpu_rev();
  44. if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  45. rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  46. return rev;
  47. }
  48. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  49. static void setup_iomux_uart(void)
  50. {
  51. static const iomux_v3_cfg_t uart_pads[] = {
  52. MX51_PAD_UART1_RXD__UART1_RXD,
  53. MX51_PAD_UART1_TXD__UART1_TXD,
  54. NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  55. NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  56. };
  57. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  58. }
  59. static void setup_iomux_fec(void)
  60. {
  61. static const iomux_v3_cfg_t fec_pads[] = {
  62. NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
  63. PAD_CTL_HYS |
  64. PAD_CTL_PUS_22K_UP |
  65. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  66. MX51_PAD_EIM_EB3__FEC_RDATA1,
  67. NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
  68. MX51_PAD_EIM_CS3__FEC_RDATA3,
  69. MX51_PAD_NANDF_CS2__FEC_TX_ER,
  70. MX51_PAD_EIM_CS5__FEC_CRS,
  71. MX51_PAD_EIM_CS4__FEC_RX_ER,
  72. /* PAD used on TS4800 */
  73. MX51_PAD_DI2_PIN2__FEC_MDC,
  74. MX51_PAD_DISP2_DAT14__FEC_RDAT0,
  75. MX51_PAD_DISP2_DAT10__FEC_COL,
  76. MX51_PAD_DISP2_DAT11__FEC_RXCLK,
  77. MX51_PAD_DISP2_DAT15__FEC_TDAT0,
  78. MX51_PAD_DISP2_DAT6__FEC_TDAT1,
  79. MX51_PAD_DISP2_DAT7__FEC_TDAT2,
  80. MX51_PAD_DISP2_DAT8__FEC_TDAT3,
  81. MX51_PAD_DISP2_DAT9__FEC_TX_EN,
  82. MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
  83. MX51_PAD_DISP2_DAT12__FEC_RX_DV,
  84. };
  85. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  86. }
  87. #ifdef CONFIG_FSL_ESDHC_IMX
  88. int board_mmc_getcd(struct mmc *mmc)
  89. {
  90. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  91. int ret;
  92. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
  93. NO_PAD_CTRL));
  94. gpio_direction_input(IMX_GPIO_NR(1, 0));
  95. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
  96. NO_PAD_CTRL));
  97. gpio_direction_input(IMX_GPIO_NR(1, 6));
  98. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  99. ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
  100. else
  101. ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
  102. return ret;
  103. }
  104. int board_mmc_init(bd_t *bis)
  105. {
  106. static const iomux_v3_cfg_t sd1_pads[] = {
  107. NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
  108. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  109. NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
  110. PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  111. NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
  112. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  113. NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
  114. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  115. NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
  116. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  117. NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
  118. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
  119. NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
  120. NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
  121. };
  122. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  123. imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
  124. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  125. }
  126. #endif
  127. int board_early_init_f(void)
  128. {
  129. setup_iomux_uart();
  130. setup_iomux_fec();
  131. return 0;
  132. }
  133. int board_init(void)
  134. {
  135. /* address of boot parameters */
  136. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  137. return 0;
  138. }
  139. /*
  140. * Read the MAC address from FEC's registers PALR PAUR.
  141. * User is supposed to configure these registers when MAC address is known
  142. * from another source (fuse), but on TS4800, MAC address is not fused and
  143. * the bootrom configure these registers on startup.
  144. */
  145. static int fec_get_mac_from_register(uint32_t base_addr)
  146. {
  147. unsigned char ethaddr[6];
  148. u32 reg_mac[2];
  149. int i;
  150. reg_mac[0] = in_be32(base_addr + 0xE4);
  151. reg_mac[1] = in_be32(base_addr + 0xE8);
  152. for(i = 0; i < 6; i++)
  153. ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
  154. if (is_valid_ethaddr(ethaddr)) {
  155. eth_env_set_enetaddr("ethaddr", ethaddr);
  156. return 0;
  157. }
  158. return -1;
  159. }
  160. #define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
  161. int board_eth_init(bd_t *bd)
  162. {
  163. int dev_id = -1;
  164. int phy_id = 0xFF;
  165. uint32_t addr = IMX_FEC_BASE;
  166. uint32_t base_mii;
  167. struct mii_dev *bus = NULL;
  168. struct phy_device *phydev = NULL;
  169. int ret;
  170. /* reset FEC phy */
  171. imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
  172. gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
  173. mdelay(1);
  174. gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
  175. mdelay(1);
  176. base_mii = addr;
  177. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  178. bus = fec_get_miibus(base_mii, dev_id);
  179. if (!bus)
  180. return -ENOMEM;
  181. phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
  182. if (!phydev) {
  183. free(bus);
  184. return -ENOMEM;
  185. }
  186. if (fec_get_mac_from_register(addr))
  187. printf("eth_init: failed to get MAC address\n");
  188. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  189. if (ret) {
  190. free(phydev);
  191. free(bus);
  192. }
  193. return ret;
  194. }
  195. /*
  196. * Do not overwrite the console
  197. * Use always serial for U-Boot console
  198. */
  199. int overwrite_console(void)
  200. {
  201. return 1;
  202. }
  203. int checkboard(void)
  204. {
  205. puts("Board: TS4800\n");
  206. return 0;
  207. }
  208. void hw_watchdog_reset(void)
  209. {
  210. struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
  211. /* feed the watchdog for another 10s */
  212. writew(0x2, &wtd->feed);
  213. }
  214. void hw_watchdog_init(void)
  215. {
  216. return;
  217. }