board.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TCL SL50 board
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <spl.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/omap.h>
  16. #include <asm/arch/ddr_defs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/mmc_host_def.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/io.h>
  23. #include <asm/emif.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <cpsw.h>
  28. #include <power/tps65217.h>
  29. #include <power/tps65910.h>
  30. #include <environment.h>
  31. #include <watchdog.h>
  32. #include "board.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  35. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  36. static const struct ddr_data ddr3_sl50_data = {
  37. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  38. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  39. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  40. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  41. };
  42. static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  43. .cmd0csratio = MT41K256M16HA125E_RATIO,
  44. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  45. .cmd1csratio = MT41K256M16HA125E_RATIO,
  46. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  47. .cmd2csratio = MT41K256M16HA125E_RATIO,
  48. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49. };
  50. static struct emif_regs ddr3_sl50_emif_reg_data = {
  51. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  52. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  53. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  54. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  55. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  56. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  57. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  58. };
  59. #ifdef CONFIG_SPL_OS_BOOT
  60. int spl_start_uboot(void)
  61. {
  62. /* break into full u-boot on 'c' */
  63. if (serial_tstc() && serial_getc() == 'c')
  64. return 1;
  65. #ifdef CONFIG_SPL_ENV_SUPPORT
  66. env_init();
  67. env_load();
  68. if (env_get_yesno("boot_os") != 1)
  69. return 1;
  70. #endif
  71. return 0;
  72. }
  73. #endif
  74. #define OSC (V_OSCK/1000000)
  75. const struct dpll_params dpll_ddr_sl50 = {
  76. 400, OSC-1, 1, -1, -1, -1, -1};
  77. void am33xx_spl_board_init(void)
  78. {
  79. int mpu_vdd;
  80. /* Get the frequency */
  81. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  82. /* BeagleBone PMIC Code */
  83. int usb_cur_lim;
  84. if (i2c_probe(TPS65217_CHIP_PM))
  85. return;
  86. /*
  87. * Increase USB current limit to 1300mA or 1800mA and set
  88. * the MPU voltage controller as needed.
  89. */
  90. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  91. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  92. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  93. } else {
  94. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  95. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  96. }
  97. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  98. TPS65217_POWER_PATH,
  99. usb_cur_lim,
  100. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  101. puts("tps65217_reg_write failure\n");
  102. /* Set DCDC3 (CORE) voltage to 1.125V */
  103. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  104. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  105. puts("tps65217_voltage_update failure\n");
  106. return;
  107. }
  108. /* Set CORE Frequencies to OPP100 */
  109. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  110. /* Set DCDC2 (MPU) voltage */
  111. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  112. puts("tps65217_voltage_update failure\n");
  113. return;
  114. }
  115. /*
  116. * Set LDO3 to 1.8V and LDO4 to 3.3V
  117. */
  118. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  119. TPS65217_DEFLS1,
  120. TPS65217_LDO_VOLTAGE_OUT_1_8,
  121. TPS65217_LDO_MASK))
  122. puts("tps65217_reg_write failure\n");
  123. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  124. TPS65217_DEFLS2,
  125. TPS65217_LDO_VOLTAGE_OUT_3_3,
  126. TPS65217_LDO_MASK))
  127. puts("tps65217_reg_write failure\n");
  128. /* Set MPU Frequency to what we detected now that voltages are set */
  129. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  130. }
  131. const struct dpll_params *get_dpll_ddr_params(void)
  132. {
  133. enable_i2c0_pin_mux();
  134. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  135. return &dpll_ddr_sl50;
  136. }
  137. void set_uart_mux_conf(void)
  138. {
  139. #if CONFIG_CONS_INDEX == 1
  140. enable_uart0_pin_mux();
  141. #elif CONFIG_CONS_INDEX == 2
  142. enable_uart1_pin_mux();
  143. #elif CONFIG_CONS_INDEX == 3
  144. enable_uart2_pin_mux();
  145. #elif CONFIG_CONS_INDEX == 4
  146. enable_uart3_pin_mux();
  147. #elif CONFIG_CONS_INDEX == 5
  148. enable_uart4_pin_mux();
  149. #elif CONFIG_CONS_INDEX == 6
  150. enable_uart5_pin_mux();
  151. #endif
  152. }
  153. void set_mux_conf_regs(void)
  154. {
  155. enable_board_pin_mux();
  156. }
  157. const struct ctrl_ioregs ioregs_evmsk = {
  158. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  159. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  160. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  161. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  162. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  163. };
  164. const struct ctrl_ioregs ioregs_bonelt = {
  165. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  166. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  167. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  168. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  169. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  170. };
  171. const struct ctrl_ioregs ioregs_evm15 = {
  172. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  173. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  174. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  175. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  176. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  177. };
  178. const struct ctrl_ioregs ioregs = {
  179. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  180. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  181. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  182. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  183. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  184. };
  185. void sdram_init(void)
  186. {
  187. config_ddr(400, &ioregs_bonelt,
  188. &ddr3_sl50_data,
  189. &ddr3_sl50_cmd_ctrl_data,
  190. &ddr3_sl50_emif_reg_data, 0);
  191. }
  192. #endif
  193. /*
  194. * Basic board specific setup. Pinmux has been handled already.
  195. */
  196. int board_init(void)
  197. {
  198. #if defined(CONFIG_HW_WATCHDOG)
  199. hw_watchdog_init();
  200. #endif
  201. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  202. return 0;
  203. }
  204. #ifdef CONFIG_BOARD_LATE_INIT
  205. int board_late_init(void)
  206. {
  207. return 0;
  208. }
  209. #endif
  210. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  211. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  212. static void cpsw_control(int enabled)
  213. {
  214. /* VTP can be added here */
  215. return;
  216. }
  217. static struct cpsw_slave_data cpsw_slaves[] = {
  218. {
  219. .slave_reg_ofs = 0x208,
  220. .sliver_reg_ofs = 0xd80,
  221. .phy_addr = 0,
  222. },
  223. {
  224. .slave_reg_ofs = 0x308,
  225. .sliver_reg_ofs = 0xdc0,
  226. .phy_addr = 1,
  227. },
  228. };
  229. static struct cpsw_platform_data cpsw_data = {
  230. .mdio_base = CPSW_MDIO_BASE,
  231. .cpsw_base = CPSW_BASE,
  232. .mdio_div = 0xff,
  233. .channels = 8,
  234. .cpdma_reg_ofs = 0x800,
  235. .slaves = 1,
  236. .slave_data = cpsw_slaves,
  237. .ale_reg_ofs = 0xd00,
  238. .ale_entries = 1024,
  239. .host_port_reg_ofs = 0x108,
  240. .hw_stats_reg_ofs = 0x900,
  241. .bd_ram_ofs = 0x2000,
  242. .mac_control = (1 << 5),
  243. .control = cpsw_control,
  244. .host_port_num = 0,
  245. .version = CPSW_CTRL_VERSION_2,
  246. };
  247. #endif
  248. /*
  249. * This function will:
  250. * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  251. * in the environment
  252. * Perform fixups to the PHY present on certain boards. We only need this
  253. * function in:
  254. * - SPL with either CPSW or USB ethernet support
  255. * - Full U-Boot, with either CPSW or USB ethernet
  256. * Build in only these cases to avoid warnings about unused variables
  257. * when we build an SPL that has neither option but full U-Boot will.
  258. */
  259. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
  260. && defined(CONFIG_SPL_BUILD)) || \
  261. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  262. defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
  263. !defined(CONFIG_SPL_BUILD))
  264. int board_eth_init(bd_t *bis)
  265. {
  266. int rv, n = 0;
  267. uint8_t mac_addr[6];
  268. uint32_t mac_hi, mac_lo;
  269. /* try reading mac address from efuse */
  270. mac_lo = readl(&cdev->macid0l);
  271. mac_hi = readl(&cdev->macid0h);
  272. mac_addr[0] = mac_hi & 0xFF;
  273. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  274. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  275. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  276. mac_addr[4] = mac_lo & 0xFF;
  277. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  278. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  279. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  280. if (!env_get("ethaddr")) {
  281. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  282. if (is_valid_ethaddr(mac_addr))
  283. eth_env_set_enetaddr("ethaddr", mac_addr);
  284. }
  285. #ifdef CONFIG_DRIVER_TI_CPSW
  286. mac_lo = readl(&cdev->macid1l);
  287. mac_hi = readl(&cdev->macid1h);
  288. mac_addr[0] = mac_hi & 0xFF;
  289. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  290. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  291. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  292. mac_addr[4] = mac_lo & 0xFF;
  293. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  294. if (!env_get("eth1addr")) {
  295. if (is_valid_ethaddr(mac_addr))
  296. eth_env_set_enetaddr("eth1addr", mac_addr);
  297. }
  298. writel(MII_MODE_ENABLE, &cdev->miisel);
  299. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
  300. PHY_INTERFACE_MODE_MII;
  301. rv = cpsw_register(&cpsw_data);
  302. if (rv < 0)
  303. printf("Error %d registering CPSW switch\n", rv);
  304. else
  305. n += rv;
  306. #endif
  307. /*
  308. *
  309. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  310. * operating points. So we must set the TX clock delay feature
  311. * in the AR8051 PHY. Since we only support a single ethernet
  312. * device in U-Boot, we only do this for the first instance.
  313. */
  314. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  315. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  316. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  317. #define AR8051_RGMII_TX_CLK_DLY 0x100
  318. #endif
  319. #if defined(CONFIG_USB_ETHER) && \
  320. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  321. if (is_valid_ether_addr(mac_addr))
  322. eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
  323. rv = usb_eth_initialize(bis);
  324. if (rv < 0)
  325. printf("Error %d registering USB_ETHER\n", rv);
  326. else
  327. n += rv;
  328. #endif
  329. return n;
  330. }
  331. #endif