sh7757lcr.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <asm/processor.h>
  9. #include <asm/io.h>
  10. #include <asm/mmc.h>
  11. #include <spi.h>
  12. #include <spi_flash.h>
  13. int checkboard(void)
  14. {
  15. puts("BOARD: R0P7757LC0030RL board\n");
  16. return 0;
  17. }
  18. static void init_gctrl(void)
  19. {
  20. struct gctrl_regs *gctrl = GCTRL_BASE;
  21. unsigned long graofst;
  22. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  23. writel(graofst | 0x20000f00, &gctrl->gracr3);
  24. }
  25. static int init_pcie_bridge_from_spi(void *buf, size_t size)
  26. {
  27. #ifdef CONFIG_DEPRECATED
  28. struct spi_flash *spi;
  29. int ret;
  30. unsigned long pcie_addr;
  31. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  32. if (!spi) {
  33. printf("%s: spi_flash probe error.\n", __func__);
  34. return 1;
  35. }
  36. if (is_sh7757_b0())
  37. pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
  38. else
  39. pcie_addr = SH7757LCR_PCIEBRG_ADDR;
  40. ret = spi_flash_read(spi, pcie_addr, size, buf);
  41. if (ret) {
  42. printf("%s: spi_flash read error.\n", __func__);
  43. spi_flash_free(spi);
  44. return 1;
  45. }
  46. spi_flash_free(spi);
  47. return 0;
  48. #else
  49. printf("No SPI support so no PCIe support\n");
  50. return 1;
  51. #endif
  52. }
  53. static void init_pcie_bridge(void)
  54. {
  55. struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
  56. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  57. int i;
  58. unsigned char *data;
  59. unsigned short tmp;
  60. unsigned long pcie_size;
  61. if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
  62. return;
  63. if (is_sh7757_b0())
  64. pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
  65. else
  66. pcie_size = SH7757LCR_PCIEBRG_SIZE;
  67. data = malloc(pcie_size);
  68. if (!data) {
  69. printf("%s: malloc error.\n", __func__);
  70. return;
  71. }
  72. if (init_pcie_bridge_from_spi(data, pcie_size)) {
  73. free(data);
  74. return;
  75. }
  76. if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
  77. data[3] == 0xff) {
  78. free(data);
  79. printf("%s: skipped initialization\n", __func__);
  80. return;
  81. }
  82. writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
  83. writew(0x0000, &pciebrg->cp_ctrl);
  84. writew(0x0000, &pciebrg->cp_addr);
  85. for (i = 0; i < pcie_size; i += 2) {
  86. tmp = (data[i] << 8) | data[i + 1];
  87. writew(tmp, &pciebrg->cp_data);
  88. }
  89. writew(0xa500, &pciebrg->ctrl_h8s); /* start */
  90. if (!is_sh7757_b0())
  91. writel(0x00000001, &pcie_setup->pbictl3);
  92. free(data);
  93. }
  94. static void init_usb_phy(void)
  95. {
  96. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  97. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  98. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  99. struct usb1_port_regs *port = USB1_PORT_BASE;
  100. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  101. writew(0x0100, &phy->reset); /* set reset */
  102. /* port0 = USB0, port1 = USB1 */
  103. writew(0x0002, &phy->portsel);
  104. writel(0x0001, &port->port1sel); /* port1 = Host */
  105. writew(0x0111, &phy->reset); /* clear reset */
  106. writew(0x4000, &common0->suspmode);
  107. writew(0x4000, &common1->suspmode);
  108. #if defined(__LITTLE_ENDIAN)
  109. writel(0x00000000, &align->ehcidatac);
  110. writel(0x00000000, &align->ohcidatac);
  111. #endif
  112. }
  113. static void set_mac_to_sh_eth_register(int channel, char *mac_string)
  114. {
  115. struct ether_mac_regs *ether;
  116. unsigned char mac[6];
  117. unsigned long val;
  118. eth_parse_enetaddr(mac_string, mac);
  119. if (!channel)
  120. ether = ETHER0_MAC_BASE;
  121. else
  122. ether = ETHER1_MAC_BASE;
  123. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  124. writel(val, &ether->mahr);
  125. val = (mac[4] << 8) | mac[5];
  126. writel(val, &ether->malr);
  127. }
  128. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  129. {
  130. struct ether_mac_regs *ether;
  131. unsigned char mac[6];
  132. unsigned long val;
  133. eth_parse_enetaddr(mac_string, mac);
  134. if (!channel)
  135. ether = GETHER0_MAC_BASE;
  136. else
  137. ether = GETHER1_MAC_BASE;
  138. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  139. writel(val, &ether->mahr);
  140. val = (mac[4] << 8) | mac[5];
  141. writel(val, &ether->malr);
  142. }
  143. /*****************************************************************
  144. * This PMB must be set on this timing. The lowlevel_init is run on
  145. * Area 0(phys 0x00000000), so we have to map it.
  146. *
  147. * The new PMB table is following:
  148. * ent virt phys v sz c wt
  149. * 0 0xa0000000 0x40000000 1 128M 0 1
  150. * 1 0xa8000000 0x48000000 1 128M 0 1
  151. * 2 0xb0000000 0x50000000 1 128M 0 1
  152. * 3 0xb8000000 0x58000000 1 128M 0 1
  153. * 4 0x80000000 0x40000000 1 128M 1 1
  154. * 5 0x88000000 0x48000000 1 128M 1 1
  155. * 6 0x90000000 0x50000000 1 128M 1 1
  156. * 7 0x98000000 0x58000000 1 128M 1 1
  157. */
  158. static void set_pmb_on_board_init(void)
  159. {
  160. struct mmu_regs *mmu = MMU_BASE;
  161. /* clear ITLB */
  162. writel(0x00000004, &mmu->mmucr);
  163. /* delete PMB for SPIBOOT */
  164. writel(0, PMB_ADDR_BASE(0));
  165. writel(0, PMB_DATA_BASE(0));
  166. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  167. /* ppn ub v s1 s0 c wt */
  168. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  169. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  170. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  171. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  172. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  173. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  174. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  175. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  176. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  177. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  178. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  179. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  180. }
  181. int board_init(void)
  182. {
  183. struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  184. set_pmb_on_board_init();
  185. /* enable RMII's MDIO (disable GRMII's MDIO) */
  186. writel(0x00030000, &gether->gbecont);
  187. init_gctrl();
  188. init_usb_phy();
  189. return 0;
  190. }
  191. int board_mmc_init(bd_t *bis)
  192. {
  193. return mmcif_mmc_init();
  194. }
  195. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  196. {
  197. #ifdef CONFIG_DEPRECATED
  198. struct spi_flash *spi;
  199. int ret;
  200. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  201. if (spi == NULL) {
  202. printf("%s: spi_flash probe error.\n", __func__);
  203. return 1;
  204. }
  205. ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
  206. if (ret) {
  207. printf("%s: spi_flash read error.\n", __func__);
  208. spi_flash_free(spi);
  209. return 1;
  210. }
  211. spi_flash_free(spi);
  212. #endif
  213. return 0;
  214. }
  215. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  216. {
  217. memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
  218. SH7757LCR_ETHERNET_MAC_SIZE);
  219. mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  220. return 0;
  221. }
  222. static void init_ethernet_mac(void)
  223. {
  224. char mac_string[64];
  225. char env_string[64];
  226. int i;
  227. unsigned char *buf;
  228. buf = malloc(256);
  229. if (!buf) {
  230. printf("%s: malloc error.\n", __func__);
  231. return;
  232. }
  233. get_sh_eth_mac_raw(buf, 256);
  234. /* Fast Ethernet */
  235. for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
  236. get_sh_eth_mac(i, mac_string, buf);
  237. if (i == 0)
  238. env_set("ethaddr", mac_string);
  239. else {
  240. sprintf(env_string, "eth%daddr", i);
  241. env_set(env_string, mac_string);
  242. }
  243. set_mac_to_sh_eth_register(i, mac_string);
  244. }
  245. /* Gigabit Ethernet */
  246. for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
  247. get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
  248. sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
  249. env_set(env_string, mac_string);
  250. set_mac_to_sh_giga_eth_register(i, mac_string);
  251. }
  252. free(buf);
  253. }
  254. static void init_pcie(void)
  255. {
  256. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  257. struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
  258. writel(0x00000ff2, &pcie_setup->ladmsk0);
  259. writel(0x00000001, &pcie_setup->barmap);
  260. writel(0xffcaa000, &pcie_setup->lad0);
  261. writel(0x00030000, &pcie_sysbus->endictl0);
  262. writel(0x00000003, &pcie_sysbus->endictl1);
  263. writel(0x00000004, &pcie_setup->pbictl2);
  264. }
  265. static void finish_spiboot(void)
  266. {
  267. struct gctrl_regs *gctrl = GCTRL_BASE;
  268. /*
  269. * SH7757 B0 does not use LBSC.
  270. * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
  271. * This setting is not cleared by manual reset, So we have to set it
  272. * to 0.
  273. */
  274. writel(0x00000000, &gctrl->spibootcan);
  275. }
  276. int board_late_init(void)
  277. {
  278. init_ethernet_mac();
  279. init_pcie_bridge();
  280. init_pcie();
  281. finish_spiboot();
  282. return 0;
  283. }
  284. int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  285. {
  286. struct gctrl_regs *gctrl = GCTRL_BASE;
  287. unsigned long graofst;
  288. writel(0xfedcba98, &gctrl->wprotect);
  289. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  290. writel(graofst | 0xa0000f00, &gctrl->gracr3);
  291. return 0;
  292. }
  293. U_BOOT_CMD(
  294. sh_g200, 1, 1, do_sh_g200,
  295. "enable sh-g200",
  296. "enable SH-G200 bus (disable PCIe-G200)"
  297. );
  298. #ifdef CONFIG_DEPRECATED
  299. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  300. {
  301. int i, ret;
  302. char mac_string[256];
  303. struct spi_flash *spi;
  304. unsigned char *buf;
  305. if (argc != 5) {
  306. buf = malloc(256);
  307. if (!buf) {
  308. printf("%s: malloc error.\n", __func__);
  309. return 1;
  310. }
  311. get_sh_eth_mac_raw(buf, 256);
  312. /* print current MAC address */
  313. for (i = 0; i < 4; i++) {
  314. get_sh_eth_mac(i, mac_string, buf);
  315. if (i < 2)
  316. printf(" ETHERC ch%d = %s\n", i, mac_string);
  317. else
  318. printf("GETHERC ch%d = %s\n", i-2, mac_string);
  319. }
  320. free(buf);
  321. return 0;
  322. }
  323. /* new setting */
  324. memset(mac_string, 0xff, sizeof(mac_string));
  325. sprintf(mac_string, "%s\t%s\t%s\t%s",
  326. argv[1], argv[2], argv[3], argv[4]);
  327. /* write MAC data to SPI rom */
  328. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  329. if (!spi) {
  330. printf("%s: spi_flash probe error.\n", __func__);
  331. return 1;
  332. }
  333. ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  334. SH7757LCR_SPI_SECTOR_SIZE);
  335. if (ret) {
  336. printf("%s: spi_flash erase error.\n", __func__);
  337. return 1;
  338. }
  339. ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  340. sizeof(mac_string), mac_string);
  341. if (ret) {
  342. printf("%s: spi_flash write error.\n", __func__);
  343. spi_flash_free(spi);
  344. return 1;
  345. }
  346. spi_flash_free(spi);
  347. puts("The writing of the MAC address to SPI ROM was completed.\n");
  348. return 0;
  349. }
  350. U_BOOT_CMD(
  351. write_mac, 5, 1, do_write_mac,
  352. "write MAC address for ETHERC/GETHERC",
  353. "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
  354. );
  355. #endif