sh7752evb.c 7.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <asm/processor.h>
  9. #include <asm/io.h>
  10. #include <asm/mmc.h>
  11. #include <spi.h>
  12. #include <spi_flash.h>
  13. int checkboard(void)
  14. {
  15. puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
  16. return 0;
  17. }
  18. static void init_gpio(void)
  19. {
  20. struct gpio_regs *gpio = GPIO_BASE;
  21. struct sermux_regs *sermux = SERMUX_BASE;
  22. /* GPIO */
  23. writew(0x0000, &gpio->pacr); /* GETHER */
  24. writew(0x0001, &gpio->pbcr); /* INTC */
  25. writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  26. writew(0xeaff, &gpio->pecr); /* GPIO */
  27. writew(0x0000, &gpio->pfcr); /* WDT */
  28. writew(0x0000, &gpio->phcr); /* SPI1 */
  29. writew(0x0000, &gpio->picr); /* SDHI */
  30. writew(0x0003, &gpio->pkcr); /* SerMux */
  31. writew(0x0000, &gpio->plcr); /* SerMux */
  32. writew(0x0000, &gpio->pmcr); /* RIIC */
  33. writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  34. writew(0x0000, &gpio->pocr); /* SGPIO */
  35. writew(0xd555, &gpio->pqcr); /* GPIO */
  36. writew(0x0000, &gpio->prcr); /* RIIC */
  37. writew(0x0000, &gpio->pscr); /* RIIC */
  38. writeb(0x00, &gpio->pudr);
  39. writew(0x5555, &gpio->pucr); /* Debug LED */
  40. writew(0x0000, &gpio->pvcr); /* RSPI */
  41. writew(0x0000, &gpio->pwcr); /* EVC */
  42. writew(0x0000, &gpio->pxcr); /* LBSC */
  43. writew(0x0000, &gpio->pycr); /* LBSC */
  44. writew(0x0000, &gpio->pzcr); /* eMMC */
  45. writew(0xfe00, &gpio->psel0);
  46. writew(0xff00, &gpio->psel3);
  47. writew(0x771f, &gpio->psel4);
  48. writew(0x00ff, &gpio->psel6);
  49. writew(0xfc00, &gpio->psel7);
  50. writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  51. }
  52. static void init_usb_phy(void)
  53. {
  54. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  55. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  56. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  57. struct usb1_port_regs *port = USB1_PORT_BASE;
  58. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  59. writew(0x0100, &phy->reset); /* set reset */
  60. /* port0 = USB0, port1 = USB1 */
  61. writew(0x0002, &phy->portsel);
  62. writel(0x0001, &port->port1sel); /* port1 = Host */
  63. writew(0x0111, &phy->reset); /* clear reset */
  64. writew(0x4000, &common0->suspmode);
  65. writew(0x4000, &common1->suspmode);
  66. #if defined(__LITTLE_ENDIAN)
  67. writel(0x00000000, &align->ehcidatac);
  68. writel(0x00000000, &align->ohcidatac);
  69. #endif
  70. }
  71. static void init_gether_mdio(void)
  72. {
  73. struct gpio_regs *gpio = GPIO_BASE;
  74. writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  75. writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  76. }
  77. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  78. {
  79. struct ether_mac_regs *ether;
  80. unsigned char mac[6];
  81. unsigned long val;
  82. eth_parse_enetaddr(mac_string, mac);
  83. if (!channel)
  84. ether = GETHER0_MAC_BASE;
  85. else
  86. ether = GETHER1_MAC_BASE;
  87. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  88. writel(val, &ether->mahr);
  89. val = (mac[4] << 8) | mac[5];
  90. writel(val, &ether->malr);
  91. }
  92. /*****************************************************************
  93. * This PMB must be set on this timing. The lowlevel_init is run on
  94. * Area 0(phys 0x00000000), so we have to map it.
  95. *
  96. * The new PMB table is following:
  97. * ent virt phys v sz c wt
  98. * 0 0xa0000000 0x40000000 1 128M 0 1
  99. * 1 0xa8000000 0x48000000 1 128M 0 1
  100. * 2 0xb0000000 0x50000000 1 128M 0 1
  101. * 3 0xb8000000 0x58000000 1 128M 0 1
  102. * 4 0x80000000 0x40000000 1 128M 1 1
  103. * 5 0x88000000 0x48000000 1 128M 1 1
  104. * 6 0x90000000 0x50000000 1 128M 1 1
  105. * 7 0x98000000 0x58000000 1 128M 1 1
  106. */
  107. static void set_pmb_on_board_init(void)
  108. {
  109. struct mmu_regs *mmu = MMU_BASE;
  110. /* clear ITLB */
  111. writel(0x00000004, &mmu->mmucr);
  112. /* delete PMB for SPIBOOT */
  113. writel(0, PMB_ADDR_BASE(0));
  114. writel(0, PMB_DATA_BASE(0));
  115. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  116. /* ppn ub v s1 s0 c wt */
  117. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  118. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  119. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  120. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  121. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  122. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  123. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  124. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  125. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  126. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  127. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  128. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  129. }
  130. int board_init(void)
  131. {
  132. init_gpio();
  133. set_pmb_on_board_init();
  134. init_usb_phy();
  135. init_gether_mdio();
  136. return 0;
  137. }
  138. int board_mmc_init(bd_t *bis)
  139. {
  140. struct gpio_regs *gpio = GPIO_BASE;
  141. writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  142. writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  143. udelay(1);
  144. writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  145. udelay(200);
  146. return mmcif_mmc_init();
  147. }
  148. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  149. {
  150. #ifdef CONFIG_DEPRECATED
  151. struct spi_flash *spi;
  152. int ret;
  153. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  154. if (spi == NULL) {
  155. printf("%s: spi_flash probe failed.\n", __func__);
  156. return 1;
  157. }
  158. ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
  159. if (ret) {
  160. printf("%s: spi_flash read failed.\n", __func__);
  161. spi_flash_free(spi);
  162. return 1;
  163. }
  164. spi_flash_free(spi);
  165. #endif
  166. return 0;
  167. }
  168. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  169. {
  170. memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
  171. SH7752EVB_ETHERNET_MAC_SIZE);
  172. mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  173. return 0;
  174. }
  175. static void init_ethernet_mac(void)
  176. {
  177. char mac_string[64];
  178. char env_string[64];
  179. int i;
  180. unsigned char *buf;
  181. buf = malloc(256);
  182. if (!buf) {
  183. printf("%s: malloc failed.\n", __func__);
  184. return;
  185. }
  186. get_sh_eth_mac_raw(buf, 256);
  187. /* Gigabit Ethernet */
  188. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  189. get_sh_eth_mac(i, mac_string, buf);
  190. if (i == 0)
  191. env_set("ethaddr", mac_string);
  192. else {
  193. sprintf(env_string, "eth%daddr", i);
  194. env_set(env_string, mac_string);
  195. }
  196. set_mac_to_sh_giga_eth_register(i, mac_string);
  197. }
  198. free(buf);
  199. }
  200. int board_late_init(void)
  201. {
  202. init_ethernet_mac();
  203. return 0;
  204. }
  205. #ifdef CONFIG_DEPRECATED
  206. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  207. {
  208. int i, ret;
  209. char mac_string[256];
  210. struct spi_flash *spi;
  211. unsigned char *buf;
  212. if (argc != 3) {
  213. buf = malloc(256);
  214. if (!buf) {
  215. printf("%s: malloc failed.\n", __func__);
  216. return 1;
  217. }
  218. get_sh_eth_mac_raw(buf, 256);
  219. /* print current MAC address */
  220. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  221. get_sh_eth_mac(i, mac_string, buf);
  222. printf("GETHERC ch%d = %s\n", i, mac_string);
  223. }
  224. free(buf);
  225. return 0;
  226. }
  227. /* new setting */
  228. memset(mac_string, 0xff, sizeof(mac_string));
  229. sprintf(mac_string, "%s\t%s",
  230. argv[1], argv[2]);
  231. /* write MAC data to SPI rom */
  232. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  233. if (!spi) {
  234. printf("%s: spi_flash probe failed.\n", __func__);
  235. return 1;
  236. }
  237. ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  238. SH7752EVB_SPI_SECTOR_SIZE);
  239. if (ret) {
  240. printf("%s: spi_flash erase failed.\n", __func__);
  241. return 1;
  242. }
  243. ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  244. sizeof(mac_string), mac_string);
  245. if (ret) {
  246. printf("%s: spi_flash write failed.\n", __func__);
  247. spi_flash_free(spi);
  248. return 1;
  249. }
  250. spi_flash_free(spi);
  251. puts("The writing of the MAC address to SPI ROM was completed.\n");
  252. return 0;
  253. }
  254. U_BOOT_CMD(
  255. write_mac, 3, 1, do_write_mac,
  256. "write MAC address for GETHERC",
  257. "[GETHERC ch0] [GETHERC ch1]\n"
  258. );
  259. #endif