board.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
  6. *
  7. * Copyright (C) 2013 Lemonage Software GmbH
  8. * Author Lars Poeschel <poeschel@lemonage.de>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <spl.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/omap.h>
  17. #include <asm/arch/ddr_defs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/mmc_host_def.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/io.h>
  23. #include <asm/emif.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <cpsw.h>
  28. #include "board.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /* MII mode defines */
  31. #define RMII_RGMII2_MODE_ENABLE 0x49
  32. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  33. #ifdef CONFIG_SPL_BUILD
  34. /* DDR RAM defines */
  35. #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
  36. #define OSC (V_OSCK/1000000)
  37. const struct dpll_params dpll_ddr = {
  38. DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
  39. const struct dpll_params *get_dpll_ddr_params(void)
  40. {
  41. return &dpll_ddr;
  42. }
  43. #ifdef CONFIG_REV1
  44. const struct ctrl_ioregs ioregs = {
  45. .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  46. .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  47. .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  48. .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  49. .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  50. };
  51. static const struct ddr_data ddr3_data = {
  52. .datardsratio0 = MT41J256M8HX15E_RD_DQS,
  53. .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  54. .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
  55. .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
  56. };
  57. static const struct cmd_control ddr3_cmd_ctrl_data = {
  58. .cmd0csratio = MT41J256M8HX15E_RATIO,
  59. .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  60. .cmd1csratio = MT41J256M8HX15E_RATIO,
  61. .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  62. .cmd2csratio = MT41J256M8HX15E_RATIO,
  63. .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  64. };
  65. static struct emif_regs ddr3_emif_reg_data = {
  66. .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
  67. .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
  68. .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
  69. .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
  70. .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
  71. .zq_config = MT41J256M8HX15E_ZQ_CFG,
  72. .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
  73. PHY_EN_DYN_PWRDN,
  74. };
  75. void sdram_init(void)
  76. {
  77. config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  78. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  79. }
  80. #else
  81. const struct ctrl_ioregs ioregs = {
  82. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  83. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  84. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  85. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  86. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  87. };
  88. static const struct ddr_data ddr3_data = {
  89. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  90. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  91. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  92. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  93. };
  94. static const struct cmd_control ddr3_cmd_ctrl_data = {
  95. .cmd0csratio = MT41K256M16HA125E_RATIO,
  96. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  97. .cmd1csratio = MT41K256M16HA125E_RATIO,
  98. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  99. .cmd2csratio = MT41K256M16HA125E_RATIO,
  100. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  101. };
  102. static struct emif_regs ddr3_emif_reg_data = {
  103. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  104. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  105. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  106. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  107. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  108. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  109. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  110. PHY_EN_DYN_PWRDN,
  111. };
  112. void sdram_init(void)
  113. {
  114. config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  115. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  116. }
  117. #endif
  118. void set_uart_mux_conf(void)
  119. {
  120. enable_uart0_pin_mux();
  121. }
  122. void set_mux_conf_regs(void)
  123. {
  124. /* Initalize the board header */
  125. enable_i2c0_pin_mux();
  126. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  127. enable_board_pin_mux();
  128. }
  129. #endif
  130. /*
  131. * Basic board specific setup. Pinmux has been handled already.
  132. */
  133. int board_init(void)
  134. {
  135. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  136. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  137. return 0;
  138. }
  139. #ifdef CONFIG_DRIVER_TI_CPSW
  140. static void cpsw_control(int enabled)
  141. {
  142. /* VTP can be added here */
  143. return;
  144. }
  145. static struct cpsw_slave_data cpsw_slaves[] = {
  146. {
  147. .slave_reg_ofs = 0x208,
  148. .sliver_reg_ofs = 0xd80,
  149. .phy_addr = 0,
  150. .phy_if = PHY_INTERFACE_MODE_RGMII,
  151. },
  152. {
  153. .slave_reg_ofs = 0x308,
  154. .sliver_reg_ofs = 0xdc0,
  155. .phy_addr = 1,
  156. .phy_if = PHY_INTERFACE_MODE_RGMII,
  157. },
  158. };
  159. static struct cpsw_platform_data cpsw_data = {
  160. .mdio_base = CPSW_MDIO_BASE,
  161. .cpsw_base = CPSW_BASE,
  162. .mdio_div = 0xff,
  163. .channels = 8,
  164. .cpdma_reg_ofs = 0x800,
  165. .slaves = 1,
  166. .slave_data = cpsw_slaves,
  167. .ale_reg_ofs = 0xd00,
  168. .ale_entries = 1024,
  169. .host_port_reg_ofs = 0x108,
  170. .hw_stats_reg_ofs = 0x900,
  171. .bd_ram_ofs = 0x2000,
  172. .mac_control = (1 << 5),
  173. .control = cpsw_control,
  174. .host_port_num = 0,
  175. .version = CPSW_CTRL_VERSION_2,
  176. };
  177. #endif
  178. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  179. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  180. int board_eth_init(bd_t *bis)
  181. {
  182. int rv, n = 0;
  183. #ifdef CONFIG_DRIVER_TI_CPSW
  184. uint8_t mac_addr[6];
  185. uint32_t mac_hi, mac_lo;
  186. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  187. printf("<ethaddr> not set. Reading from E-fuse\n");
  188. /* try reading mac address from efuse */
  189. mac_lo = readl(&cdev->macid0l);
  190. mac_hi = readl(&cdev->macid0h);
  191. mac_addr[0] = mac_hi & 0xFF;
  192. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  193. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  194. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  195. mac_addr[4] = mac_lo & 0xFF;
  196. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  197. if (is_valid_ethaddr(mac_addr))
  198. eth_env_set_enetaddr("ethaddr", mac_addr);
  199. else
  200. goto try_usbether;
  201. }
  202. writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
  203. rv = cpsw_register(&cpsw_data);
  204. if (rv < 0)
  205. printf("Error %d registering CPSW switch\n", rv);
  206. else
  207. n += rv;
  208. try_usbether:
  209. #endif
  210. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
  211. rv = usb_eth_initialize(bis);
  212. if (rv < 0)
  213. printf("Error %d registering USB_ETHER\n", rv);
  214. else
  215. n += rv;
  216. #endif
  217. return n;
  218. }
  219. #endif