spl.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <spl.h>
  9. #include <linux/libfdt.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include "asm/arch/crm_regs.h"
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include "asm/arch/iomux.h"
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/gpio.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <netdev.h>
  22. #include <bootcount.h>
  23. #include <watchdog.h>
  24. #include "common.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  27. .dram_sdclk_0 = 0x00000030,
  28. .dram_sdclk_1 = 0x00000030,
  29. .dram_cas = 0x00000030,
  30. .dram_ras = 0x00000030,
  31. .dram_reset = 0x00000030,
  32. .dram_sdcke0 = 0x00003000,
  33. .dram_sdcke1 = 0x00003000,
  34. .dram_sdba2 = 0x00000000,
  35. .dram_sdodt0 = 0x00000030,
  36. .dram_sdodt1 = 0x00000030,
  37. .dram_sdqs0 = 0x00000030,
  38. .dram_sdqs1 = 0x00000030,
  39. .dram_sdqs2 = 0x00000030,
  40. .dram_sdqs3 = 0x00000030,
  41. .dram_sdqs4 = 0x00000030,
  42. .dram_sdqs5 = 0x00000030,
  43. .dram_sdqs6 = 0x00000030,
  44. .dram_sdqs7 = 0x00000030,
  45. .dram_dqm0 = 0x00000030,
  46. .dram_dqm1 = 0x00000030,
  47. .dram_dqm2 = 0x00000030,
  48. .dram_dqm3 = 0x00000030,
  49. .dram_dqm4 = 0x00000030,
  50. .dram_dqm5 = 0x00000030,
  51. .dram_dqm6 = 0x00000030,
  52. .dram_dqm7 = 0x00000030,
  53. };
  54. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  55. .grp_ddr_type = 0x000c0000,
  56. .grp_ddrmode_ctl = 0x00020000,
  57. .grp_ddrpke = 0x00000000,
  58. .grp_addds = 0x00000030,
  59. .grp_ctlds = 0x00000030,
  60. .grp_ddrmode = 0x00020000,
  61. .grp_b0ds = 0x00000030,
  62. .grp_b1ds = 0x00000030,
  63. .grp_b2ds = 0x00000030,
  64. .grp_b3ds = 0x00000030,
  65. .grp_b4ds = 0x00000030,
  66. .grp_b5ds = 0x00000030,
  67. .grp_b6ds = 0x00000030,
  68. .grp_b7ds = 0x00000030,
  69. };
  70. /* 4x128Mx16.cfg */
  71. static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  72. .p0_mpwldectrl0 = 0x002D0028,
  73. .p0_mpwldectrl1 = 0x0032002D,
  74. .p1_mpwldectrl0 = 0x00210036,
  75. .p1_mpwldectrl1 = 0x0019002E,
  76. .p0_mpdgctrl0 = 0x4349035C,
  77. .p0_mpdgctrl1 = 0x0348033D,
  78. .p1_mpdgctrl0 = 0x43550362,
  79. .p1_mpdgctrl1 = 0x03520316,
  80. .p0_mprddlctl = 0x41393940,
  81. .p1_mprddlctl = 0x3F3A3C47,
  82. .p0_mpwrdlctl = 0x413A423A,
  83. .p1_mpwrdlctl = 0x4042483E,
  84. };
  85. /* MT41K128M16JT-125 (2Gb density) */
  86. static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  87. .mem_speed = 1600,
  88. .density = 2,
  89. .width = 16,
  90. .banks = 8,
  91. .rowaddr = 14,
  92. .coladdr = 10,
  93. .pagesz = 2,
  94. .trcd = 1375,
  95. .trcmin = 4875,
  96. .trasmin = 3500,
  97. };
  98. static void ccgr_init(void)
  99. {
  100. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  101. writel(0x00C03F3F, &ccm->CCGR0);
  102. writel(0x0030FC3F, &ccm->CCGR1);
  103. writel(0x0FFFCFC0, &ccm->CCGR2);
  104. writel(0x3FF00000, &ccm->CCGR3);
  105. writel(0x00FFF300, &ccm->CCGR4);
  106. writel(0x0F0000C3, &ccm->CCGR5);
  107. writel(0x000003FF, &ccm->CCGR6);
  108. }
  109. #ifdef CONFIG_MX6_DDRCAL
  110. static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
  111. {
  112. struct mx6_mmdc_calibration calibration = {0};
  113. mmdc_read_calibration(sysinfo, &calibration);
  114. debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
  115. debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
  116. debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
  117. debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
  118. debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
  119. debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
  120. debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
  121. debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
  122. debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
  123. debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
  124. debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
  125. debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
  126. }
  127. static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  128. {
  129. int ret;
  130. /* Perform DDR DRAM calibration */
  131. udelay(100);
  132. ret = mmdc_do_write_level_calibration(sysinfo);
  133. if (ret) {
  134. printf("DDR: Write level calibration error [%d]\n", ret);
  135. return;
  136. }
  137. ret = mmdc_do_dqs_calibration(sysinfo);
  138. if (ret) {
  139. printf("DDR: DQS calibration error [%d]\n", ret);
  140. return;
  141. }
  142. spl_dram_print_cal(sysinfo);
  143. }
  144. #endif /* CONFIG_MX6_DDRCAL */
  145. static void spl_dram_init(void)
  146. {
  147. struct mx6_ddr_sysinfo sysinfo = {
  148. /* width of data bus:0=16,1=32,2=64 */
  149. .dsize = 2,
  150. /* config for full 4GB range so that get_mem_size() works */
  151. .cs_density = 32, /* 32Gb per CS */
  152. /* single chip select */
  153. .ncs = 1,
  154. .cs1_mirror = 0,
  155. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  156. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  157. .walat = 1, /* Write additional latency */
  158. .ralat = 5, /* Read additional latency */
  159. .mif3_mode = 3, /* Command prediction working mode */
  160. .bi_on = 1, /* Bank interleaving enabled */
  161. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  162. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  163. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  164. .ddr_type = DDR_TYPE_DDR3,
  165. .refsel = 1, /* Refresh cycles at 32KHz */
  166. .refr = 7, /* 8 refresh commands per refresh cycle */
  167. };
  168. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  169. mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
  170. #ifdef CONFIG_MX6_DDRCAL
  171. spl_dram_perform_cal(&sysinfo);
  172. #endif
  173. }
  174. #ifdef CONFIG_SPL_SPI_SUPPORT
  175. static void displ5_init_ecspi(void)
  176. {
  177. displ5_set_iomux_ecspi_spl();
  178. enable_spi_clk(1, 1);
  179. }
  180. #else
  181. static inline void displ5_init_ecspi(void) { }
  182. #endif
  183. #ifdef CONFIG_SPL_MMC_SUPPORT
  184. static struct fsl_esdhc_cfg usdhc_cfg = {
  185. .esdhc_base = USDHC4_BASE_ADDR,
  186. .max_bus_width = 8,
  187. };
  188. int board_mmc_init(bd_t *bd)
  189. {
  190. displ5_set_iomux_usdhc_spl();
  191. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  192. gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
  193. return fsl_esdhc_initialize(bd, &usdhc_cfg);
  194. }
  195. #endif
  196. void board_init_f(ulong dummy)
  197. {
  198. ccgr_init();
  199. arch_cpu_init();
  200. gpr_init();
  201. /* setup GP timer */
  202. timer_init();
  203. displ5_set_iomux_uart_spl();
  204. /* UART clocks enabled and gd valid - init serial console */
  205. preloader_console_init();
  206. displ5_init_ecspi();
  207. /* DDR initialization */
  208. spl_dram_init();
  209. /* Clear the BSS. */
  210. memset(__bss_start, 0, __bss_end - __bss_start);
  211. displ5_set_iomux_misc_spl();
  212. /* Initialize and reset WDT in SPL */
  213. hw_watchdog_init();
  214. WATCHDOG_RESET();
  215. /* load/boot image from boot device */
  216. board_init_r(NULL, 0);
  217. }
  218. #define EM_PAD IMX_GPIO_NR(3, 29)
  219. int board_check_emergency_pad(void)
  220. {
  221. int ret;
  222. ret = gpio_direction_input(EM_PAD);
  223. if (ret)
  224. return ret;
  225. return !gpio_get_value(EM_PAD);
  226. }
  227. void board_boot_order(u32 *spl_boot_list)
  228. {
  229. /* Default boot sequence SPI -> MMC */
  230. spl_boot_list[0] = spl_boot_device();
  231. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  232. spl_boot_list[2] = BOOT_DEVICE_UART;
  233. spl_boot_list[3] = BOOT_DEVICE_NONE;
  234. /*
  235. * In case of emergency PAD pressed, we always boot
  236. * to proper u-boot and perform recovery tasks there.
  237. */
  238. if (board_check_emergency_pad())
  239. return;
  240. #ifdef CONFIG_SPL_ENV_SUPPORT
  241. /* 'fastboot' */
  242. const char *s;
  243. if (env_init() || env_load())
  244. return;
  245. s = env_get("BOOT_FROM");
  246. if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
  247. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  248. spl_boot_list[1] = spl_boot_device();
  249. }
  250. #endif
  251. }
  252. void reset_cpu(ulong addr) {}
  253. #ifdef CONFIG_SPL_LOAD_FIT
  254. int board_fit_config_name_match(const char *name)
  255. {
  256. return 0;
  257. }
  258. #endif
  259. #ifdef CONFIG_SPL_OS_BOOT
  260. /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
  261. int spl_start_uboot(void)
  262. {
  263. /* break into full u-boot on 'c' */
  264. if (serial_tstc() && serial_getc() == 'c')
  265. return 1;
  266. #ifdef CONFIG_SPL_ENV_SUPPORT
  267. if (env_get_yesno("boot_os") != 1)
  268. return 1;
  269. #endif
  270. return 0;
  271. }
  272. #endif