display5.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <env.h>
  16. #include <errno.h>
  17. #include <asm/gpio.h>
  18. #include <malloc.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <asm/mach-imx/spi.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <miiphy.h>
  26. #include <netdev.h>
  27. #include <i2c.h>
  28. #include <dm.h>
  29. #include <dm/platform_data/serial_mxc.h>
  30. #include <dm/platdata.h>
  31. #ifndef CONFIG_MXC_SPI
  32. #error "CONFIG_SPI must be set for this board"
  33. #error "Please check your config file"
  34. #endif
  35. #include "common.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static bool hw_ids_valid;
  38. static bool sw_ids_valid;
  39. static u32 cpu_id;
  40. static u32 unit_id;
  41. #define EM_PAD IMX_GPIO_NR(3, 29)
  42. #define SW0 IMX_GPIO_NR(2, 4)
  43. #define SW1 IMX_GPIO_NR(2, 5)
  44. #define SW2 IMX_GPIO_NR(2, 6)
  45. #define SW3 IMX_GPIO_NR(2, 7)
  46. #define HW0 IMX_GPIO_NR(6, 7)
  47. #define HW1 IMX_GPIO_NR(6, 9)
  48. #define HW2 IMX_GPIO_NR(6, 10)
  49. #define HW3 IMX_GPIO_NR(6, 11)
  50. #define HW4 IMX_GPIO_NR(4, 7)
  51. #define HW5 IMX_GPIO_NR(4, 11)
  52. #define HW6 IMX_GPIO_NR(4, 13)
  53. #define HW7 IMX_GPIO_NR(4, 15)
  54. int gpio_table_sw_ids[] = {
  55. SW0, SW1, SW2, SW3
  56. };
  57. const char *gpio_table_sw_ids_names[] = {
  58. "sw0", "sw1", "sw2", "sw3"
  59. };
  60. int gpio_table_hw_ids[] = {
  61. HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
  62. };
  63. const char *gpio_table_hw_ids_names[] = {
  64. "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
  65. };
  66. static int get_board_id(int *ids, const char **c, int size,
  67. bool *valid, u32 *id)
  68. {
  69. int i, ret, val;
  70. *valid = false;
  71. for (i = 0; i < size; i++) {
  72. ret = gpio_request(ids[i], c[i]);
  73. if (ret) {
  74. printf("Can't request SWx gpios\n");
  75. return ret;
  76. }
  77. }
  78. for (i = 0; i < size; i++) {
  79. ret = gpio_direction_input(ids[i]);
  80. if (ret) {
  81. printf("Can't set SWx gpios direction\n");
  82. return ret;
  83. }
  84. }
  85. for (i = 0; i < size; i++) {
  86. val = gpio_get_value(ids[i]);
  87. if (val < 0) {
  88. printf("Can't get SW%d ID\n", i);
  89. *id = 0;
  90. return val;
  91. }
  92. *id |= val << i;
  93. }
  94. *valid = true;
  95. return 0;
  96. }
  97. int dram_init(void)
  98. {
  99. gd->ram_size = imx_ddr_size();
  100. return 0;
  101. }
  102. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  103. /* I2C1: TFA9879 */
  104. struct i2c_pads_info i2c_pad_info0 = {
  105. .scl = {
  106. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  107. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  108. .gp = IMX_GPIO_NR(3, 21)
  109. },
  110. .sda = {
  111. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  112. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  113. .gp = IMX_GPIO_NR(3, 28)
  114. }
  115. };
  116. /* I2C2: TIVO TM4C123 */
  117. struct i2c_pads_info i2c_pad_info1 = {
  118. .scl = {
  119. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  120. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  121. .gp = IMX_GPIO_NR(2, 30)
  122. },
  123. .sda = {
  124. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  125. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  126. .gp = IMX_GPIO_NR(3, 16)
  127. }
  128. };
  129. /* I2C3: PMIC PF0100, EEPROM AT24C256C */
  130. struct i2c_pads_info i2c_pad_info2 = {
  131. .scl = {
  132. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  133. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  134. .gp = IMX_GPIO_NR(3, 17)
  135. },
  136. .sda = {
  137. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  138. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  139. .gp = IMX_GPIO_NR(3, 18)
  140. }
  141. };
  142. iomux_v3_cfg_t const misc_pads[] = {
  143. /* Prod ID GPIO pins */
  144. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  145. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  146. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  147. MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  148. /* HW revision GPIO pins */
  149. MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  150. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  151. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  152. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  153. MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  154. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155. MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  157. /* XTALOSC */
  158. MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
  159. /* Emergency recovery pin */
  160. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  161. };
  162. #ifdef CONFIG_FSL_ESDHC_IMX
  163. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  164. { USDHC4_BASE_ADDR, 0, 8, },
  165. };
  166. int board_mmc_getcd(struct mmc *mmc)
  167. {
  168. return 1;
  169. }
  170. int board_mmc_init(bd_t *bis)
  171. {
  172. displ5_set_iomux_usdhc();
  173. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  174. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  175. }
  176. #endif /* CONFIG_FSL_ESDHC_IMX */
  177. static void displ5_setup_ecspi(void)
  178. {
  179. int ret;
  180. displ5_set_iomux_ecspi();
  181. ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
  182. if (!ret)
  183. gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
  184. ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
  185. if (!ret)
  186. gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
  187. }
  188. #ifdef CONFIG_FEC_MXC
  189. iomux_v3_cfg_t const enet_pads[] = {
  190. MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  191. MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
  192. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  193. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  194. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  195. /* for old evalboard with R159 present and R160 not populated */
  196. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  197. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  198. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  199. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  200. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  201. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  202. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  203. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  204. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  205. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  206. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  207. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  208. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  209. /*INT#_GBE*/
  210. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  211. };
  212. static void setup_iomux_enet(void)
  213. {
  214. SETUP_IOMUX_PADS(enet_pads);
  215. gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
  216. }
  217. static int setup_mac_from_fuse(void)
  218. {
  219. unsigned char enetaddr[6];
  220. int ret;
  221. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  222. if (ret) /* ethaddr is already set */
  223. return 0;
  224. imx_get_mac_from_fuse(0, enetaddr);
  225. if (is_valid_ethaddr(enetaddr)) {
  226. eth_env_set_enetaddr("ethaddr", enetaddr);
  227. return 0;
  228. }
  229. return 0;
  230. }
  231. int board_eth_init(bd_t *bd)
  232. {
  233. struct phy_device *phydev;
  234. struct mii_dev *bus;
  235. int ret;
  236. setup_iomux_enet();
  237. iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
  238. ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  239. if (ret)
  240. return ret;
  241. setup_mac_from_fuse();
  242. bus = fec_get_miibus(IMX_FEC_BASE, -1);
  243. if (!bus)
  244. return -ENODEV;
  245. /*
  246. * We use here the "rgmii-id" mode of operation and allow M88E1512
  247. * PHY to use its internally callibrated RX/TX delays
  248. */
  249. phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
  250. PHY_INTERFACE_MODE_RGMII_ID);
  251. if (!phydev) {
  252. ret = -ENODEV;
  253. goto err_phy;
  254. }
  255. /* display5 due to PCB routing can only work with 100 Mbps */
  256. phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
  257. ADVERTISED_1000baseX_Full |
  258. SUPPORTED_1000baseT_Half |
  259. SUPPORTED_1000baseT_Full);
  260. ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
  261. if (ret)
  262. goto err_sw;
  263. return 0;
  264. err_sw:
  265. free(phydev);
  266. err_phy:
  267. mdio_unregister(bus);
  268. free(bus);
  269. return ret;
  270. }
  271. #endif /* CONFIG_FEC_MXC */
  272. /*
  273. * Do not overwrite the console
  274. * Always use serial for U-Boot console
  275. */
  276. int overwrite_console(void)
  277. {
  278. return 1;
  279. }
  280. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  281. int ft_board_setup(void *blob, bd_t *bd)
  282. {
  283. fdt_fixup_ethernet(blob);
  284. return 0;
  285. }
  286. #endif
  287. int board_init(void)
  288. {
  289. debug("board init\n");
  290. /* address of boot parameters */
  291. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  292. /* Setup iomux for non console UARTS */
  293. displ5_set_iomux_uart();
  294. displ5_setup_ecspi();
  295. SETUP_IOMUX_PADS(misc_pads);
  296. get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
  297. ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
  298. debug("SWx unit_id 0x%x\n", unit_id);
  299. get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
  300. ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
  301. debug("HWx cpu_id 0x%x\n", cpu_id);
  302. if (hw_ids_valid && sw_ids_valid)
  303. printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
  304. udelay(25);
  305. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  306. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  307. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  308. return 0;
  309. }
  310. #ifdef CONFIG_CMD_BMODE
  311. static const struct boot_mode board_boot_modes[] = {
  312. /* eMMC, USDHC-4, 8-bit bus width */
  313. /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
  314. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  315. {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
  316. {NULL, 0},
  317. };
  318. static void setup_boot_modes(void)
  319. {
  320. add_board_boot_modes(board_boot_modes);
  321. }
  322. #else
  323. static inline void setup_boot_modes(void) {}
  324. #endif
  325. int misc_init_r(void)
  326. {
  327. int ret;
  328. setup_boot_modes();
  329. ret = gpio_request(EM_PAD, "Emergency_PAD");
  330. if (ret) {
  331. printf("Can't request emergency PAD gpio\n");
  332. return ret;
  333. }
  334. ret = gpio_direction_input(EM_PAD);
  335. if (ret) {
  336. printf("Can't set emergency PAD direction\n");
  337. return ret;
  338. }
  339. return 0;
  340. }