board.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
  4. *
  5. * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <spl.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/omap.h>
  14. #include <asm/arch/ddr_defs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/mmc_host_def.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/io.h>
  20. #include <asm/emif.h>
  21. #include <asm/gpio.h>
  22. #include <i2c.h>
  23. #include <miiphy.h>
  24. #include <cpsw.h>
  25. #include <fdt_support.h>
  26. #include <mtd_node.h>
  27. #include <jffs2/load_kernel.h>
  28. #include "board.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  31. * and control IGEP0034 green and red LEDs.
  32. * U-boot configures these pins as input pullup to detect board revision:
  33. * IGEP0034-LITE = 0b00
  34. * IGEP0034 (FULL) = 0b01
  35. * IGEP0033 = 0b1X
  36. */
  37. #define GPIO_GREEN_REVISION 27
  38. #define GPIO_RED_REVISION 26
  39. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40. /*
  41. * Routine: get_board_revision
  42. * Description: Returns the board revision
  43. */
  44. static int get_board_revision(void)
  45. {
  46. int revision;
  47. gpio_request(GPIO_GREEN_REVISION, "green_revision");
  48. gpio_direction_input(GPIO_GREEN_REVISION);
  49. revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  50. gpio_free(GPIO_GREEN_REVISION);
  51. gpio_request(GPIO_RED_REVISION, "red_revision");
  52. gpio_direction_input(GPIO_RED_REVISION);
  53. revision = revision + gpio_get_value(GPIO_RED_REVISION);
  54. gpio_free(GPIO_RED_REVISION);
  55. return revision;
  56. }
  57. #ifdef CONFIG_SPL_BUILD
  58. /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  59. static const struct ddr_data ddr3_igep0034_data = {
  60. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  61. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  62. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  63. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  64. };
  65. static const struct ddr_data ddr3_igep0034_lite_data = {
  66. .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  67. .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  68. .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  69. .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  70. };
  71. static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  72. .cmd0csratio = MT41K256M16HA125E_RATIO,
  73. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  74. .cmd1csratio = MT41K256M16HA125E_RATIO,
  75. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  76. .cmd2csratio = MT41K256M16HA125E_RATIO,
  77. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  78. };
  79. static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  80. .cmd0csratio = K4B2G1646EBIH9_RATIO,
  81. .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  82. .cmd1csratio = K4B2G1646EBIH9_RATIO,
  83. .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  84. .cmd2csratio = K4B2G1646EBIH9_RATIO,
  85. .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  86. };
  87. static struct emif_regs ddr3_igep0034_emif_reg_data = {
  88. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  89. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  90. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  91. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  92. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  93. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  94. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  95. };
  96. static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
  97. .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  98. .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  99. .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  100. .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  101. .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  102. .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  103. .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  104. };
  105. const struct ctrl_ioregs ioregs_igep0034 = {
  106. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  107. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  108. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  109. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  110. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  111. };
  112. const struct ctrl_ioregs ioregs_igep0034_lite = {
  113. .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  114. .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  115. .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  116. .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  117. .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  118. };
  119. #define OSC (V_OSCK/1000000)
  120. const struct dpll_params dpll_ddr = {
  121. 400, OSC-1, 1, -1, -1, -1, -1};
  122. const struct dpll_params *get_dpll_ddr_params(void)
  123. {
  124. return &dpll_ddr;
  125. }
  126. void set_uart_mux_conf(void)
  127. {
  128. enable_uart0_pin_mux();
  129. }
  130. void set_mux_conf_regs(void)
  131. {
  132. enable_board_pin_mux();
  133. }
  134. void sdram_init(void)
  135. {
  136. if (get_board_revision() == 1)
  137. config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
  138. &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
  139. else
  140. config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
  141. &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
  142. }
  143. #ifdef CONFIG_SPL_OS_BOOT
  144. int spl_start_uboot(void)
  145. {
  146. /* break into full u-boot on 'c' */
  147. return serial_tstc() && serial_getc() == 'c';
  148. }
  149. #endif
  150. #endif
  151. /*
  152. * Basic board specific setup. Pinmux has been handled already.
  153. */
  154. int board_init(void)
  155. {
  156. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  157. gpmc_init();
  158. return 0;
  159. }
  160. #ifdef CONFIG_BOARD_LATE_INIT
  161. int board_late_init(void)
  162. {
  163. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  164. switch (get_board_revision()) {
  165. case 0:
  166. env_set("board_name", "igep0034-lite");
  167. break;
  168. case 1:
  169. env_set("board_name", "igep0034");
  170. break;
  171. default:
  172. env_set("board_name", "igep0033");
  173. break;
  174. }
  175. #endif
  176. return 0;
  177. }
  178. #endif
  179. #ifdef CONFIG_OF_BOARD_SETUP
  180. int ft_board_setup(void *blob, bd_t *bd)
  181. {
  182. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  183. static const struct node_info nodes[] = {
  184. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  185. };
  186. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  187. #endif
  188. return 0;
  189. }
  190. #endif
  191. #if defined(CONFIG_DRIVER_TI_CPSW)
  192. static void cpsw_control(int enabled)
  193. {
  194. /* VTP can be added here */
  195. return;
  196. }
  197. static struct cpsw_slave_data cpsw_slaves[] = {
  198. {
  199. .slave_reg_ofs = 0x208,
  200. .sliver_reg_ofs = 0xd80,
  201. .phy_addr = 0,
  202. .phy_if = PHY_INTERFACE_MODE_RMII,
  203. },
  204. };
  205. static struct cpsw_platform_data cpsw_data = {
  206. .mdio_base = CPSW_MDIO_BASE,
  207. .cpsw_base = CPSW_BASE,
  208. .mdio_div = 0xff,
  209. .channels = 8,
  210. .cpdma_reg_ofs = 0x800,
  211. .slaves = 1,
  212. .slave_data = cpsw_slaves,
  213. .ale_reg_ofs = 0xd00,
  214. .ale_entries = 1024,
  215. .host_port_reg_ofs = 0x108,
  216. .hw_stats_reg_ofs = 0x900,
  217. .bd_ram_ofs = 0x2000,
  218. .mac_control = (1 << 5),
  219. .control = cpsw_control,
  220. .host_port_num = 0,
  221. .version = CPSW_CTRL_VERSION_2,
  222. };
  223. int board_eth_init(bd_t *bis)
  224. {
  225. int rv, ret = 0;
  226. uint8_t mac_addr[6];
  227. uint32_t mac_hi, mac_lo;
  228. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  229. /* try reading mac address from efuse */
  230. mac_lo = readl(&cdev->macid0l);
  231. mac_hi = readl(&cdev->macid0h);
  232. mac_addr[0] = mac_hi & 0xFF;
  233. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  234. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  235. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  236. mac_addr[4] = mac_lo & 0xFF;
  237. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  238. if (is_valid_ethaddr(mac_addr))
  239. eth_env_set_enetaddr("ethaddr", mac_addr);
  240. }
  241. writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
  242. &cdev->miisel);
  243. if (get_board_revision() == 1)
  244. cpsw_slaves[0].phy_addr = 1;
  245. rv = cpsw_register(&cpsw_data);
  246. if (rv < 0)
  247. printf("Error %d registering CPSW switch\n", rv);
  248. else
  249. ret += rv;
  250. return ret;
  251. }
  252. #endif