gw_ventana_spl.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx6-ddr.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <env.h>
  17. #include <i2c.h>
  18. #include <spl.h>
  19. #include "gsc.h"
  20. #include "common.h"
  21. #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  22. #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
  23. #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
  24. /* configure MX6Q/DUAL mmdc DDR io registers */
  25. struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  26. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  27. .dram_sdclk_0 = 0x00020030,
  28. .dram_sdclk_1 = 0x00020030,
  29. .dram_cas = 0x00020030,
  30. .dram_ras = 0x00020030,
  31. .dram_reset = 0x00020030,
  32. /* SDCKE[0:1]: 100k pull-up */
  33. .dram_sdcke0 = 0x00003000,
  34. .dram_sdcke1 = 0x00003000,
  35. /* SDBA2: pull-up disabled */
  36. .dram_sdba2 = 0x00000000,
  37. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  38. .dram_sdodt0 = 0x00003030,
  39. .dram_sdodt1 = 0x00003030,
  40. /* SDQS[0:7]: Differential input, 40 ohm */
  41. .dram_sdqs0 = 0x00000030,
  42. .dram_sdqs1 = 0x00000030,
  43. .dram_sdqs2 = 0x00000030,
  44. .dram_sdqs3 = 0x00000030,
  45. .dram_sdqs4 = 0x00000030,
  46. .dram_sdqs5 = 0x00000030,
  47. .dram_sdqs6 = 0x00000030,
  48. .dram_sdqs7 = 0x00000030,
  49. /* DQM[0:7]: Differential input, 40 ohm */
  50. .dram_dqm0 = 0x00020030,
  51. .dram_dqm1 = 0x00020030,
  52. .dram_dqm2 = 0x00020030,
  53. .dram_dqm3 = 0x00020030,
  54. .dram_dqm4 = 0x00020030,
  55. .dram_dqm5 = 0x00020030,
  56. .dram_dqm6 = 0x00020030,
  57. .dram_dqm7 = 0x00020030,
  58. };
  59. /* configure MX6Q/DUAL mmdc GRP io registers */
  60. struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  61. /* DDR3 */
  62. .grp_ddr_type = 0x000c0000,
  63. .grp_ddrmode_ctl = 0x00020000,
  64. /* disable DDR pullups */
  65. .grp_ddrpke = 0x00000000,
  66. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  67. .grp_addds = 0x00000030,
  68. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  69. .grp_ctlds = 0x00000030,
  70. /* DATA[00:63]: Differential input, 40 ohm */
  71. .grp_ddrmode = 0x00020000,
  72. .grp_b0ds = 0x00000030,
  73. .grp_b1ds = 0x00000030,
  74. .grp_b2ds = 0x00000030,
  75. .grp_b3ds = 0x00000030,
  76. .grp_b4ds = 0x00000030,
  77. .grp_b5ds = 0x00000030,
  78. .grp_b6ds = 0x00000030,
  79. .grp_b7ds = 0x00000030,
  80. };
  81. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  82. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  83. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  84. .dram_sdclk_0 = 0x00020030,
  85. .dram_sdclk_1 = 0x00020030,
  86. .dram_cas = 0x00020030,
  87. .dram_ras = 0x00020030,
  88. .dram_reset = 0x00020030,
  89. /* SDCKE[0:1]: 100k pull-up */
  90. .dram_sdcke0 = 0x00003000,
  91. .dram_sdcke1 = 0x00003000,
  92. /* SDBA2: pull-up disabled */
  93. .dram_sdba2 = 0x00000000,
  94. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  95. .dram_sdodt0 = 0x00003030,
  96. .dram_sdodt1 = 0x00003030,
  97. /* SDQS[0:7]: Differential input, 40 ohm */
  98. .dram_sdqs0 = 0x00000030,
  99. .dram_sdqs1 = 0x00000030,
  100. .dram_sdqs2 = 0x00000030,
  101. .dram_sdqs3 = 0x00000030,
  102. .dram_sdqs4 = 0x00000030,
  103. .dram_sdqs5 = 0x00000030,
  104. .dram_sdqs6 = 0x00000030,
  105. .dram_sdqs7 = 0x00000030,
  106. /* DQM[0:7]: Differential input, 40 ohm */
  107. .dram_dqm0 = 0x00020030,
  108. .dram_dqm1 = 0x00020030,
  109. .dram_dqm2 = 0x00020030,
  110. .dram_dqm3 = 0x00020030,
  111. .dram_dqm4 = 0x00020030,
  112. .dram_dqm5 = 0x00020030,
  113. .dram_dqm6 = 0x00020030,
  114. .dram_dqm7 = 0x00020030,
  115. };
  116. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  117. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  118. /* DDR3 */
  119. .grp_ddr_type = 0x000c0000,
  120. /* SDQS[0:7]: Differential input, 40 ohm */
  121. .grp_ddrmode_ctl = 0x00020000,
  122. /* disable DDR pullups */
  123. .grp_ddrpke = 0x00000000,
  124. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  125. .grp_addds = 0x00000030,
  126. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  127. .grp_ctlds = 0x00000030,
  128. /* DATA[00:63]: Differential input, 40 ohm */
  129. .grp_ddrmode = 0x00020000,
  130. .grp_b0ds = 0x00000030,
  131. .grp_b1ds = 0x00000030,
  132. .grp_b2ds = 0x00000030,
  133. .grp_b3ds = 0x00000030,
  134. .grp_b4ds = 0x00000030,
  135. .grp_b5ds = 0x00000030,
  136. .grp_b6ds = 0x00000030,
  137. .grp_b7ds = 0x00000030,
  138. };
  139. /* MT41K64M16JT-125 (1Gb density) */
  140. static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
  141. .mem_speed = 1600,
  142. .density = 1,
  143. .width = 16,
  144. .banks = 8,
  145. .rowaddr = 13,
  146. .coladdr = 10,
  147. .pagesz = 2,
  148. .trcd = 1375,
  149. .trcmin = 4875,
  150. .trasmin = 3500,
  151. };
  152. /* MT41K128M16JT-125 (2Gb density) */
  153. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  154. .mem_speed = 1600,
  155. .density = 2,
  156. .width = 16,
  157. .banks = 8,
  158. .rowaddr = 14,
  159. .coladdr = 10,
  160. .pagesz = 2,
  161. .trcd = 1375,
  162. .trcmin = 4875,
  163. .trasmin = 3500,
  164. };
  165. /* MT41K256M16HA-125 (4Gb density) */
  166. static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  167. .mem_speed = 1600,
  168. .density = 4,
  169. .width = 16,
  170. .banks = 8,
  171. .rowaddr = 15,
  172. .coladdr = 10,
  173. .pagesz = 2,
  174. .trcd = 1375,
  175. .trcmin = 4875,
  176. .trasmin = 3500,
  177. };
  178. /* MT41K512M16HA-125 (8Gb density) */
  179. static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
  180. .mem_speed = 1600,
  181. .density = 8,
  182. .width = 16,
  183. .banks = 8,
  184. .rowaddr = 16,
  185. .coladdr = 10,
  186. .pagesz = 2,
  187. .trcd = 1375,
  188. .trcmin = 4875,
  189. .trasmin = 3500,
  190. };
  191. /*
  192. * calibration - these are the various CPU/DDR3 combinations we support
  193. */
  194. static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
  195. /* write leveling calibration determine */
  196. .p0_mpwldectrl0 = 0x004C004E,
  197. .p0_mpwldectrl1 = 0x00440044,
  198. /* Read DQS Gating calibration */
  199. .p0_mpdgctrl0 = 0x42440247,
  200. .p0_mpdgctrl1 = 0x02310232,
  201. /* Read Calibration: DQS delay relative to DQ read access */
  202. .p0_mprddlctl = 0x45424746,
  203. /* Write Calibration: DQ/DM delay relative to DQS write access */
  204. .p0_mpwrdlctl = 0x33382C31,
  205. };
  206. /* TODO: update with calibrated values */
  207. static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
  208. /* write leveling calibration determine */
  209. .p0_mpwldectrl0 = 0x00190017,
  210. .p0_mpwldectrl1 = 0x00140026,
  211. .p1_mpwldectrl0 = 0x0021001C,
  212. .p1_mpwldectrl1 = 0x0011001D,
  213. /* Read DQS Gating calibration */
  214. .p0_mpdgctrl0 = 0x43380347,
  215. .p0_mpdgctrl1 = 0x433C034D,
  216. .p1_mpdgctrl0 = 0x032C0324,
  217. .p1_mpdgctrl1 = 0x03310232,
  218. /* Read Calibration: DQS delay relative to DQ read access */
  219. .p0_mprddlctl = 0x3C313539,
  220. .p1_mprddlctl = 0x37343141,
  221. /* Write Calibration: DQ/DM delay relative to DQS write access */
  222. .p0_mpwrdlctl = 0x36393C39,
  223. .p1_mpwrdlctl = 0x42344438,
  224. };
  225. /* TODO: update with calibrated values */
  226. static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
  227. /* write leveling calibration determine */
  228. .p0_mpwldectrl0 = 0x003C003C,
  229. .p0_mpwldectrl1 = 0x001F002A,
  230. .p1_mpwldectrl0 = 0x00330038,
  231. .p1_mpwldectrl1 = 0x0022003F,
  232. /* Read DQS Gating calibration */
  233. .p0_mpdgctrl0 = 0x42410244,
  234. .p0_mpdgctrl1 = 0x4234023A,
  235. .p1_mpdgctrl0 = 0x022D022D,
  236. .p1_mpdgctrl1 = 0x021C0228,
  237. /* Read Calibration: DQS delay relative to DQ read access */
  238. .p0_mprddlctl = 0x484A4C4B,
  239. .p1_mprddlctl = 0x4B4D4E4B,
  240. /* Write Calibration: DQ/DM delay relative to DQS write access */
  241. .p0_mpwrdlctl = 0x33342B32,
  242. .p1_mpwrdlctl = 0x3933332B,
  243. };
  244. static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
  245. /* write leveling calibration determine */
  246. .p0_mpwldectrl0 = 0x001B0016,
  247. .p0_mpwldectrl1 = 0x000C000E,
  248. /* Read DQS Gating calibration */
  249. .p0_mpdgctrl0 = 0x4324033A,
  250. .p0_mpdgctrl1 = 0x00000000,
  251. /* Read Calibration: DQS delay relative to DQ read access */
  252. .p0_mprddlctl = 0x40403438,
  253. /* Write Calibration: DQ/DM delay relative to DQS write access */
  254. .p0_mpwrdlctl = 0x40403D36,
  255. };
  256. static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
  257. /* write leveling calibration determine */
  258. .p0_mpwldectrl0 = 0x00420043,
  259. .p0_mpwldectrl1 = 0x0016001A,
  260. /* Read DQS Gating calibration */
  261. .p0_mpdgctrl0 = 0x4238023B,
  262. .p0_mpdgctrl1 = 0x00000000,
  263. /* Read Calibration: DQS delay relative to DQ read access */
  264. .p0_mprddlctl = 0x40404849,
  265. /* Write Calibration: DQ/DM delay relative to DQS write access */
  266. .p0_mpwrdlctl = 0x40402E2F,
  267. };
  268. static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
  269. /* write leveling calibration determine */
  270. .p0_mpwldectrl0 = 0x00190017,
  271. .p0_mpwldectrl1 = 0x00140026,
  272. /* Read DQS Gating calibration */
  273. .p0_mpdgctrl0 = 0x43380347,
  274. .p0_mpdgctrl1 = 0x433C034D,
  275. /* Read Calibration: DQS delay relative to DQ read access */
  276. .p0_mprddlctl = 0x3C313539,
  277. /* Write Calibration: DQ/DM delay relative to DQS write access */
  278. .p0_mpwrdlctl = 0x36393C39,
  279. };
  280. static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
  281. /* write leveling calibration determine */
  282. .p0_mpwldectrl0 = 0x003C003C,
  283. .p0_mpwldectrl1 = 0x001F002A,
  284. /* Read DQS Gating calibration */
  285. .p0_mpdgctrl0 = 0x42410244,
  286. .p0_mpdgctrl1 = 0x4234023A,
  287. /* Read Calibration: DQS delay relative to DQ read access */
  288. .p0_mprddlctl = 0x484A4C4B,
  289. /* Write Calibration: DQ/DM delay relative to DQS write access */
  290. .p0_mpwrdlctl = 0x33342B32,
  291. };
  292. static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
  293. /* write leveling calibration determine */
  294. .p0_mpwldectrl0 = 0x00190017,
  295. .p0_mpwldectrl1 = 0x00140026,
  296. .p1_mpwldectrl0 = 0x0021001C,
  297. .p1_mpwldectrl1 = 0x0011001D,
  298. /* Read DQS Gating calibration */
  299. .p0_mpdgctrl0 = 0x43380347,
  300. .p0_mpdgctrl1 = 0x433C034D,
  301. .p1_mpdgctrl0 = 0x032C0324,
  302. .p1_mpdgctrl1 = 0x03310232,
  303. /* Read Calibration: DQS delay relative to DQ read access */
  304. .p0_mprddlctl = 0x3C313539,
  305. .p1_mprddlctl = 0x37343141,
  306. /* Write Calibration: DQ/DM delay relative to DQS write access */
  307. .p0_mpwrdlctl = 0x36393C39,
  308. .p1_mpwrdlctl = 0x42344438,
  309. };
  310. static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
  311. /* write leveling calibration determine */
  312. .p0_mpwldectrl0 = 0x003C003C,
  313. .p0_mpwldectrl1 = 0x001F002A,
  314. .p1_mpwldectrl0 = 0x00330038,
  315. .p1_mpwldectrl1 = 0x0022003F,
  316. /* Read DQS Gating calibration */
  317. .p0_mpdgctrl0 = 0x42410244,
  318. .p0_mpdgctrl1 = 0x4234023A,
  319. .p1_mpdgctrl0 = 0x022D022D,
  320. .p1_mpdgctrl1 = 0x021C0228,
  321. /* Read Calibration: DQS delay relative to DQ read access */
  322. .p0_mprddlctl = 0x484A4C4B,
  323. .p1_mprddlctl = 0x4B4D4E4B,
  324. /* Write Calibration: DQ/DM delay relative to DQS write access */
  325. .p0_mpwrdlctl = 0x33342B32,
  326. .p1_mpwrdlctl = 0x3933332B,
  327. };
  328. static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
  329. /* write leveling calibration determine */
  330. .p0_mpwldectrl0 = 0x001E001A,
  331. .p0_mpwldectrl1 = 0x0026001F,
  332. /* Read DQS Gating calibration */
  333. .p0_mpdgctrl0 = 0x43370349,
  334. .p0_mpdgctrl1 = 0x032D0327,
  335. /* Read Calibration: DQS delay relative to DQ read access */
  336. .p0_mprddlctl = 0x3D303639,
  337. /* Write Calibration: DQ/DM delay relative to DQS write access */
  338. .p0_mpwrdlctl = 0x32363934,
  339. };
  340. static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
  341. /* write leveling calibration determine */
  342. .p0_mpwldectrl0 = 0X00480047,
  343. .p0_mpwldectrl1 = 0X003D003F,
  344. /* Read DQS Gating calibration */
  345. .p0_mpdgctrl0 = 0X423E0241,
  346. .p0_mpdgctrl1 = 0X022B022C,
  347. /* Read Calibration: DQS delay relative to DQ read access */
  348. .p0_mprddlctl = 0X49454A4A,
  349. /* Write Calibration: DQ/DM delay relative to DQS write access */
  350. .p0_mpwrdlctl = 0X2E372C32,
  351. };
  352. static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
  353. /* write leveling calibration determine */
  354. .p0_mpwldectrl0 = 0X00220021,
  355. .p0_mpwldectrl1 = 0X00200030,
  356. .p1_mpwldectrl0 = 0X002D0027,
  357. .p1_mpwldectrl1 = 0X00150026,
  358. /* Read DQS Gating calibration */
  359. .p0_mpdgctrl0 = 0x43330342,
  360. .p0_mpdgctrl1 = 0x0339034A,
  361. .p1_mpdgctrl0 = 0x032F0325,
  362. .p1_mpdgctrl1 = 0x032F022E,
  363. /* Read Calibration: DQS delay relative to DQ read access */
  364. .p0_mprddlctl = 0X3A2E3437,
  365. .p1_mprddlctl = 0X35312F3F,
  366. /* Write Calibration: DQ/DM delay relative to DQS write access */
  367. .p0_mpwrdlctl = 0X33363B37,
  368. .p1_mpwrdlctl = 0X40304239,
  369. };
  370. static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
  371. /* write leveling calibration determine */
  372. .p0_mpwldectrl0 = 0x0048004A,
  373. .p0_mpwldectrl1 = 0x003F004A,
  374. .p1_mpwldectrl0 = 0x001E0028,
  375. .p1_mpwldectrl1 = 0x002C0043,
  376. /* Read DQS Gating calibration */
  377. .p0_mpdgctrl0 = 0x02250219,
  378. .p0_mpdgctrl1 = 0x01790202,
  379. .p1_mpdgctrl0 = 0x02080208,
  380. .p1_mpdgctrl1 = 0x016C0175,
  381. /* Read Calibration: DQS delay relative to DQ read access */
  382. .p0_mprddlctl = 0x4A4C4D4C,
  383. .p1_mprddlctl = 0x494C4A48,
  384. /* Write Calibration: DQ/DM delay relative to DQS write access */
  385. .p0_mpwrdlctl = 0x403F3437,
  386. .p1_mpwrdlctl = 0x383A3930,
  387. };
  388. static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
  389. /* write leveling calibration determine */
  390. .p0_mpwldectrl0 = 0x001F003F,
  391. .p0_mpwldectrl1 = 0x001F001F,
  392. .p1_mpwldectrl0 = 0x001F004E,
  393. .p1_mpwldectrl1 = 0x0059001F,
  394. /* Read DQS Gating calibration */
  395. .p0_mpdgctrl0 = 0x42220225,
  396. .p0_mpdgctrl1 = 0x0213021F,
  397. .p1_mpdgctrl0 = 0x022C0242,
  398. .p1_mpdgctrl1 = 0x022C0244,
  399. /* Read Calibration: DQS delay relative to DQ read access */
  400. .p0_mprddlctl = 0x474A4C4A,
  401. .p1_mprddlctl = 0x48494C45,
  402. /* Write Calibration: DQ/DM delay relative to DQS write access */
  403. .p0_mpwrdlctl = 0x3F3F3F36,
  404. .p1_mpwrdlctl = 0x3F36363F,
  405. };
  406. static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
  407. /* write leveling calibration determine */
  408. .p0_mpwldectrl0 = 0x001F003F,
  409. .p0_mpwldectrl1 = 0x001F001F,
  410. .p1_mpwldectrl0 = 0x001F004E,
  411. .p1_mpwldectrl1 = 0x0059001F,
  412. /* Read DQS Gating calibration */
  413. .p0_mpdgctrl0 = 0x42220225,
  414. .p0_mpdgctrl1 = 0x0213021F,
  415. .p1_mpdgctrl0 = 0x022C0242,
  416. .p1_mpdgctrl1 = 0x022C0244,
  417. /* Read Calibration: DQS delay relative to DQ read access */
  418. .p0_mprddlctl = 0x474A4C4A,
  419. .p1_mprddlctl = 0x48494C45,
  420. /* Write Calibration: DQ/DM delay relative to DQS write access */
  421. .p0_mpwrdlctl = 0x3F3F3F36,
  422. .p1_mpwrdlctl = 0x3F36363F,
  423. };
  424. static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
  425. /* write leveling calibration determine */
  426. .p0_mpwldectrl0 = 0x002A0025,
  427. .p0_mpwldectrl1 = 0x003A002A,
  428. /* Read DQS Gating calibration */
  429. .p0_mpdgctrl0 = 0x43430356,
  430. .p0_mpdgctrl1 = 0x033C0335,
  431. /* Read Calibration: DQS delay relative to DQ read access */
  432. .p0_mprddlctl = 0x4B373F42,
  433. /* Write Calibration: DQ/DM delay relative to DQS write access */
  434. .p0_mpwrdlctl = 0x303E3C36,
  435. };
  436. static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
  437. /* write leveling calibration determine */
  438. .p0_mpwldectrl0 = 0x00230020,
  439. .p0_mpwldectrl1 = 0x002F002A,
  440. .p1_mpwldectrl0 = 0x001D0027,
  441. .p1_mpwldectrl1 = 0x00100023,
  442. /* Read DQS Gating calibration */
  443. .p0_mpdgctrl0 = 0x03250339,
  444. .p0_mpdgctrl1 = 0x031C0316,
  445. .p1_mpdgctrl0 = 0x03210331,
  446. .p1_mpdgctrl1 = 0x031C025A,
  447. /* Read Calibration: DQS delay relative to DQ read access */
  448. .p0_mprddlctl = 0x40373C40,
  449. .p1_mprddlctl = 0x3A373646,
  450. /* Write Calibration: DQ/DM delay relative to DQS write access */
  451. .p0_mpwrdlctl = 0x2E353933,
  452. .p1_mpwrdlctl = 0x3C2F3F35,
  453. };
  454. static void spl_dram_init(int width, int size_mb, int board_model)
  455. {
  456. struct mx6_ddr3_cfg *mem = NULL;
  457. struct mx6_mmdc_calibration *calib = NULL;
  458. struct mx6_ddr_sysinfo sysinfo = {
  459. /* width of data bus:0=16,1=32,2=64 */
  460. .dsize = width/32,
  461. /* config for full 4GB range so that get_mem_size() works */
  462. .cs_density = 32, /* 32Gb per CS */
  463. /* single chip select */
  464. .ncs = 1,
  465. .cs1_mirror = 0,
  466. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  467. #ifdef RTT_NOM_120OHM
  468. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  469. #else
  470. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  471. #endif
  472. .walat = 1, /* Write additional latency */
  473. .ralat = 5, /* Read additional latency */
  474. .mif3_mode = 3, /* Command prediction working mode */
  475. .bi_on = 1, /* Bank interleaving enabled */
  476. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  477. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  478. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  479. .ddr_type = DDR_TYPE_DDR3,
  480. .refsel = 1, /* Refresh cycles at 32KHz */
  481. .refr = 7, /* 8 refresh commands per refresh cycle */
  482. };
  483. /*
  484. * MMDC Calibration requires the following data:
  485. * mx6_mmdc_calibration - board-specific calibration (routing delays)
  486. * these calibration values depend on board routing, SoC, and DDR
  487. * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
  488. * mx6_ddr_cfg - chip specific timing/layout details
  489. */
  490. if (width == 16 && size_mb == 128) {
  491. mem = &mt41k64m16jt_125;
  492. if (is_cpu_type(MXC_CPU_MX6Q))
  493. ;
  494. else
  495. calib = &mx6sdl_64x16_mmdc_calib;
  496. debug("1gB density\n");
  497. } else if (width == 16 && size_mb == 256) {
  498. /* 1x 2Gb density chip - same calib as 2x 2Gb */
  499. mem = &mt41k128m16jt_125;
  500. if (is_cpu_type(MXC_CPU_MX6Q))
  501. calib = &mx6dq_128x32_mmdc_calib;
  502. else
  503. calib = &mx6sdl_128x32_mmdc_calib;
  504. debug("2gB density\n");
  505. } else if (width == 16 && size_mb == 512) {
  506. mem = &mt41k256m16ha_125;
  507. if (is_cpu_type(MXC_CPU_MX6Q))
  508. calib = &mx6dq_256x16_mmdc_calib;
  509. else
  510. calib = &mx6sdl_256x16_mmdc_calib;
  511. debug("4gB density\n");
  512. } else if (width == 16 && size_mb == 1024) {
  513. mem = &mt41k512m16ha_125;
  514. if (is_cpu_type(MXC_CPU_MX6Q))
  515. calib = &mx6dq_512x32_mmdc_calib;
  516. debug("8gB density\n");
  517. } else if (width == 32 && size_mb == 256) {
  518. /* Same calib as width==16, size==128 */
  519. mem = &mt41k64m16jt_125;
  520. if (is_cpu_type(MXC_CPU_MX6Q))
  521. ;
  522. else
  523. calib = &mx6sdl_64x16_mmdc_calib;
  524. debug("1gB density\n");
  525. } else if (width == 32 && size_mb == 512) {
  526. mem = &mt41k128m16jt_125;
  527. if (is_cpu_type(MXC_CPU_MX6Q))
  528. calib = &mx6dq_128x32_mmdc_calib;
  529. else
  530. calib = &mx6sdl_128x32_mmdc_calib;
  531. debug("2gB density\n");
  532. } else if (width == 32 && size_mb == 1024) {
  533. mem = &mt41k256m16ha_125;
  534. if (is_cpu_type(MXC_CPU_MX6Q))
  535. calib = &mx6dq_256x32_mmdc_calib;
  536. else
  537. calib = &mx6sdl_256x32_mmdc_calib;
  538. debug("4gB density\n");
  539. } else if (width == 32 && size_mb == 2048) {
  540. mem = &mt41k512m16ha_125;
  541. if (is_cpu_type(MXC_CPU_MX6Q))
  542. calib = &mx6dq_512x32_mmdc_calib;
  543. debug("8gB density\n");
  544. } else if (width == 64 && size_mb == 512) {
  545. mem = &mt41k64m16jt_125;
  546. debug("1gB density\n");
  547. if (is_cpu_type(MXC_CPU_MX6Q))
  548. calib = &mx6dq_64x64_mmdc_calib;
  549. else
  550. calib = &mx6sdl_64x64_mmdc_calib;
  551. } else if (width == 64 && size_mb == 1024) {
  552. mem = &mt41k128m16jt_125;
  553. if (is_cpu_type(MXC_CPU_MX6Q))
  554. calib = &mx6dq_128x64_mmdc_calib;
  555. else
  556. calib = &mx6sdl_128x64_mmdc_calib;
  557. debug("2gB density\n");
  558. } else if (width == 64 && size_mb == 2048) {
  559. switch(board_model) {
  560. case GW5905:
  561. /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
  562. mem = &mt41k128m16jt_125;
  563. debug("2gB density - 2 chipsel\n");
  564. if (!is_cpu_type(MXC_CPU_MX6Q)) {
  565. calib = &mx6sdl_128x64x2_mmdc_calib;
  566. sysinfo.ncs = 2;
  567. sysinfo.cs_density = 10; /* CS0_END=39 */
  568. sysinfo.cs1_mirror = 1; /* mirror enabled */
  569. }
  570. break;
  571. default:
  572. mem = &mt41k256m16ha_125;
  573. if (is_cpu_type(MXC_CPU_MX6Q))
  574. calib = &mx6dq_256x64_mmdc_calib;
  575. else
  576. calib = &mx6sdl_256x64_mmdc_calib;
  577. debug("4gB density\n");
  578. break;
  579. }
  580. } else if (width == 64 && size_mb == 4096) {
  581. switch(board_model) {
  582. case GW5903:
  583. /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
  584. mem = &mt41k256m16ha_125;
  585. debug("4gB density - 2 chipsel\n");
  586. if (!is_cpu_type(MXC_CPU_MX6Q)) {
  587. calib = &mx6sdl_256x64x2_mmdc_calib;
  588. sysinfo.ncs = 2;
  589. sysinfo.cs_density = 18; /* CS0_END=71 */
  590. sysinfo.cs1_mirror = 1; /* mirror enabled */
  591. }
  592. break;
  593. default:
  594. mem = &mt41k512m16ha_125;
  595. if (is_cpu_type(MXC_CPU_MX6Q))
  596. calib = &mx6dq_512x64_mmdc_calib;
  597. debug("8gB density\n");
  598. break;
  599. }
  600. }
  601. if (!(mem && calib)) {
  602. puts("Error: Invalid Calibration/Board Configuration\n");
  603. printf("MEM : %s\n", mem ? "OKAY" : "NULL");
  604. printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
  605. printf("CPUTYPE: %s\n",
  606. is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
  607. printf("SIZE_MB: %d\n", size_mb);
  608. printf("WIDTH : %d\n", width);
  609. hang();
  610. }
  611. if (is_cpu_type(MXC_CPU_MX6Q))
  612. mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
  613. &mx6dq_grp_ioregs);
  614. else
  615. mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
  616. &mx6sdl_grp_ioregs);
  617. mx6_dram_cfg(&sysinfo, calib, mem);
  618. }
  619. static void ccgr_init(void)
  620. {
  621. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  622. writel(0x00C03F3F, &ccm->CCGR0);
  623. writel(0x0030FC03, &ccm->CCGR1);
  624. writel(0x0FFFC000, &ccm->CCGR2);
  625. writel(0x3FF00000, &ccm->CCGR3);
  626. writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
  627. writel(0x0F0000C3, &ccm->CCGR5);
  628. writel(0x000003FF, &ccm->CCGR6);
  629. }
  630. /*
  631. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  632. * - we have a stack and a place to store GD, both in SRAM
  633. * - no variable global data is available
  634. */
  635. void board_init_f(ulong dummy)
  636. {
  637. struct ventana_board_info ventana_info;
  638. int board_model;
  639. /* setup clock gating */
  640. ccgr_init();
  641. /* setup AIPS and disable watchdog */
  642. arch_cpu_init();
  643. /* setup AXI */
  644. gpr_init();
  645. /* iomux and setup of uart/i2c */
  646. setup_iomux_uart();
  647. setup_ventana_i2c(0);
  648. setup_ventana_i2c(1);
  649. /* setup GP timer */
  650. timer_init();
  651. /* UART clocks enabled and gd valid - init serial console */
  652. preloader_console_init();
  653. /* read/validate EEPROM info to determine board model and SDRAM cfg */
  654. board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  655. /* configure model-specific gpio */
  656. setup_iomux_gpio(board_model, &ventana_info);
  657. /* provide some some default: 32bit 128MB */
  658. if (GW_UNKNOWN == board_model)
  659. hang();
  660. /* configure MMDC for SDRAM width/size and per-model calibration */
  661. spl_dram_init(8 << ventana_info.sdram_width,
  662. 16 << ventana_info.sdram_size,
  663. board_model);
  664. }
  665. void board_boot_order(u32 *spl_boot_list)
  666. {
  667. spl_boot_list[0] = spl_boot_device();
  668. switch (spl_boot_list[0]) {
  669. case BOOT_DEVICE_NAND:
  670. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  671. spl_boot_list[2] = BOOT_DEVICE_UART;
  672. break;
  673. case BOOT_DEVICE_MMC1:
  674. spl_boot_list[1] = BOOT_DEVICE_UART;
  675. break;
  676. }
  677. }
  678. /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
  679. /* its our chance to print info about boot device */
  680. void spl_board_init(void)
  681. {
  682. /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
  683. u32 boot_device = spl_boot_device();
  684. switch (boot_device) {
  685. case BOOT_DEVICE_MMC1:
  686. puts("Booting from MMC\n");
  687. break;
  688. case BOOT_DEVICE_NAND:
  689. puts("Booting from NAND\n");
  690. break;
  691. case BOOT_DEVICE_SATA:
  692. puts("Booting from SATA\n");
  693. break;
  694. default:
  695. puts("Unknown boot device\n");
  696. }
  697. /* PMIC init */
  698. setup_pmic();
  699. }
  700. #ifdef CONFIG_SPL_OS_BOOT
  701. /* return 1 if we wish to boot to uboot vs os (falcon mode) */
  702. int spl_start_uboot(void)
  703. {
  704. unsigned char ret = 1;
  705. debug("%s\n", __func__);
  706. #ifdef CONFIG_SPL_ENV_SUPPORT
  707. env_init();
  708. env_load();
  709. debug("boot_os=%s\n", env_get("boot_os"));
  710. if (env_get_yesno("boot_os") == 1)
  711. ret = 0;
  712. #else
  713. /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
  714. i2c_set_bus_num(0);
  715. gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
  716. #endif
  717. if (!ret)
  718. gsc_boot_wd_disable();
  719. debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
  720. return ret;
  721. }
  722. #endif